Add 'pci_map_bus' function and PCIE_QCOM config for Qualcomm platform.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57615
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PCIe domain support for herobrine by enabling it in the devicetree.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: Ied8fbbc8d20698ee081d93ba184b7d0291bb6a76
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65137
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disabling the Package C-state demotion feature for brya baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.
This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This adds SPDX-License-Identifiers to all of the files in src/include
that are missing them or have unrecognized identifiers.
Files that were written specifically for coreboot and don't have license
information are licensed GPL-2.0-only, which is the license for the
overall coreboot project.
Files that were sourced from Linux are similarly GPL-2.0-only.
The cpu/power files were committed with source that was licensed as
GPL-2.0-or-later, so presumably that's the license for that entire
commit.
The final file, vbe.h gives a pointer to the BSD-2-Clause license
at opensource.org.
Change-Id: I3f8fd7848ce11c1a0060e05903fb17a7583b4725
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035.
Reason for revert: Now that PSP supports a soft fuse flag to toggle the
verstage serial logs, prevent PSP verstage from writing to the UART.
BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP
verstage logs are not seen twice in the console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
HW Modexp engine is verified to be working fine. Any verification
failures during PSP verstage are because the firmware body is not read
correctly. This might be because of the incorrect SPI ROM mapping. Hence
enable the HW modexp engine for keyblock, preamble and firmware body
verification.
BUG=b:240175446
TEST=Build and boot to OS in Skyrim with PSP verstage using one of the
FW slots.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8f6742630a7049354a24053fce28c477e53259e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This is required to enable PSP verstage on SoCs with recovery A/B
layout.
BUG=b:217414563
TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2
directory. Build and boot to OS in Skyrim with both PSP and x86
verstage.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Update MrChromebox’ default branch from uefipayload_202107 to
uefipayload_202207.
This is based on upstream edk2, commit f26b70c (UefiPayloadPkg:
Add support for logging to CBMEM console).
Tested on:
* StarBook Mk V
* StarLite Mk III
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I16a012485e4b4957439e776914ffd016b4506a47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66083
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
SMMSTORE support in edk2 was not allowed in upstream edk2
as it was bootloader specific.
Shortly, it will be built from edk2-platforms and then,
it will be retired.
For now, the patches exist in the MrChromeBox fork (TIANOCORE_UEFIPAYLOAD), so enable
these by default when SMMSTORE_v2 is enabled.
Change-Id: I1861bf739c2e25f661b4f06a303348f0537dc8b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65867
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow passing custom build parameters to any version of edk2, not
just forks.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4eed535415ba15ae73e22cada9153820538f5f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
- Move configs for PCIe ports not present on z220_sff_workstation
from the devicetree.cb of base board to the overridetree.cb of
z220_cmt_workstation.
- Add a note for ME/AMT Flash Override jumper, for it is hard to
flash from OEM firmware either internally or externally without
closing this jumper.
- Add a side note for similar HP Compaq Elite 8300 SFF.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DPTF Policy and temperature sensor values from thermal team.
BUG=b:236294162
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Iebcfb74c4bc719e6d8d8d9317435becd912eaf85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
futility now supports image truncation and signing of whole images with
a single command invocation. Use it for vboot-enabled coreboot images.
TEST=Build and run coreboot on google/volteer
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I49eb7e977b635ccb9f6c1b76e53c36e82be1d795
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch enables display port configuration as per the Rex
schematics.
TEST=Able to dump FSP UPD to ensure the override is successful.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e81d037416e46e52cb72344425d6d8725dae192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Pujjoflex support OZ711LV2LN SD card controller,
Select the Bayhub LV2 driver for OZ711LV2LN SD card.
BUG=b:215487382
TEST=Build FW and checking SD card work as expected in OS.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I6759fde1eaf24599a1fdb364d6e78f4e4e12f311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
The gpios and the tick delay register are different between MT8188
and previous MediaTek SoCs, so we need to add this patch to support
SPI.
TEST=build pass
BUG=b:236331724
Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com>
Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which
is different from previous SoCs, so we define a macro to get the
designated register.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the common definitions to rtc_reg_common.h, so we can reuse those
definitions on MT8188.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AUXADC register definitions are the same for all MediaTek SoCs, so
we move struct mtk_auxadc_regs to auxadc_common.h.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Remove the parameter and set I2C bus speed to fast. Will fill the
tuning value after real tuning.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iba7fe4551959617ecfa49719c1124bf85d624c31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Create the gaelin variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:239514438
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_GAELIN
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Add TDP and Power Limit settings for ADL-S 8+8 150W, 4+0 and 2+0.
The System Agent PCI IDs were not present in older 2.1 revision of
DOC #619501. Now that the mapping of these IDs to SKUs is known, fill
the missing TDPs and Power Limit settings based on DOC #626343.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I23dd8478e60bcc81a1048f2f6e6717dd281d1a69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Add missing System Agent PCI IDs for ADL-S 4+0 and 2+0 to configure
VccIn Aux Imon IccMax. They were not present in older 2.1 revision of
DOC #619501. Based on DOC #619501 rev 2.6.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Idfd57ce9b63db5d5fcc9d4efb8aa27ed7cc6222d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The patch updates platform_is_resuming() API such that platform resume
state is determined from the saved state (CBMEM) instead of checking PMC
registers (PM1_STS & PM1_CNT) as they are getting cleared (before/early)
ramstage.
coreboot sends DISCONNECT IPC command which times out during resume (S3)
if system has servoV4 connected on port0. The issue occurs only during
the first cycle of resume (S3) test cycle after cold boot due to side
effect of platform_is_resuming() API that is not determining the resume
(S3) state correctly in ramstage.
PM1_STS and PM1_CNT register gets cleared at the start of ramstage.
platform_is_resuming() function was checks the cleared register value
and fails the condition of resume (S3) resulting in sending DISCONNECT
IPC command. Checking the platform resume state from the CBMEM saved
state using acpe_get_sleep_type() function helps cross verify the
system previous state at the later part of ramstage.
localhost ~ # cbmem -c | grep ERROR
[ERROR] EC returned error result code 3
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:0 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:1 to initial state
[ERROR] GENERIC: 0.0 missing read_resources
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0xd0 failed
[ERROR] PMC: Failed sending PCI Enumeration Done Command
BUG=b:227289581
TEST=Verified system boots to OS and verified below tests on
Redrix (ADL-P) and Nivviks (ADL-N)
1. coreboot doesn't send the DISCONNECT during S3 resume
2. suspend S3 passes with both suzyq and servoV4 connected
3. After S3 resume, system detects the pen drive with Superspeed
4. After system resumes from S3, hot-plug the pen drive, system detects
the pen drive
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I353ab49073bc4b5288943e19a75efa04bd809227
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66126
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add weida touchscreen support for drawcia.
BRANCH=dedede
TEST=Build and verify that touchscreen works on drawcia.
Change-Id: Ic76f3529771c6eeeafef7ca50fc400065aac2211
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65471
Reviewed-by: Ivan Chen <yulunchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
set i2c address to 0x14 for Goodix touchscreen
BUG=b:239180430
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I11a2d9c684bc511b3942f88f74a2495e796bc3c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
When the dGPU is entering GCOFF, the link should first be placed into
L2/L3 as appropriate for the design, then when exiting, the link should
be placed back into L0. This patch fixes that oversight.
BUG=b:239719056
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Prasad Malisetty