Since vboot_extend_pcr() returns vb2_error_t, the return type of
extend_pcrs() should be vb2_error_t too.
Also fix an assignment for vboot_locate_firmware(), which returns int
instead of vb2_error_t.
Change-Id: I1a2a2a66f3e594aba64d33cfc532d1bd88fa305e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For GICD and GICR a SOC needs to implement 2 callbacks to get the base
of those interrupt controllers.
For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3
devices in a similar fashion to how x86 lapics are added. It's up to the
SOC to add those devices to the tree.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Linux v6.3.5 is able to detect and use ACPI tables on an out of tree
target using hacked version of u-boot to pass ACPI through UEFI.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4f60c546ec262ffb4d447fe6476844cf5a1b756d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76071
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
data_fabric_disable_mmio_reg and data_fabric_find_unused_mmio_reg are
only used by data_fabric_set_mmio_np in the same file, so make them
static and drop the prototype from the header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6bf7a868aae2fd01b8adecd3e4cba6ff6d5119af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
coreboot offers two vboot schemes VBOOT_SLOTS_RW_A and
VBOOT_SLOTS_RW_AB. When VBOOT_SLOTS_RW_AB is not selected then the
resulting image is rather not expected to have the FW_MAIN_B FMAP
region. When only RW_A region is used, vboot does additional full_reset
cycles to try RW_B, even though it does not exist / the build was not
configured for two RW partitions. To avoid it, a new vboot context
flag has been introduced, VB2_CONTEXT_SLOT_A_ONLY, which can be set
right after context initialization to inform vboot about absence of
slot B. This will result in less full_reset cycles when vboot runs
out of available slots and cause vboot to switch to recovery mode
faster.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie123881a2f9f766ae65e4ac7c36bc2a8fce8d100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75462
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With commit b7832de026 ("x86: Add .data
section support for pre-memory stages"), this comment is not correct
anymore and should be removed.
Change-Id: I61597841cd3f90cebe7323a68738f91d6d64b33d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
With commit b7832de026 ("x86: Add .data
section support for pre-memory stages"), the libhwbase and libgfxinit
.data symbols can be moved to the .data section.
Change-Id: I302391e7bc8cb4739e5801d360c57776b0e3eff6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
With commit b7832de026 ("x86: Add .data
section support for pre-memory stages"), the `ENV_HAS_DATA_SECTION'
flag and its derivatives can now be removed from the code.
Change-Id: Ic0afac76264a9bd4a9c93ca35c90bd84e9b747a2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77291
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit dc7cc5bc6e ("mb/google/skyrim: Disable
USE_SELECTIVE_GOP_INIT") but limits the default enablement to Skyrim
variant only, to allow for continued testing.
BUG=b:271850970
BRANCH=skyrim
TEST=build/boot ChromeOS R117+ on google/skyrim, verify no display init
failures with feature enabled on cold/warm boots or S0i3 resume.
Change-Id: I21c70111a5f407a7e8dd1ad1f2c2759ddb91893e
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Added Raptor Lake U graphics device ids.
Renamed Raptor Lake U graphics device ids that were marked as
Raptor Lake P.
Added Raptor Lake P graphics device ids.
References:
RaptorLake External Design Specification Volume 1 (640555)
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I44734f927764f872b89e3805a47d16c1ffa28865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77898
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
cpu_cl_cleanup() function checks if the SOC supports storage-off
feature. This feature allows to turn off PUNIT SSRAM to save power.
Enable the storage-off if it's supported. Enabling it also clears the
crashlog records from PUNIT SSRAM.
cpu_cl_rearm() function rearms the CPU crashlog.
BUG=b:262501347
TEST=Able to build google/rex. Verified both features get asserted.
Change-Id: Id9ba0f5db0b5d2bd57a7a21f178ef1e86ca63fae
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77239
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add more details in CPU crashlog header structure, such as
storage off status and support, re-arm status etc. These fields
are used to check of particular feature is supported or not and
if supported what is the status of the feature.
BUG=b:262501347
TEST=Able to build google/rex.
Change-Id: I4242b6043b8f8ad9212780f44ca0448cd2b6b9f8
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77562
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all SOC follow the same programming to clear crashlog
data. So make common implementation of cpu_cl_clear_data()
weak.
BUG=b:262501347
TEST=Able to build google/rex.
Change-Id: Ic2b4631d57703abff0ab1880fb272ef67bb1b8e9
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
relanding original commit 5013c60a87
("soc/intel/meteorlake: Generate new TME key on each warm boot") which was previously reverted by commit 19e66b7c95
(Revert "soc/intel/meteorlake: Generate new TME key on each warm boot")
due to consecutive reboot post warm reset issue.
The consecutive reboot post warm reboot issue has been fixed with
commit ba7a9eefcf ("soc/intel/common: Fix
invalid MADT entries creation"), hence, reattempting to land the original TME key related patch.
BUG=299294328
TEST=Boot up the system, generate kernel crash using following
commands:
$ echo 1 > /proc/sys/kernel/sysrq
$ echo "c" > /proc/sysrq-trigger
System performs warm boot automatically. Once it is booted,
execute following commands in linux console of the DUT and confirm
ramoops can be read.
$ cat /sys/fs/pstore/console-ramoops-0
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I5d45d265ccef1a7d37669ea22a74b52e2f3ae20d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch eliminates the need to maintain separate FMD files for rex
variants and rex variants with ISH. It does this by using the
BOARD_GOOGLE_MODEL_REX_EC_ISH config to differentiate between ME-RW
layout sizes.
TEST=Able to build and boot google/rex and google/rex_ec_ish.
Change-Id: Ibb6ee9aad9fb68198c6c1a1d5978f77d53a2e3ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77895
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 449c6d981c.
Reason for revert: (EVT board build does not exhibit shutdown followed
by warm reboot)
This commit reverts the workaround that limits the TCC activation
temperature. The original issue that was reported (shutdown followed
by warm reboot) was not seen in the EVT board build, so this change is
likely unnecessary.
Change-Id: I22adcdee6512e57ad0b6d531f2611e22a95c863e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips
initial probe during kernel boot and prevent privacy LED blink.
TEST=Boot to OS, check camera LEDs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib9375d602171aa5018b1add1deac3021724dc207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC is added to mipi camera
driver to extend the same support for all SoCs, so removing this config
from Alderlake SoC code.
BUG=None
TEST=Build rex and brya to check if the build passes without an
error.
Change-Id: I5bc23fce89f0ae22b64b90cb12621320cac30d85
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Some of our documentation still points to the wrong branches
Change-Id: Idb72e4f44f294f64eb01c588027d300a53d6fb41
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77875
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add fw_config - DB_1A_HDMI for craaskana, and disable C1 PMC mux conn
for HDMI.
BUG=b:296791122
TEST=build and check HDMI function works on craaskana
Change-Id: Ibaa0cd917a23b7f670ecd648765d1eb566edfe61
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77890
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Move the existing FSP 4221.00 headers for Raptor Lake to a
subdirectory called 4221.00_google, and select this if the
vendor is Google.
Add the standard FSP 4301.01 headers to a separate directory,
from Intel download #686654, and select this for all other
vendors.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icd99bdee1eeac70dfcaca3d07150d3de6bb83d81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77101
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add some noop device_operations for devices below chip drivers/pc80/tpm
in the case CONFIG_TPM is unset. This avoids the warning "... missing
read_resources" when probing all devices for resources.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ibc37642a8b5f37b95c648141e03025a04ffa36bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77386
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are going to be skus without stylus and fingerprint module.
Disable stylus and fingerprint module based on fw_config.
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: I047aae06c4a915d0392edc836757b882a261c178
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77647
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:264960828
TEST=On dibbi, ACPI tables contain entries for USB 3.4 and 3.5
Change-Id: If3266d356a2deaf42aa0943f85593416d80637ad
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
UWB on Rex will have 2 options to connect to the SoC:
1. Through GSPI1 (muxed with FP)
2. bit-bang over GPP
This CL adds GSPI1 option. BB may be added later.
BUG=b:263413448, b:263499898
TEST=UWB ranging works on Rex with this CL
Change-Id: I93b3bcef84d775866df43d00c934f013e9f85c47
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76665
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Kuldax-refresh use USB Hub, add fw_config probe for USB Hub.
BUG=b:275335023
BRANCH=brya
TEST=Built and check firmware log.
Change-Id: Ib983ca527a891718f317336597faad66d076247f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The PMC and P2SB IDs for Raptor Lake-S PCH were missing. Add them based
on doc 619362 rev 2.2.
Change-Id: I5de00adf2d87cf50571abb02b28e7feebdc3911e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77448
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch addresses the increased boot time issue that occurs when ISH
store is enabled, such as in the "rex4es_ec_ish" variant.
During a cold reboot, the CBMEM memory resets and loses the stored
firmware versions. This causes the firmware versions to be fetched again
from the CSE, which increases the boot time by about 200 ms. This patch
stores a backup of the firmware version in CMOS and updates the CBMEM
memory during a cold reboot.
BUG=b:280722061
Test=Verified the changes on rex board.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75755
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements APIs to access the CSE FW partition versions in
CMOS. The get API allows users to retrieve the current version from
CMOS memory. The set API allows users to set the version in CMOS
memory.
BUG=b:280722061
TEST=APIs verified on rex board.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Remove the check to follow the new flow that commit 9c348a7b7e
("soc/intel/alderlake: Fix processor hang while plug unplug of
TBT device") introduced.
Processor hang is observed while hot plug unplug of TBT device. BIOS
should execute TBT PCIe RP RTD3 flow based on the value of
TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if
BIT30 in TBT FW version is not set.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie822b8e1fd7592a31275db8455519c4cc6ac02ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The memory log we get returned by QcLib contains Windows line endings
("\r\n"), while we prefer to have POSIX line endings in the CBMEM
console (just "\n"). Filter the '\r' character out when copying that log
into the CBMEM console to convert.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0652300c2393fbc0b3c9875bb0ca1aa921e59098
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77722
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
x86 pre-memory stages do not support the `.data` section and as a
result developers are required to include runtime initialization code
instead of relying on C global variable definition.
To illustrate the impact of this lack of `.data` section support, here
are two limitations I personally ran into:
1. The inclusion of libgfxinit in romstage for Raptor Lake has
required some changes in libgfxinit to ensure data is initialized at
runtime. In addition, we had to manually map some `.data` symbols in
the `_bss` region.
2. CBFS cache is currently not supported in pre-memory stages and
enabling it would require to add an initialization function and
find a generic spot to call it.
Other platforms do not have that limitation. Hence, resolving it would
help to align code and reduce compilation based restriction (cf. the
use of `ENV_HAS_DATA_SECTION` compilation flag in various places of
coreboot code).
We identified three cases to consider:
1. eXecute-In-Place pre-memory stages
- code is in SPINOR
- data is also stored in SPINOR but must be linked in Cache-As-RAM
and copied there at runtime
2. `bootblock` stage is a bit different as it uses Cache-As-Ram but
the memory mapping and its entry code different
3. pre-memory stages loaded in and executed from
Cache-As-RAM (cf. `CONFIG_NO_XIP_EARLY_STAGES`).
eXecute-In-Place pre-memory stages (#1) require the creation of a new
ELF segment as the code segment Virtual Memory Address and Load Memory
Address are identical but the data needs to be linked in
cache-As-RAM (VMA) but to be stored right after the code (LMA).
Here is the output `readelf --segments` on a `romstage.debug` ELF
binary.
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000080 0x02000000 0x02000000 0x21960 0x21960 R E 0x20
LOAD 0x0219e0 0xfefb1640 0x02021960 0x00018 0x00018 RW 0x4
Section to Segment mapping:
Segment Sections...
00 .text
01 .data
Segment 0 `VirtAddr` and `PhysAddr` are at the same address while they
are totally different for the Segment 1 holding the `.data`
section. Since we need the data section `VirtAddr` to be in the
Cache-As-Ram and its `PhysAddr` right after the `.text` section, the
use of a new segment is mandatory.
`bootblock` (#2) also uses this new segment to store the data right
after the code and load it to Cache-As-RAM at runtime. However, the
code involved is different.
Not eXecute-In-Place pre-memory stages (#3) do not really need any
special work other than enabling a data section as the code and data
VMA / LMA translation vector is the same.
TEST=#1 and #2 verified on rex and qemu 32 and 64 bits:
- The `bootblock.debug`, `romstage.debug` and
`verstage.debug` all have data stored at the end of the `.text`
section and code to copy the data content to the Cache-As-RAM.
- The CBFS stages included in the final image has not improperly
relocated any of the `.data` section symbol.
- Test purposes global data symbols we added in bootblock,
romstage and verstage are properly accessible at runtime
#3: for "Intel Apollolake DDR3 RVP1" board, we verified that the
generated romstage ELF includes a .data section similarly to a
regular memory enabled stage.
Change-Id: I030407fcc72776e59def476daa5b86ad0495debe
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
For x86 eXecute-In-Place (XIP) pre-memory `.data` section support, we
have to use an extra segment as the VMA/LMA of the data is different
than the VMA/LMA of the code.
To support this requirement, this patch makes cbfstool:
1. Allow the load of an ELF with an extra segment
2. Makes add-stage for XIP (cf. parse_elf_to_xip_stage()) write its
content to the output binary.
To prevent the creation of unsuitable binaries, cbfstool verifies that
the LMA addresses of the segments are consecutives.
TEST=XIP pre-memory stages with a `.data` section have the `.data`
section covered by a second segment properly included right after
the code.
Change-Id: I480b4b047546c8aa4e12dfb688e0299f80283234
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77584
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For x86 eXecute-In-Place (XIP) .data section support, cbfstool need to
to skip relocation of the .data section symbols in addition to
.car.data section symbols.
To support this requirement, this patch makes the `-S` option take a
multiple section names separated by commas.
TEST=With `-S ".car.data .data"`, XIP pre-memory stages with
a `.data` section do not have any of the `.car.data` or `.data`
section symbols relocated.
Change-Id: Icf09ee5a318e37c5da94bba6c0a0f39485963d3a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
When using Intel(R) Xeon(R) Platinum 8490H on IBM/SBP1 the platform runs
with 480 cores. With 480 cores coreboot needs at least 440KiB for ACPI
tables. Bump the config to 512 KiB to have some free space for future
changes.
Change-Id: I2c0bbc36f45aab921f3189459de4438a0cd5dd1f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
The connected panel on this mainboard gets the PWM frequency directly
from the Elkhart Lake CPU. The PWM controls the brightness of the
backlight. Therefore, it is necessary to activate the PWM passthrough
mode in the PTN3460 eDP-to-LVDS bridge (see PTN3460 Programming Guide -
5. Configuration Registers).
Link to PTN3460 Programming Guide:
https://web.archive.org/web/20230908074244/https://www.nxp.com/docs/en/application-note/AN11128.pdf
BUG=none
TEST=Boot into Linux and change the brightness of the screen
Change-Id: Ia0a329426e585b6243c8888806befbe4f6ec2998
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Yu-Ping Wu