It is a requirement for Firmware to have Firmware Interface Table (FIT),
which contains pointers to each microcode update.
The microcode update is loaded for all logical processors before reset vector.
FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are
input parameters to TempRamInit API.
If these values are 0, FSP will not attempt to update microcode.
Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place
hence skipping FSP-T loading ucode after CPU reset options.
Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and
CONFIG_CPU_MICROCODE_CBFS_LEN
Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A stripped down version (without S3) of ../agesa/family*/state_machine.c
is used to provide platform-specific hooks.
TEST=boot PC Engines apu2 with POSTCAR_STAGE patch
Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32421
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides options to override descriptor default CPU flex
ratio from coreboot code. cpu_ratio_override to provide the required CPU
ratio.
Note: Don't override the flex ratio if cpu_ratio is 0.
BUG=b:142264107
TEST=Without override flex_ratio is 0 and verified booting to
OS after overriding with flex_ratio value 5.
Change-Id: Ib01650f52f3d402f669e7e7f5b28a648b86f08ec
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When we only enable XO_SOC and mask most BBLPM requests, the BBLPM HW
arbiter will have DCXO core to enter Baseband Low-Power Mode(BBLPM).
Under BBLPM mode, inaccurate(about 1.5KHz offset) 26MHz clocks from
crystal is provided and crystal voltage will drop from 1.8V to 0.7V
or lower.
In order to ensure the stability by always outputting an accuarate
system clock when system is running. We should disable BBLPM when only
XO_SOC enabled.
BRANCH=kukui
TEST=accurate 26MHz provided and correct crystal voltage swing
Change-Id: Iea72a964507a19735cf92e3774cd8a94c06545b2
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37136
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mechanism for getting the SPIBAR is little different.
Tested on Intel Minnowboard Turbot.
Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This macro is already defined in commonlib/helpers.h
Change-Id: I1fce2936757b13807e254f4a844f583b938bf349
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Alex James <theracermaster@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
These macros are already defined in stdbool.h or commonlib/helpers.h
Change-Id: I6e474fc233d3134c89c29840471797b1e0c9e3c3
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Current code uses CPUID leaf 0x1, EBX bits 16:23 to determine number for
"core count". However, it turns out this number has little to do with
real number of cores. According to SDM vol 2A, it stays for "maximum
number of addressable IDs for logical processors in this physical
package". This does not seem to take into account fusing of giving
processor.
The new code determines 'core count' by dividing thread-level cpus by
reported logical cores. This seems to be the only way to arrive
to number of cores as it is reported in official CPU datasheet.
TEST=tested on OCP monolake
Change-Id: Id4ba9e3079f92ffe38f9104ffcfafe62582dd259
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The mrc.bin uses a lot of stack. The BSP stack size is kept
the same for both romstage bootpaths, mrc.bin and native,
in order for the CAR symbol/setups to be compatible.
Change-Id: Ic422980ca1a0549b6937e30a433ce52e0d7a595c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37185
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old logic only uses the type to identify resources, which makes a
resource in override tree overriding the first resource with the same
type (but possibly different index) in base tree, and resources with
same type (but again different index) in override tree overriding each
other.
Resources had better be identified with both their type and index.
Change-Id: I7cd88905a8d6d1c7c6c03833835df2fba83047ea
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37109
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SuperIO header needs to be included regardless of
Kconfig option, otherwise compilation fails due to
missing prototype for try_enabling_LPC47N207_uart()
if DRIVERS_UART_8250IO is not set.
Change-Id: I0eda4aee2cbb114bde33e862940a64675469693d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
SAGE brought these in outside AGESA specifications and they
had some ill semantics. They were already removed from StoneyRidge.
Change-Id: I59d0c450583b2ff58031c127aae881d1f3799338
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add Kconfig option for Jasperlake soc and make tigerlake as a base soc.
This will allow us to differentiate between soc features.
Change-Id: Id5001dc498a7d7d5c7903dc3a3762da740fc9c8e
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Now that the EC software sync in romstage ("early EC sync") patches
have landed, it's time to enable this for Hatch.
BUG=none
BRANCH=hatch
TEST=verify EC sync runs in romstage
Change-Id: Ie567ab081b95b2302b051812fbf46e183c76bab6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37025
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define the number of IOAPICs in a Kconfig to get rid of
AmdGetValue calls being not conformant to AGESA API.
Change-Id: I532597dd326093455358a23aef3b3ea0d0a14f75
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Console is not yet enabled in bootblock. This will be done in
a different CL.
Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This feature and therefore the boards using it, will be deprecated
soon.
Change-Id: I1e970dd0613702346b5764d2b56012a72ed62cde
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37155
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The romcc bootblock will be deprecated soon and most platforms use
C_ENVIRONMENT_BOOTBLOCK already. This patch drops the
CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK
where needed.
Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Some guarding is not needed because the linker drops the code,
other guarding is not needed because all platforms using the code now
have C_ENVIRONMENT_BOOTBLOCK.
Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Meep was just the first one to fail, but the others aren't any better.
Change-Id: I177c50cfe7593a5b2ad770ce1ab1191d2dff93d2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37163
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now the comment matches what is programmed into LPC_EN.
Change-Id: Ia01cf4bd068a593fc91e9ac12d0adf42d4ee937b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36995
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.
Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This fixes issue that became visible after implementing post-CAR stage on
top of `340e4b80904f lib/cbmem_top: Add a common cbmem_top implementation`.
Compilation error was:
Forbidden global variables in romstage:
ffffff00 d top.2205
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I088ac824f9b66387843ae5810fd2c75a8b16d9db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36976
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to SI team request, need to tune I2C bus 2 data
hold time more than 300ns
BUG=b:144736027
TEST=build firmware and measure I2C bus 2 data hold time
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Idc58a595c77eba8544f27682a284be6aac5dbe25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36945
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Binary strings should be joined with a binary string
* Binary files should be opened in binary mode.
* Division that wants truncation should make it explicit.
I have tested that these changes let me compile.
Change-Id: I7c41b80688a9c6bdb3c66561ff531311cc7ebb13
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37024
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even with four cloc invocations it's faster than doing the rename
dance and messes up the tree less. It also opens up using cloc's git
mode to work on a git tree instead of a checkout.
Change-Id: I3ad8fc6802ecedb332359d00b28ea61c33ed2ea0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Having the release notes mostly ready one week before the release
allows for better review.
Some statistics, the actual release date and commit ID can only be
filled in on release day, but there's a tried & true technique for
that: placeholders.
It's also a nice touch to have the release notes of a release within
its source tarballs, so push them right before creating the release
(since changes in Documentation/releases won't break coreboot in
any way).
Change-Id: Iad7ba1ba4fc841bf437f2a997428b7f636e15422
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36957
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We had two _very_ long lines containing arguments that enumerate the
paths where blobs are stored: Now there's a variable containing them.
Change-Id: I501b27158d00ba00d1c9b9e2f00a17a8b9c3f682
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36955
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
git clone allows using a local repo as reference which reduces the
required network traffic.
Change-Id: I64722cd5dbdfc0c2bcd935715cffdb99b773711c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36954
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPG 2 expects the GPG_TTY variable to be configured so
that it can properly ask for the passphrase. If it's
not already set, do so.
Change-Id: I7e145a492c9eceda40cc1a1e04452a78852042d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36953
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit f96d9051c2 (Remove MIPS Architecture) accidentally enabled
a MIPS special case to not support 64bit integers in printf for
all platforms.
This removes that MIPS-only special case entirely.
Change-Id: I5245bb32b45f9bd37bd012a7b15a64fba24a4cb7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
3b452e0 "nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak"
introduced a regression where the GAME_L decode range was not set
up, which is used by the WACOM digitizer on the Thinkpad X201T.
Change-Id: Ie569d567a65010aa5372323f8610a1b8b5d2599d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36994
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This save state is just plainly wrong in many regards and em64t100
should be used.
Checked with a model 0x17 core2 CPU.
Change-Id: I4d89691e87c91dd12b34a44b74849b18b4ac5369
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch replaces hard-coded PCI IDs with macros
from pci_ids.h and cleans up some code.
Change-Id: Ie6ea72ac49eb015ef5cbaa98ed2b3400072000b5
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36705
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Could able to build and boot ICL DE system
Change-Id: Icd71ec99f06434896c73cff5a52cd3a5ad6ce5f3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Since 'base' is a uintptr_t, it needs the PRIxPTR format specifier. This
fixes a compilation error when targeting x86_64 or using Clang 9.0.0.
Change-Id: Ib806e2b3cbb255ef208b361744ac4547b8ba262f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Use correct address for second DIMM.
Tested on Lenovo T410:
* Both DIMMs are found and are usable
Change-Id: I8bace47f04a0e185c2901695879d4d4e12d4ce6a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37105
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Patrick Georgi