Commit Graph

15170 Commits

Author SHA1 Message Date
Stefan Reinauer a4ffe8aa49 MAINTAINERS: Fix format for file entries (F:)
According to the documentation further up in the file:

F:   drivers/net/    all files in and below drivers/net
F:   drivers/net/*   all files in drivers/net, but not below
F:   */net/*         all files in "any top level directory"/net

Add trailing slashes to directory names.

Change-Id: I7bfd2eb2528a75fb6af79a990acb89f5e4251383
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12118
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-22 20:20:48 +02:00
Patrick Georgi 744729a4f0 libpayload: Add ptrdiff_t typedef
vboot2 in payloads (eg depthcharge) needs it.

Change-Id: I4e79ae29cc282c8680f21686befd35c4ff461b3a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11922
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-20 16:50:25 +02:00
Patrick Georgi 5c406459e8 Enable MULTIPLE_CBFS_INSTANCES on x86, too
It works there, we want it, disable that restriction.

Change-Id: Idc023775f0750c980c989bff10486550e4ad1374
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/12094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-20 16:39:00 +02:00
Nico Huber 0859991c4b Revert "coreboot_table: don't add CMOS checksum twice."
This reverts commit e660651824.

After some discussion on IRC we decided to revert it as libpayload can
only read the copy that was removed (and other users like nvramtool can
only read the other copy). So we need both copies at this time.

Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db
Reviewed-on: http://review.coreboot.org/11696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-20 16:35:12 +02:00
Patrick Georgi 821bcd6456 cbfstool: Fix typo in error message
Change-Id: Iaee7e2c74fe9f63d4d4878278bd445af393942f4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11920
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-19 21:09:35 +02:00
Patrick Georgi 087477fd0e vendorcode/google: Deal with MULTIPLE_CBFS_INSTANCES
We need to special-case filling out the vboot structures when
we use CBFS instead of vboot's custom indexed format, otherwise
(due to the way the CBFS header looks), it will try to write several
million entries.

Change-Id: Ie1289d4a19060bac48089ff70e5cfc04a2de373f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11914
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-19 21:09:30 +02:00
Paul Menzel d98471ccb4 Makefile.inc: Put every tool in `TOOLLIST` on separate line
This way, commit differences will be easier to read. Also sort the list
lexicographically.

Change-Id: I4ce3ac9018a3fddf5e30d7c1ac0c57090fac1d3d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12084
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-18 16:39:08 +00:00
Paul Kocialkowski 3414561f00 armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
Some registers only allow word-sized or half-word-sized operations and will
cause a data fault when accessed with byte-sized operations.
However, the compiler may or may not break such an operation into smaller
(byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
32 bit read/write and half-word-sized operations for 16 bit read/write.

This is particularly the case on the rk3288 SRAM registers, where the watchdog
tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
compiler, where a 32 bit read would be broken into byte-sized chunks, which
caused a data fault when accessing the watchdog tombstone register.

The definitions for byte-sized memory operations are also adapted to stay
consistent with the rest.

Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11698
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-17 18:10:29 +00:00
Aaron Durbin 285111f822 cbfstool: Fix removing and adding file with same name
Currently, cbfstool regressed that removing a file from CBFS the space
is marked as empty but the filename is still shown, preventing adding a
file with the same name again. [1]

```
$ echo a > a
$ echo b > b
$ ./util/cbfstool/cbfstool  test.rom create -m x86 -s 1024
Created CBFS (capacity = 920 bytes)
$ ./util/cbfstool/cbfstool test.rom add -f a -n a -t raw
$ ./util/cbfstool/cbfstool test.rom add -f b -n b -t raw
$ cp test.rom test.rom.original
$ ./util/cbfstool/cbfstool test.rom remove  -n
$ diff -up <(hexdump -C test.rom.original) <(hexdump -C test.rom)
--- /dev/fd/63  2015-08-07 08:43:42.118430961 -0500
+++ /dev/fd/62  2015-08-07 08:43:42.114430961 -0500
@@ -1,4 +1,4 @@
-00000000  4c 41 52 43 48 49 56 45  00 00 00 02 00 00 00 50  |LARCHIVE.......P|
+00000000  4c 41 52 43 48 49 56 45  00 00 00 02 ff ff ff ff  |LARCHIVE........|
 00000010  00 00 00 00 00 00 00 28  61 00 00 00 00 00 00 00  |.......(a.......|
 00000020  00 00 00 00 00 00 00 00  61 0a ff ff ff ff ff ff  |........a.......|
 00000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
$ ./util/cbfstool/cbfstool test.rom add -f c -n c -t raw

$ ./util/cbfstool/cbfstool test.rom print
test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0
alignment: 64 bytes, architecture: x86

Name                           Offset     Type         Size
c                              0x0        raw          2
b                              0x40       raw          2
(empty)                        0x80       null         792
```

So it is “deteled” as the type changed. But the name was not changed to
match the *(empty)* heuristic.

So also adapt the name when removing a file by writing a null byte to
the beginning of the name, so that the heuristic works. (Though remove
doesn't really clear contents.)

```
$ ./util/cbfstool/cbfstool test.rom remove  -n c
$ ./util/cbfstool/cbfstool test.rom print
test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0
alignment: 64 bytes, architecture: x86

Name                           Offset     Type         Size
(empty)                        0x0        null         2
b                              0x40       raw          2
(empty)                        0x80       null         792
```

[1] http://www.coreboot.org/pipermail/coreboot/2015-August/080201.html

Change-Id: I033456ab10e3e1b402ac2374f3a887cefd3e5abf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11632
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-17 06:57:50 +00:00
Paul Menzel 831bbe8446 cbfstool/cbfs_image.c: Just use one space before `=`
Change-Id: Id31c889d1e83e7ddfb0f0f98b78601f37b71cfa2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11631
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:57:42 +00:00
Maxime de Roucy 8190078ad5 coreinfo: reboot when finished
Behave as nvramcui.
Avoid a "General Protection Fault Exception" when launched by SeaBIOS on
pcengines APU1.

Change-Id: I00b1f859f76e693e8d49a38c1e02f4f49add85b7
Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com>
Reviewed-on: http://review.coreboot.org/11731
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:55:54 +00:00
Paul Menzel dc1b3c162e libpayload/Kconfig: Use official spelling for TinyCurses
TinyCursess is officially spelled in CamelCase [1].

[1] https://github.com/tommyettinger/TinyCurses

Change-Id: I7e0aa5af54140796a981c0f4c58950b25fdd67ba
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11727
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:53:52 +00:00
Paul Menzel aa98eec316 libpayload/configs: Add default configuration with TinyCurses enabled
Change-Id: Ib057e2b5f15b8d5bcdf45666f8761614317d25ee
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11726
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:53:37 +00:00
Martin Roth de9adebb10 Add junit.xml code to top Makefile.inc instead of utils
Instead of adding code to generate the junit.xml file for jenkins to
each of the util makefiles, add it once to the top level Makefile.inc.

Create a list of tools to run the test on.
Add nvramtool and inteltool to the list of utilities tested.

Note that the util builds depend on implicit rules, so MFLAGS and
MAKEFLAGS have to be cleared to get the builds to work.

Change-Id: Id7ee5ea41ce3bf4a40fb50942ae785bb838fa639
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11910
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:45:01 +00:00
Nico Huber ee09d9c658 kontron/ktqm77: Tag all four USB3 ports switchable and SS capable
With the introduction of these options in commit b26156e
(bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.)
the default regressed to disable these capabilities. Maybe other boards
regressed too. I didn't check.

Change-Id: I220896e656d00145618e61d55b74904517c7d855
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11287
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:28:30 +00:00
Martin Roth 8d226f2dbf enable lint-stable build on jenkins
This will run the lint-stable scripts on jenkins to block a commit with
obvious and known errors.

It runs in under a second on my system, so shouldn't contribute to any
real delay on jenkins.

Change-Id: I6ff3468ec29dc4ccd0c115f2c26e26b291c507df
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11892
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-17 06:16:56 +00:00
Martin Roth 606ca51530 lint: Fix shellcheck warnings, add comments
When the script was pulled out of the makefile, it was left as it was
written in the makefile to show the continuity with the original.  This
patch cleans up issues identified by shellcheck and adds comments.

Change-Id: I5e6573a4fdfbb397e15db38e2e3dfadeb3430573
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11931
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:16:49 +00:00
Martin Roth b6d739d449 lint: Add junit.xml output for jenkins
To add lint to jenkins testing, we need junit.xml output.  This adds an
optional --junit command line parameter to enable output to an xml file
in the lint directory.

Change-Id: I5588190cb050b9dbe99458cb18a71a147769f50e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11891
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:16:40 +00:00
Martin Roth e4fc407e3f lint: Move the lint script out of Makefile.inc
In preparation for adding junit xml to the lint tests, move the
script out of Makefile.inc and into its own file.

Add a copyright, usage, and error checking that was not needed
inside the Makefile.

Change-Id: I32bebc6a5f1f6fa652812c8a014d84006e2e6c8a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11890
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:16:05 +00:00
Shawn Nematbakhsh 5266fe4d97 auron: Remove duplicate pei_data assignment
Merge artifact -- don't check spd_index twice.

BUG=None
TEST=Build only
BRANCH=Auron

Original-Change-Id: I0cc372fec415646854aa931949ed0f57b473cb01
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234421
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>

(cherry picked from commit 850125141b52886c845161434a1320676e59534d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I0070e3f26ebddba716905ebb934bcec4715c4b05
Reviewed-on: http://review.coreboot.org/11912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2015-10-16 23:13:57 +00:00
Nico Huber 7b2f9f6994 intel/southbridge/bd82x6x: Add option to set SPI VSCC registers
These are needed for the hardware-sequencing function of the PCH SPI
interface. Values are specific to the flash chip used on a board.

Change-Id: Id06766b4bac2686406bc09b8afa02f311f40dee7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11798
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-10-16 22:47:22 +00:00
Tim Chen f3214d0248 auron: fix can not recognize 4G memory
Part of the following patch was lost in the merge from chromium.
This patch fixes up the spd_index for the copy from the SPD file.

In spd.c "spd_index *= SPD_LEN" will change the original spd_index
from gpio and let the following if(spd_index>3) to misjudge and
disable channel 1 incorrectly. So we calculate the index for spd file
memcpy when calling memcpy().

BUG=chrome-os-partner:32879
TEST=Can get total memory 4G on yuna 4G SKU
BRANCH=Auron

Original-Change-Id: Iebc49e20e4ca15ef6db8c4defe43cc22382a28bf
Original-Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/234420
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>

(cherry picked from commit 3b1fce58b7b4b15e947b40fd011174d4e8e294bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I03f9d63623e083c99d349d938fd802d828858f70
Reviewed-on: http://review.coreboot.org/11911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Georg Wicherski <gw@oxff.net>
Tested-by: build bot (Jenkins)
2015-10-16 22:41:17 +00:00
Timothy Pearson cbda504eec southbridge/amd/sr5650: Remove unnecessary register configuration
Do not hardcode the CPU downstream non-posted request limit; the
value of this register is CPU family specific and is set appropriately
in the corresponding CPU driver code.

Change-Id: I432b942f114243cba23c9a8d916cf6d07bc4740b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11935
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-16 21:25:28 +00:00
Timothy Pearson cfbcba5db8 arch/x86/smbios: Add Crucial DIMM manufacturer ID
Change-Id: I975142351c0c033f9dc44670dcf819d296896921
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11934
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-16 20:26:01 +00:00
Timothy Pearson ace3525e75 arch/x86/boot/smbios: Add SPD IDs for Kingston and Corsair
Change-Id: I6a32b69d3b75d7d086dc7f8ea1e195473399f406
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11933
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-16 20:25:18 +00:00
Timothy Pearson bea714088b util/cbmem: Fix failure with certain cbmem base alignments
Change-Id: Icd28af388c49ad36d7a8e414b3c82e18e1f8f523
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11932
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-16 20:23:33 +00:00
Paul Menzel 2ea25552e9 bootblock: Link timestamp.c only with EARLY_CBMEM_INIT
Commit dbeedbef (arch/x86/bootblock: Link in object files selected with
bootblock-y) breaks building of x86 boards with
`CONFIG_EARLY_CBMEM_INIT` *not* selected but CBMEM time stamp collection
enabled.

Aaron Durbin explained as below [1] and provided this patch to fix it.

> That change actually processes bootblock-objs where before it never did
> such a thing. I'm sure this isn’t the only issue lurking. bootblock on
> x86 implied romcc and thus all the bootblock-y += rules that other
> architectures use worked, but now all the implied assumptions are no
> longer true on x86.
>
> timestamp stuff on x86 !CONFIG_EARLY_CBMEM_INIT is the issue you're
> seeing. In order to compile timestamp.c for bootblock under these
> conditions will mean there needs to be some more Makefile guarding.

[1] http://review.coreboot.org/11864

Change-Id: I3441b9fcdbbc8bbe82b9f2075e60668a846ecf09
Fix-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-16 11:58:45 +00:00
Timothy Pearson 24e6d0445c cpu/amd/model_10xxx: Install AMD-provided microcode files in CBFS
Change-Id: I208b012c6b612a94b3bbc8235d5a005028be8bcc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11832
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-16 02:41:37 +00:00
Paul Menzel 6a70dbc397 cpu/x86/mtrr: Add MTRR index and total MTRRs to error message
Change-Id: I626a11c17c9d05c174c507d50684e498c8604cbc
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11905
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-15 23:31:38 +00:00
Georg Wicherski 49ee5efea7 soc/intel/broadwell: fix USBDEBUG copy-pasta
The broadwell soc code was upstreamed based off an old coreboot branch
and apparently never tested with USBDEBUG.
This changeset fixes USBDEBUG on the not yet upstreamed Auron-Paine
board, as verified with a FT232H setup. The fix is simply removing
outdated code that since branching off had been deduplicated in upstream
coreboot, anyway.

Change-Id: I53c924aa2a5357ed8313d0c9eaa2f9f9e132345e
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: http://review.coreboot.org/11874
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-15 17:48:17 +00:00
Martin Roth 615f69e53d Update 'what-jenkins-does' makefile target for junit filename
Instead of renaming the junit filename, send abuild the desired
name on the command line.

Change-Id: I779bc180343bd549908750d7128bedbab7f36266
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11879
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-15 12:21:23 +00:00
Martin Roth 21ca9beda4 abuild: add a command line parameter for junit filename
The 'what-jenkins-does' makefile target was renaming the junit filename
after abuild finished.  Instead, just add a command line parameter to
send it to a different filename.

Change-Id: I66f7d80d621573d77a5154f36f2db49d7b2e948a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-15 12:21:19 +00:00
Kyösti Mälkki cd32da425c pcengines/apu1: Fill serial number in SMBIOS
Serial number is derived from the MAC address of first NIC.

Change-Id: I91e5555b462cca87d48fb56c83aedd1eb02eba62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11901
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-10-15 12:11:05 +00:00
Kyösti Mälkki 164dbd6a5c pcengines/apu1: Fix CRCs in SPD file
Do this to wipe error message and hexdump of SPD from console log.

Change-Id: I45ffcb1c80aecf43b79d93faedcd62c8f0023cb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11900
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15 12:09:06 +00:00
Kyösti Mälkki c82ab0adf5 pcengines/apu1: Fix SPD for 4GB model
Value of tRFCmin was incorrectly using 2 Gigabit chip data.
There was no observed instability or bug reports because of this.

Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11899
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15 12:08:42 +00:00
Patrick Georgi f50603176b ec/google: Move label to BOL to satisfy lint-tests
Change-Id: I3a42ba9494b5174920e36e3110b8d62d721fe742
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11886
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15 07:36:26 +00:00
Patrick Georgi b864de5752 nvidia/tegra210: Drop FSF address
Change-Id: Ia158b4c6c12fb6e22ea7fed9035574a3abedf98c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11885
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-15 07:36:20 +00:00
Alexandru Gagniuc 86091f94b6 cpu/mtrr.h: Fix macro names for MTRR registers
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.

Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-10-15 03:52:49 +00:00
Martin Roth 58562405c8 Revert "Remove FSP Rangeley SOC and mohonpeak board support"
This chip is still being used and should not have been deleted.  It's
a current intel chip, and doesn't even require an ME binary.

This reverts commit 959478a763.

Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-14 22:49:03 +00:00
Audrey Pearson 83e4c5613e cpu/amd/microcode: Update parser to use stock microcode blobs
The existing microcode update system used custom, manually generated microcode
blob files.  This made updates very difficult.  Update parser to use stock
microcode update files as provided by AMD.

Change-Id: I772b264ad167f2a5d629dab5d64d9b0ccab3a053
Signed-off-by: Audrey Pearson <apearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11829
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-14 21:22:52 +00:00
Duncan Laurie aa1b6b06ef skylake: ACPI: Fix compiler warnings with iasl-20150717
Updating to a new IASL introduces a lot of warnings that are
not serious issues but can be fixed with some reworks.

- Method local variables that are set but never used now warn,
when needing to read back a register the ordering is now changed
to set the value in Local0 first so the compiler does not complain.
- Methods that create an object must be serialized
- A ResourceTemplate declared inside a _CRS with a named variable
does not seem to be able to compile without a warning.  To fix
this move the ResourceTemplate outside the _CRS method.
- The DPTF CPU code was still using the old legacy \_PR.CPUx
instead of the new \_PR.CPxx definitions.

BUG=chrome-os-partner:44622
BRANCH=none
TEST=build glados with iasl-20150717 and see no warnings

Original-Change-Id: I4a66c7eb6495aac4ae1aa42100c846725c1a04d2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302168
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ia3af802ca2faab4f1c59e73f2ce31a65c7e862e0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11812
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-10-14 18:33:40 +00:00
Aaron Durbin 909c512c88 fsp1_1: add verstage support
In order to support verstage the cache-as-ram split
is taken advantage of such that verstage has the
cache-as-ram setup and rosmtage has the cache-as-ram
tear down path. The verstage proper just initializes
the console and attempts to run romstage which triggers
the vboot verification of the firmware. In order to
pass the current FSP to use during romstage a global
variable in cache-as-ram is populated before returning
to the assembly code which tears down cache-as-ram.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados with verstage support as well as
     VBOOT_DYNAMIC_WORK_BUFFER with direct link in romstage.

Change-Id: I8de74a41387ac914b03c9da67fd80f8b91e9e7ca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11824
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-14 17:07:56 +00:00
Aaron Durbin 75c51d9af1 x86: add standalone verstage support
To support x86 verstage one needs a working buffer for
vboot. That buffer resides in the cache-as-ram region
which persists across verstage and romstage. The current
assumption is that verstage brings cache-as-ram up
and romstage tears cache-as-ram down. The timestamp,
cbmem console, and the vboot work buffer are persistent
through in both romstage and verstage. The vboot
work buffer as well as the cbmem console are permanently
destroyed once cache-as-ram is torn down. The timestamp
region is migrated. When verstage is enabled the assumption
is that _start is the romstage entry point. It's currently
expected that the chipset provides the entry point to
romstage when verstage is employed. Also, the car_var_*()
APIs use direct access when in verstage since its expected
verstage does not tear down cache-as-ram. Lastly, supporting
files were added to verstage-y such that an x86 verstage
will build and link.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados using separate verstage.

Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-14 17:07:52 +00:00
Aaron Durbin e3d2d6fd70 vboot: allow more flexibility when adding verstage
When a separate verstage is employed the verstage file
was just being added through the cbfs-files mechanism.
However, that doesn't allow one to specify other flags
that aren't supported that an architecture may require.
The x86 architecture is one of those entities in that
it needs its verstage to be XIP. To that end provide
a mechanism for adding verstage with options.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados using his mechansim on x86.

Change-Id: Iaba053a55a4d84d8455026e7d6fa548744edaa28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11819
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-14 17:07:31 +00:00
Kyösti Mälkki 6f499069e8 sandy/ivy: Fix PIRQs on Chromebooks
This partially reverts commit 33b535f1. After this commit, samsung/lumpy had its
internal USB EHCI controller broken, with no assigned IRQ.

PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive
for the GPIO to use. They cannot be used for PCI devices at the same time.

Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/9993
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-14 08:37:57 +00:00
Furquan Shaikh b1535e6528 t132: Add TIMESTAMP region to memlayout.ld
If timestamps need to be enabled for t132-boards, build would break
because TIMESTAMP region does not exist. With this change, t132 boards
can enable "COLLECT_TIMESTAMPS" without any build error.

Change-Id: I283a5ec49b5af95bd524f590e352367b7cbfd83d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-13 22:40:12 +00:00
Nico Huber deeec18520 gma ACPI: Do not overwrite backlight configuration
Changes to CR1 and CR2 were effectively overwriting the backlight
configuration from the devicetree with static values.

Instead read the maximum brightness value from BCLM (backlight
modulation frequency) and calculate the target level (Arg0 is the
target level as percentage).

Turned out that _BQC has to return a value from the list returned by
_BCL. So XBQC got a little heavier to search for the correct value.

Change-Id: I35419993c8250c95fc69ba4db30db9dba9e6f8ff
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11704
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-12 10:10:03 +00:00
Nico Huber d5842f5b5f gma ACPI: Consolidate non-PCH and PCH brightness levels
The two cases only differ in the register locations.

As the values in BRIG were all the same, consolidate them. They also
got normalized to percentages as the ACPI spec wants that (0x61 was 100%
before).

Change-Id: I9216a953bb89458ed102c39194ea370cbf463d5e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11703
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-12 10:09:29 +00:00
Nico Huber 62047d1e4a gma: Consolidate Intel IGD ACPI code some more
Consolidate some common (and mostly broken) code. Will try to fix things
in separate commits.

Maybe, igd.asl taken from gm45 (the non-PCH case) could also be used for
i945 and sch. But this needs further investigation.

Change-Id: Id3663bf588458e1e71920b96a3149f96947921e9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11702
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-12 10:09:00 +00:00
Aaron Durbin b66d6739c8 skylake: add support for verstage
The right files just need to be added to the verstage
build. Do that so a stand alone verstage builds and
links.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.

Change-Id: I2d0c98760494e2f4657ee35b6f155690939d2d18
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11827
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11 23:59:14 +00:00