The Shimlayer recipe requires OBJCOPY, so declare it at the top of
the Makefile so this recipe works as intended.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2e04dfe18df6252261836dcdf98f7e8de65287b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
After some measurements it turned out that Elkhart Lake uses a higher
CSR clock internally from which the MDIO clock is derived. In order to
stay compliant with the specification, the MDIO clock needs to be lower
than 2.5 MHz. Therefore, the divider needs to be 102 and not 62.
This patch changes the define to match the new divider value and uses
this new define at the appropriate place.
Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz.
Change-Id: Idf498c3547530dfa395f54488ef244e787062e34
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The highly real time driven application executed on mc_ehl1 has shown
that the L1 prefetcher on Elkhart Lake is too aggressive which in the
end leads to an increased number of cache misses. Disabling the L1
prefetcher boosts up the performance (in some cases by more than 10 %)
in this specific use case.
Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Depending on the real workload that is executed on the system the L1
prefetcher might be too aggressive and will populate the L1 cache ahead
with data that is not really needed. In the end, this will result in a
higher cache miss rate thus slowing down the real application.
This patch provides a devicetree option to disable the L1 prefetcher if
needed. This can be requested on mainboard level if needed.
Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68667
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For MT8188, the SPDX identifiers are all GPL-2.0-only OR MIT, so
replace "GPL-2.0-only" with "GPL-2.0-only OR MIT".
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5ef6c488b7ef937f6e298670ea75d306b9fe7491
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68759
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are
required.
- For audio, it requires powering on adsp_ao_pwr_con,
adsp_infra_pwr_con and audio_pwr_con.
- Add new power domain data `ext_buck_iso_bits` for buck isolation
control.
BUG=b:244208960
TEST=access display registers successfully.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The SPM register at offset 0x0 is often named as poweron_config_set in
previous MediaTek SoCs. To use common driver, we rename it from
poweron_config_en to poweron_config_set.
BUG=none
TEST=emerge-geralt coreboot.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68486
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8195 supports 2P mode and MT8188 supports 1P mode. A new struct
member `input_mode` is added to `struct mtk_dpintf` for
differentiation. We also move SoC-specific data `dpintf_data` to soc
folder.
BUG=b:244208960
TEST=emerge-cherry coreboot.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
DP drivers can be shared for both MT8195 and MT8188, so move them to
common folder.
BUG=b:244208960
TEST=emerge-cherry coreboot.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Always detecting the presence of the ELAN touchpad doesn't affect the
functionality, but allows dropping the override for all variants that
have multiple touchpad options.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id5d14eedd5d95dd0990ae56775daed9284c03717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This helps with deduplicating the identical parts of the variants'
devicetrees.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Enable SSE2 (and SSE) when compiling for x86_64. Compilers often assume
SSE2 is present and enabled when targeting x86_64.
This fixes:
- lzma decompression code is compiled with the -Ofast flag
- 'everything' when compiling with clang.
This mostly affects qemu targets, which did not have this flag selected
yet.
TESTED on qemu.
Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44869
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
For some nissa variants, there are build configurations that need to use
different blobs, but otherwise are identical. Currently, they use the
same choice of board config and configure blob paths appropriately. This
avoids duplication within the Kconfig file, but the resulting firmware
images can be difficult to distinguish, since they report the same
FRID.
Add a prompt string for MAINBOARD_PART_NUMBER so it can be overridden
and round-tripped through make oldconfig, allowing customisation of the
reported FRID and other MAINBOARD_PART_NUMBER-derived values with
minimal overhead.
BUG=b:253966060
BRANCH=None
TEST=CL:3960290 MAINBOARD_PART_NUMBER configs apply successfully
Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: I3497d7fa1c04c8fa2592025c771d9dbc65632e6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Parallel Port has LDN 1 and Serial Pot has LDN 2. Fix typo made in the
patch adding register definitions for NCT6687D Super I/O chip.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This is the enum value to initialize the Smart Trace Buffer's
Spill-to-DRAM feature. More information on how this is used is
available in the STB Linux kernel driver.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Fix "bad revision" error when we run "update_submodules" with no option.
This adds "origin/trunk" branch name for "util/goswid".
Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
We've seen failures because the binaries were not being built into the
image. In particular, the APCB is modified by the coreboot build
process, so if the APCB isn't built correctly to support the correct
number of SPDs, the build can fail.
The mendocino FSP binaries are not yet pushed, so the build is currently
pointing at the cezanne binaries. The mendocino FSP will be pushed when
the mendocino chips are released for sale.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I31d11c5327416f4339930373c447531ae9f79d28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Update the MCA bank names for morgana per PPR #57396, rev 1.52
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If0082bd5362bdead3f9dc693d1e338e8cda224f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Pentium CPU will use 150W adaptor, this change revises PsysPL2 to 150W
based on fw_config.
BUG=b:253542746
TEST=Check CPU PsysPL2=150W in AP log with Pentium CPU.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
SaGv is enabled for all brya variants, so it should be harmless
to enable it for brask variants to save some power.
BUG=254374912
TEST=Build and boot to Chrome OS
Signed-off-by: Derek Huang <derekhuang@google.com>
Change-Id: Ib5d1e39b3f901606e2f1449e4ed40d53696562ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The touchscreen IRQ has been configured as LEVEL_LOW in skyrim projects.
Therefore, update the gpio.c to be consistent with the configuration.
BUG=b:253506651, b:251367588
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp
Counter Frequence. For CPUs that do not support this instruction, EDK2
must include a different library which is the reason why this must be
configured at build time.
If this is enabled, and the CPU doesn't support 0x15, it will fail to
boot. If is not enabled, and the CPU does support 0x15, it will still
boot but without support for the leaf. Consequently, disabled it by
default.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Working with resources in KB is tedious and the base_k / size_k variable
naming was simply wrong in one case.
Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
TOLUD stands for top of lower usable dram. Memory between cbmem_top and
TOLUD, even if stolen for another device/purpose can still be marked WB
cacheable. This will result in a cleaner MTRR setup.
Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68405
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2
variants in order to provide the real delay value for the VCC supply
rail. This delay is needed to enable proper switching between different
VCC levels based on current system state.
Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
the "x86 PIC code ebx" workaround done previously
by commit 689e31d18b ("Make cpuid functions usable
when compiled with PIC") does not work for x86_64
(the upper dword of rbx is set to 0)
the GCC bug that needed the workaround was fixed
in version 5 (see GCC bug 54232)
Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95
Signed-off-by: Matei Dibu <matdibu@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66345
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Apollo Lake seems to start with PCIe root ports unusable/uninitialized
before FspMemoryInit() is called and FSP-M properly initializes these
root ports.
However, we need the root ports accessible before FspMemoryInit() in
certain cases, such as emitting POST codes through a PCIe device.
For the initialization to happen properly, certain register writes
specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter
3.3.1 have to be done.
BUG=none
TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check
that the POST codes are emitted before FspMemoryInit().
Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the VCCST ICCMax Control for the ADL-N display flicker issue.
Please refer the Doc with ID 742988 for more details.
BUG=b:248249033
TEST=Verified that the display flicker issue is fixed.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68252
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
We still had a lingering reference to the old sabrina codename in the
vendorcode directory. Searching through the code now, the only places
the sabrina codename is seen is in the release notes, as is proper.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Make GPIO_I2C_MASK macro more accurate by using the GPIO_I2Cx_SCL
definitions instead of BIT(x).
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On nissa, the pre-x86 time is not part of the 1s firmware boot time
target. Including the pre-x86 timestamps causes confusion since the boot
time appears to be greater than 1s, so disable the Kconfig on nissa.
We're not doing any analysis or optimisation of the pre-x86 time on
nissa anyway, this work will start from MTL onwards. Also, the Kconfig
is already disabled on the brya firmware branch, so this will result in
the same behaviour as brya.
Before:
Total Time: 1,205,840
After:
Total Time: 995,300
BUG=b:239769532
TEST=Boot nivviks, check "1st timestamp" is the first timestamp.
Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all kahlee variants use the RT5682 audio codec, so split the
baseboard audio ACPI into two parts and only include the asl for
the codec(s) actually needed for a given variant.
TEST=build/boot aleena, liara variants and verify no ACPI present
for RT5682 codec (which is not present on the boards).
Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update generated FSP headers for Alder Lake N from v3301.00 to v3343.04.
Changes include:
- FspsUpd.h: 1. Add PchFivrVccstIccMaxControl UPD
BUG=b:254374913
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa.
Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68424
Reviewed-by: Reka Norman <rekanorman@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Built from a mixture of autoport output, other variants, schematics and
expert guesswork. I don't have this board, but the code has been tested
by someone else and boots successfully (first try) with TianoCore. It's
reasonable to assume most things work, as this board is very similar to
the already-supported variants.
Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61541
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sean Rhodes