Commit Graph

43374 Commits

Author SHA1 Message Date
Matthew Blecker a5714574fd mb/google/poppy/variants/atlas: stop setting touchscreen probed=1
All Atlas devices have the touchscreen controller, so probing for its
presence is unnecessary.  Removing the probe requirement allows the
touchscreen ACPI device in Linux to re-enumerate when rebinding its
I2C adapter device.

Without this change, after rebinding the touchscreen's I2C adapter
device using sysfs the touchscreen ACPI and HID devices are absent, and
the touchscreen is unresponsive.

With this change, the touchscreen ACPI and HID devices are re-created
after rebinding its I2C adapter device, and the touchscreen becomes
responsive again.

BUG=b:177350937
TEST=Tested on 2 Atlas DUTs running Chrome OS R94 top-of-tree builds
with Linux 4.4 and 5.4.

Built new AP FW from Atlas Chrome OS firmware branch with this change
applied.  Tested shipping RO + new RW, and new RO + new RW.

Test sequence:

1) Boot DUT, verify basic touchscreen functionality.

2) $ cd /sys/bus/platform/drivers/i2c_designware

3) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}}
lrwxrwxrwx. 1 root root 0 Aug 12 01:07 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6
drwxr-xr-x. 4 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00
drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002
drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw
drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw/hidraw1

4) $ echo i2c_designware.0 > unbind

5) Verify touchscreen is unresponsive (as expected after unbind).

6) $ ls -ld i2c_designware.0
ls: cannot access 'i2c_designware.0': No such file or directory

7) $ echo i2c_designware.0 > bind

*** Without this change: ***

8) Touchscreen remains unresponsive.

9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00}}
ls: cannot access 'i2c_designware.0/i2c-6/i2c-ACPI0C50:00': No such file or directory
lrwxrwxrwx. 1 root root 0 Aug 12 01:18 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 4 root root 0 Aug 12 01:18 i2c_designware.0/i2c-6

*** With this change: ***

8) Touchscreen is functional again.

9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}}
lrwxrwxrwx. 1 root root 0 Aug 12 01:09 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0
drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6
drwxr-xr-x. 4 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00
drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003
drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw
drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw/hidraw1

Signed-off-by: Matthew Blecker <matthewb@chromium.org>
Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56928
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16 14:55:12 +00:00
Wisley Chen 441bc06905 mb/google/brya/var/redrix: Generate SPD ID for supported parts
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.

MT53E512M32D1NP-046 WT:B
MT53E1G32D2NP-046 WT:B

BUG=b:192052098
TEST=FW_NAME=redrix emerge-brya coreboot

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I61377e6cdd3af9d6d80b9e1e68191b39f43358ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16 14:54:44 +00:00
Eric Lai 637470c438 mb/google/brya: Add I2C parameter
Add I2C parameters to make sure each bus speed is around 390kHz.

BUG=b:188793264
TEST=Measure by scope.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib47228b8684c44f6acfec9e9e4b6e7b18ba6f6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16 14:54:18 +00:00
David Wu 93a6c39b86 mb/google/brya/variants/kano: Configure GPIOs according to schematics
Update initial gpio configuration for kano

BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4d6099fa8d17bebf798ddf236a68886087e2a95e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16 14:54:01 +00:00
Varshit B Pandya df368d5dfe mb/google/brya: Configure EN_FCAM_PWR to high
Recent change "7a8c68a: mb/google/brya: Configure H21 as GPO and A17
as low" turned EN_FCAM_PWR low since EN_FCAM_PWR is turned ON and
OFF by IPU driver while MIPI UFC probing. However USB UFC also
requires 3.3V which is enabled by A17. This caused USB UFC
enumeration to fail

BUG=b:196014678

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I88c204ec07b1f7511f0d88074e336cfc9116a7d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56882
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16 14:53:49 +00:00
Yu-Ping Wu d019bfc2d1 Documentation/util/kconfig: Remove silentoldconfig
The "silentoldconfig" target has been removed in Linux 5.13's kconfig
(CB:37152). As explained by Michal Marek at
https://lkml.org/lkml/2011/8/31/189, the "silentoldconfig" target has
become an internal interface and "oldconfig" is just as silent now.
Therefore, correct the target for syntax checking.

Change-Id: I8416bd4a96d15415f46c591ceb26ebb29aef1ab0
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-08-16 14:53:01 +00:00
Casper Chang 8d7d3e5f0f mb/google/brya/primus: Fix G2 touchscreen reset GPIO polarity
modify reset_gpio as active low to meet touchscreen spec

BUG=b:195490284
BRANCH=none
TEST=build coreboot and touchscreen works

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I7ce1b3025db8abebf5693b34da846a7e969246fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16 14:51:27 +00:00
Boris Mittelberg cd1f8c5c5b mb/google/brya: allow MKBP devices and disable TBMC device
Enable MKBP (Matrix Keyboard Protocol) interface for all Brya family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.

BUG=b:170966461
TEST=manual test on Brya P1: Volume Up/Down buttons

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: Ic9c707f57871f388c363e01c9ab78a3b358ce728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16 14:51:07 +00:00
Martin Roth 266dfc95c4 mb/google/guybrush: Update GPIOs for fingerprint MCU
Add mainboard finalize and shutdown call to match zork.
Deassert EN_PWR_FP in bootblock, power up correctly in finalize.

| Phase     | SOC_FP_RST_L | EN_PWR_FP | S3 resume            |
|-----------|--------------|-----------|----------------------|
| Bootblock | **Low**      | **Low**   | Maintain High / High |
| Romstage  | Low          | Low       | Maintain High / High |
| Ramstage  | Low          | **High**  | Maintain High / High |
| Finalize  | **High**     | High      |                      |
| Shutdown  | **Low**      | **Low**   |                      |

BUG=b:191694480
TEST=Build, verify GPIO configuration.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-16 14:47:03 +00:00
Patrick Rudolph ad82106eb9 Documentation: Mark ECC as working on Sandy Bridge
Change-Id: I9f9aa5bf6ed4e1430e7067bfe5d3ce8e59e85812
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-16 14:46:13 +00:00
Mackenzie May 9bd9362ae6 crossgcc: upgrade Expat from 2.2.9 to 2.4.1
Versions of expat before 2.4.0 have been renamed to prevent their
use, due to some kind of vulnerability. without updating this
dependency it is currently not possible to build crossgcc with GDB.

Change-Id: Iec2cf560902dc556a41206d7dcd65c22cf3e1215
Signed-off-by: Mackenzie May <ky0ko@disroot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56868
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16 10:00:42 +00:00
Subrata Banik 095e2a7835 soc/intel/alderlake: Create eNEM Kconfig for Alder Lake
Alder Lake SoC specific Kconfig that internally selects all eNEM
related Kconfig. CONFIG_ALDERLAKE_CAR_ENHANCED_NEM will get
autoselected if platform doesn't have INTEL_CAR_NEM Kconfig selected
explicitly.

BUG=b:168820083
TEST=Verified CONFIG_INTEL_CAR_NEM is still enable.

Change-Id: Ife1c7d2036cece4598275dfc26ed138fb46bd881
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56090
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16 05:07:45 +00:00
Subrata Banik 0e2510f616 soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC
Kconfig and here is modified flow as below:
Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS
Update eNEM init flow:
  - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1
Update eNEM teardown flow:
  - Set MSR 0xC85 L3_Protected_ways = 0x00000

BUG=b:168820083
TEST=Verified filling up the entire cache with memcpy at the beginning
itself and then running the entire bootblock, verstage, debug FSP-M
without running into any issue. This proves that code caching and
eviction is working as expected in eNEM mode.

Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16 05:07:12 +00:00
Subrata Banik ad08265740 soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enable
As per TGL EDS doc:575681, two ways will be controlled with one bit
of SF QoS register(SF Mask#1/#2) hence, selects SF_MASK_2WAYS_PER_BIT
for TGL SoC.

Change-Id: Ibeef653e0c510b62880b10b3f9767664d89c9623
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15 07:12:41 +00:00
Subrata Banik baf922c798 soc/intel/common: Calculate and configure SF Mask 1
MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL and is used
to find out the NUM_SNOOP_FILTER_WAYS. Bit[5:0] of MSR 0xc87 indicates
the maximum number of bits that may be set in any of the SF MASK
register. Hence, this patch calculates SF way count using below logic:

Calculate SF masks 1:

1. Calculate SFWayCnt = (MSR 0xC87) & 0x3f

2. if CONFIG_SF_MASK_2WAYS_PER_BIT:
	a. SFWayCnt = SFWayCnt / 2

3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - SF_MASK_2

Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15 06:58:36 +00:00
Subrata Banik 16ab9bdcd5 soc/intel/common: Calculate and configure SF Mask 2
As per TGL EDS, two ways will be controlled with one bit of SF QoS
register hence, this patch introduces SF_MASK_2WAYS_PER_BIT Kconfig to
allow SoC users to select SF_MASK_2WAYS_PER_BIT to follow the EDS
recommendation.

Calculate SF masks 2:
1. if CONFIG_SF_MASK_2WAYS_PER_BIT:
        a. data_ways = data_ways / 2

Also, program SF Mask#2 using below logic:
2. Set SF_MASK_2 = (1 << data_ways) - 1

Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15 06:58:09 +00:00
Sumeet Pawnikar 83c9b3a599 mb/google/brya: set PL4 value dynamically for thermal
Set PL4 value dynamically for brya board based on CPU SKUs
which is detectable at runtime.

BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 with below messages,
 On brya (282):
  Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000)
 On brya (482):
  Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000)

Change-Id: I20b98ccd8493ed238de647cda8ceb25f62029133
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15 02:07:35 +00:00
Felix Singer c18ee230dd mb/google/brya/{redrix,taeko}: Deduplicate lockdown config
Lockdown configuration is done in their baseboards. Thus, remove the
setting from the variants overridetree.

Change-Id: Iadb1201718466503987e4f6bd72bf711a2d3128e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-15 02:02:35 +00:00
Karthikeyan Ramasubramanian 54be00a072 mb/google/guybrush: Create nipperkin variant
Create the nipperkin variant of the guybrush reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=None
BRANCH=None
TEST=util/abuild/abuild -p none -t google/guybrush -x -a
make sure the build includes GOOGLE_NIPPERKIN

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ie525ea501e6c3d5d94e67c1db1d4e307fb7ccba7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56921
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13 22:10:01 +00:00
Tim Crawford ebf8a41b05 soc/intel/tgl: Hook up ucode for TGL-U and TGL-R
Hook up microcode from 3rdparty repo for:

- TGL-U: 06-8c-01 (CPUID signature: 0x806c1)
- TGL-R: 06-8c-02 (CPUID signature: 0x806c2)

Verified microcode blob was found in CBFS on system76/darp7 (TGL-U).

    CBFS: Found 'cpu_microcode_blob.bin' @0x103c0 size 0x31c00 in mcache @0x76c2d0ac
    microcode: sig=0x806c1 pf=0x80 revision=0x88

coreboot reports the correct revision for the microcode.

Change-Id: I210c0133dad7ade63b9f7177aaa9a69b019469af
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56862
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13 18:07:22 +00:00
Tim Crawford 8de2d591e2 3rdparty/intel-microcode: Update submodule to 20210608 release
Update submodule pointer to include microcode for TGL and others.

Tested the following still boot:

- galp3-c (WHL-U): sig=0x806eb pf=0x80 revision=0xe9
- oryp5 (CFL-H): sig=0x906ea pf=0x20 revision=0xe9
- gaze15 (CML-H): sig=0xa0652 pf=0x20 revision=0xe9

coreboot reports the revision as -1 from what it actually is. i.e.,
these should report revision=0xea (and that is what Linux reports).
However, this behavior is not new.

Change-Id: I084ba67e8eaf7383f1c05fa5589b63c92ff900b1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56861
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13 18:06:50 +00:00
Jakub Czapiga d0bd012b5e tests/Makefile.inc: Add missing include paths to TEST_CFLAGS
Add missing paths to common tests cflags and remove these paths from
individual tests configuration.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I13cb336195bfb06b861d7f403822f06bec8a40aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-13 18:05:55 +00:00
Jakub Czapiga 9bf716ede0 tests/Makefile.inc: Add copy-test macro
copy-test macro copies attributes from one test to another. It can be
used to create multiple tests with the same subset of attributes values.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I9c9b6b12830c7060ffe5dcf35c9486655cbd08e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-13 18:05:41 +00:00
Jakub Czapiga eaf5ff3607 tests/Makefile.inc: Change assignments to immediate and fix style
Change assignments to be immediate instead of lazy. Add spaces between
variable name and assignment operators to increase readability.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Idf07b5a836b33cd80c3533e582e2a1916a7bd45d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-13 18:05:21 +00:00
Sumeet Pawnikar e7f3e6a055 mb/google/brya/variants/brya0: add PL4 values for different SKUs
Add PL4 values for brya0 board for different CPU SKUs.

BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 with below messages,
 On brya (282):
  Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000)
 On brya (482):
  Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000)

Change-Id: I095e9eda6665fd1927f35ee57d52922eddd8227a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-13 18:04:55 +00:00
Ivy Jian 13bf4dde29 mb/google/guybrush: update USB 2.0 Lane Parameter settings for USB port5
Tune the USB phy settings to update TXVREFTUNE0/COMPDISTUNE0 to
higher value for USB port 5 (Type-A).

BUG=b:194053549
TEST= Pass USB 2.0 SI Eye diagram measurement.

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Id1ede34bdbee0c1f9f7d10fc7ffbc9648af31e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56925
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13 18:04:26 +00:00
Meera Ravindranath bcc74afa73 mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU
DDR5 Maple Ridge SKU (Board ID 0x16) uses a Memory down DIMM
configuration.

TEST=Boot DDR5 MR SKU to OS.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56881
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13 18:04:02 +00:00
Bhanu Prakash Maiya adc9e63c59 util/mb/google: add template files for guybrush
Create template for guyrbsuh variant creation.

BRANCH=none
BUG=b:194031783
TEST=n/a

Change-Id: If62c1a63d0890539d4b43f840f75ee9d7ceab4f8
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-13 18:03:40 +00:00
Meera Ravindranath eb32a85ade mb/intel/adlrvp: Rename spd_info struct based on memory topology
Naming spd_info struct based on memory topology helps in reuse of
code.
lp4_lp5_spd_info  -> memory_down_spd_info
ddr4_ddr5_spd_info -> dimm_module_spd_info

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7a66b5524d8b80776ab7578ce7b13181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-08-13 18:03:15 +00:00
Nico Huber 5142ab4193 mb/{kontron/bsl6,siemens/chili}: Add `inhibit_flashlock` nvram option
Change-Id: I8c5d6686bf7c694f9d594e3801c79cfd7fb3da80
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56342
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13 18:02:48 +00:00
Boris Mittelberg 71a0bb57d7 mb/google/dedede: allow MKBP devices and disable TBMC device
Enable MKBP (Matrix Keyboard Protocol) interface for all dedede family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.

BUG=b:170966461
TEST=manual test on Madoo:
Volume Up/Down and Power buttons, Tablet Mode switch

Cq-Depend: chromium:3069163
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I9d1f43e4dd56318af4c1d5f5c1c3a2c237a05c5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56840
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13 17:14:59 +00:00
Sathya Prakash M R 1f19ef54e4 mb/intel/adlrvp: Use HDA TMODE 8T to match spec for ADL P RVP
With current setting Display audio codec probe fails.
Hence HDMI/DP audio fails.

Earlier, with FSP 2037 was used the mode was incorrectly programmed to 4T

This setting was carried ahead with below change:
Commit : 50f8b4ebdd

The issue was fixed in later FSPs and with current
FSP v2237, we need to set the TMODE to 8T as per spec.

TEST=Verify HDMI/DP Playback on ADL P RVP

Fixes: 50f8b4ebdd
       (soc/intel/alderlake: Add enum for HDA audio configuration)

Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Change-Id: Ia39a33f5da2fea0dc2eaf4eae45999a711c61c33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56208
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13 04:15:32 +00:00
Felix Singer f9d7dc7ed3 soc/intel/alderlake: Clean up FSP chipset lockdown configuration
Use a variable to store if the FSP should be responsible for the chipset
lockdown and use it for setting related configuration options. Thus, get
rid of that if-else-clause.

Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12 21:42:36 +00:00
Felix Singer c8fc542e1b soc/intel/jasperlake: Clean up FSP chipset lockdown configuration
Use a variable to store if the FSP should be responsible for the chipset
lockdown and use it for setting related configuration options. Thus, get
rid of that if-else-clause.

Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12 21:42:16 +00:00
Felix Singer 673e6d1c67 soc/intel/tigerlake: Clean up FSP chipset lockdown configuration
Use a variable to store if the FSP should be responsible for the chipset
lockdown and use it for setting related configuration options. Thus, get
rid of that if-else-clause.

Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12 21:42:01 +00:00
Felix Singer 5385b4daa8 soc/intel/skylake: Clean up FSP chipset lockdown configuration
Use a variable to store if the FSP should be responsible for the chipset
lockdown and use it for setting related configuration options. Thus, get
rid of that if-clause and adjust comments.

This changes behavior since now related options are always set,
depending on if coreboot or the FSP should be responsible for the
chipset lockdown. This ensures a defined state independent from the
default configuration of the FSP.

Change-Id: I0c43a11a40a474de4af22aa5506b1d387809bda2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12 21:41:46 +00:00
Felix Singer 85ebab8541 soc/intel/cannonlake: Clean up FSP chipset lockdown configuration
Use a variable to store if the FSP should be responsible for the chipset
lockdown and use it for setting related configuration options. Thus, get
rid of that if-else-clause and adjust comments.

Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12 21:41:31 +00:00
V Sowmya c6d7166942 soc/intel/alderlake: Configure the SKU specific parameters for VR domains
This patch configures the SKU specific power delivery parameters for the
VR domains.
+--------------+-------+-------+-------+-------+-----------+--------+
|      SKU     |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time|
|              |       |(mOhms)|(mOhms)|  (A)  |     (A)   |  (msec)|
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 682(45W)|   IA  |  2.3  |  2.3  |  160  |     57    | 28000  |
+              +-------+-------+-------+-------+-----------+--------+
|              |   GT  |  3.2  |  3.2  |   50  |     57    | 28000  |
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 482(28W)|   IA  |  2.3  |  2.3  |  109  |     40    | 28000  |
+              +-------+-------+-------+-------+-----------+--------+
|              |   GT  |  3.2  |  3.2  |   50  |     40    | 28000  |
+--------------+-------+-------+-------+-------+-----------+--------+
|ADL-P 282(15W)|   IA  |  2.8  |  2.8  |   80  |     20    | 28000  |
+              +-------+-------+-------+-------+-----------+--------+
|              |   GT  |  3.2  |  3.2  |   40  |     20    | 28000  |
+--------------+-------+-------+-------+-------+-----------+--------+

These config values are generated iPDG application with ADL-P platform
package tool and supports 15W/28W/45W SKU's.
RDC Kit ID for the iPDG tools,
* Intel(R) Platform Design Studio Installer: 610905.
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345.
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261.

BUG=b:195033556

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56325
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12 19:32:34 +00:00
V Sowmya 458708fc30 soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL
This patch updates the VccIn Aux Imon IccMax for ADL-P to SOC SKU
specific values from the FSP default value 160.
* ADL-P 682(45W) = 137.
* ADL-P 482(28W) = 128.
* ADL-P 282(15W) = 128.

These config values are generated iPDG application with ADL-P platform
package tool and supports 15W/28W/45W SKU's.
RDC Kit ID for the iPDG tools,
* Intel(R) Platform Design Studio Installer: 610905.
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345.
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261.

BUG=b:195033556

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56176
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12 19:31:35 +00:00
Jamie Chen d5d25558bc soc/intel/apollolake: add 4Gb and 6Gb dram density
This patch adds 4gb and 6gb dram density support to APL and GLK.

BUG=b:178665760
BRANCH=NONE
TEST=build fw and flash to the dut, the dut can boot up successfully.

Change-Id: Ic0d5d14f26a30da7a9caf4ef43d7fac88a4d2bf1
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55153
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12 18:01:42 +00:00
Jamie Chen adda399234 soc/intel/apollolake: change LPDDR4 density enum definition
Originally we use rank_density=0 to mean disable the channel, but actually
rank_density=0 means 4Gb density in the FSP.
This patch changes the LPDDR4 enum values to the real density number and
adds a switch statement to mapping the density define in the FSP.

BUG=b:178665760
BRANCH=NONE
TEST=build fw and flash to the dut, the dut can boot up successfully.

Change-Id: I36dba2cef130211e7aea9e2a4f82c5db78f82a83
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56805
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12 18:00:54 +00:00
Tim Crawford 9f7e9cbc26 mb/system76/*: Add CMOS option table
System76 uses several custom CMOS values downstream. Reduce our diff by
providing a generic layout with the defaults:

    boot_option=Fallback
    debug_level=Debug
    power_on_after_fail=Enable

Tested on galp3-c, gaze15, oryp5, oryp6. All boards boot multiple times
with USE_OPTION_TABLE selected.

Change-Id: Ie57b0e5713bba8ad46e1a4123a3ddd43e0eea964
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-08-12 17:59:21 +00:00
Rex-BC Chen 716320b726 soc/mediatek/mt8192: move DFD driver to common folder
Move DFD driver to common folder so MT8195 can also use it.

BUG=b:192429713
TEST=emerge-asurada coreboot

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7937cddf5f3a66f9269a94301d3134e6f4f9f22e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-12 17:59:00 +00:00
Ryan Chuang 4572727547 vc/mediatek/mt8195: Optimize DRAM init time by disabling Vcore setting
Remove the unnecessary Vcore setting for the DVFS feature.

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: If3c28e57a559a7ec04319c1a489138817e44ec4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-12 17:58:45 +00:00
Rex-BC Chen 909f2d04a0 soc/mediatek: revise the dependency of DVFS config options
The MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT only makes sense if DVFS
is enabled (e.g., MEDIATEK_DRAM_DVFS) so we should change it to
depend on that instead of selecting DVFS.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib81e4e48e863616ed1e36cd5c0000f4e2cfb5456
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-08-12 17:58:21 +00:00
Eric Lai b6f6e01bcb drivers/generic/alc1015: Add HID to support alc1019
ALC1019 will use the ACPI compatible and share the same driver with
ALC1015. Add HID to support more compatible ICs.

BUG=b:195891240
TEST=ALC1019P driver can probe properly.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3e98297f3a39048b24d61e61ca95c60cd2037eb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-12 17:57:55 +00:00
Nico Huber 6cf47f524a libpayload: Mark Intel 300 series AHCI as tested
Tested with filo on roda/rw14.

Change-Id: Ia5f868d3a9cead0a872e6d3e9fdacd6eeb7f158b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56666
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12 17:57:35 +00:00
Maxim Polyakov 8f6c896167 MAINTAINERS: Add Maxim Polyakov as intelp2m maintainer
Change-Id: I85835712926ca456b108b1d80e6a55f75e604591
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-12 17:57:17 +00:00
FrankChu 627bc558ec mb/google/dedede/var/galtic: Add charger throttling function
Add charger current throttling support for galtic
  control charger index * 64 = Value mA
    32*64=2048
    28*64=1792
    24*64=1536
    20*64=1280

BUG=b:187231627
TEST=Built and tested on boten system

Cq-Depend: chrome-internal:3846209
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I5e1849551ff051bca591f19f9e40da4c89ab74e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-08-12 17:54:55 +00:00
Wisley Chen eb07e4c957 mb/google/dedede/variants/haboki: add discrete TPM in overridetree
Haboki is project which use discrete TPM, so add discrete TPM and
disable cr50 in overrideree.

BUG=b:187094464
TEST=FW_NAME=haboki emerge-keeby coreboot chromeos-bootimage

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I08f2a562c3f62c60402350151ea260b70890a744
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-12 17:54:32 +00:00