Commit Graph

36933 Commits

Author SHA1 Message Date
Rob Barnes 875d0c22b8 mb/google/zork: Add woomax memory ID 0
Woomax needs memory ID 0 to map to MT40A512M16TB-062E:J.

BUG=b:165611555
TEST=None

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ibbcef6be382bd6649c93cfe92427f124dd137112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45264
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 15:41:21 +00:00
Nikolai Vyssotski 1e633e88dd soc/amd/picasso: Fix TSC frequency calculation
Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.

BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork

Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11 15:32:14 +00:00
Felix Held 1fa45b1460 vc/amd/fsp/picasso: Fix FSP-S UPD header file formatting
Use one tab instead of 8 spaces at the beginning of the lines added in
commit 39a8040ddc.

Change-Id: I8d7553e1b41dbbbdabd7392028a51e3a0f79c97a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-11 14:28:38 +00:00
Felix Held b026c7c65a soc/amd/common/espi_util: clarify espi_open_io_window
Calling espi_open_generic_io_window in espi_open_io_window depends on
the condition in the preceding if statement, so move the command into an
else block to make it more obvious that this is the case.

TEST=Timeless build results in identical image.

Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11 14:27:57 +00:00
Subrata Banik 3999aa6cdb soc/intel/tigerlake: Clean up systemagent.h
List of changes:
1. Convert inconsistent white space into tab.
2. Group together all MCHBAR offset macros.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I82fc362589389081b1b1856524a972b780af9a13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45256
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 03:14:05 +00:00
Subrata Banik 86e53267c4 device: Fix incompatible-pointer-types build error
The build error `incompatible-pointer-types` occurs while using
`pci_dev_request_bus_master` as part of device ops

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3b1ce85b8db1ddf9ac860415edbe64694b91b3d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45122
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 03:13:17 +00:00
Alex Levin a903ea8d62 mb/google/volteer/variants/volteer2: route GPP_F14 via APIC
GPP_F14 should be configured to be routed via APIC and not SCI.

BUG=b:162528549
TEST=verified on a volteer2

Signed-off-by: Alex Levin <levinale@google.com>
Change-Id: I7f2c7af230dd75b3cb3806e2b186725d49da9e68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 01:04:36 +00:00
Julius Werner 8678d47deb trogdor: Strappings_update_final3.1_second_thisistherealone.patch
Apparently what I thought was lazor-rev2 is actually lazor-rev3 and
nobody is really sure what lazor-rev4 is going to be at this point or
how we proceed from there. What seems to be somewhat agreed upon is that
for now all Lazor revisions use the "old" GPIO mapping and it's not very
clear if that's ever going to change for Lazor, so let's take the
revision restriction out from Lazor for now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4939ccfd8464da6e72b5e01a58489b8c80f5b4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-10 21:40:07 +00:00
Rob Barnes b2545cc3c6 soc/amd/picasso: Move APCB generation out of picasso
Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.

BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
     Build and boot ezkinil

Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 20:26:03 +00:00
Michael Niewöhner 3992da034f lib/Makefile.inc: fix hex-to-bin conversion of SPD files
This fixes the hex-to-bin conversion command, used to generated binary
SPD files from hexdumps.

An issue that only appeared on one of my systems, where conversion of
'01 02 03' to binary resulted in \x01\x32\x03 instead of \x01\x02\x03:

for c in 01 02 03; do printf $(printf '\%o' 0x$c); done | xxd -g 1
00000000: 01 32 03                                         .2.

The reason for this was that the syntax in lib/Makefile.inc is wrong,
because the backslash must be escaped due to chaining two printf
commands.

Change-Id: I36b0efac81977e95d3cc4f189c3ae418379fe315
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 17:30:00 +00:00
Patrick Georgi 28276fc834 util/abuild: Remove symbols that don't exist anymore in Kconfig
Bayou and OpenBIOS aren't supported by the coreboot build system
anymore, so remove these mentions.

Change-Id: Ibdf6fdc776068041cb468fdbf5b56b06f85c2d4b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-10 15:50:27 +00:00
Jason Glenesk f459a4084e soc/amd/picasso: Add MADT entry for GNB IOAPIC
Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot
will always enable the GNB IOAPIC.

Cq-Depend: chrome-internal:3247431, chrome-internal:3253044
BUG=b:167421913, b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
     parameter. Dump MADT and IVRS tables. Cross check ioapic entries
     in MADT against IVRS.
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 12:38:19 +00:00
Marshall Dawson 39c64b0bdd soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSP
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot.  Do the same
for the northbridge's IOAPIC base address.

Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.

BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 12:37:45 +00:00
Marshall Dawson 39a8040ddc vc/amd/fsp/picasso: Sync FSP-S UPD header file
Sync the UPD definitions with the latest auto-generated files.
Definitions and usage will be updated in a subsequent FSP
Integration Guide.

Cq-Depend: chrome-internal:3247431
BUG=b:167421913, b:166519072, b:159664044
TEST=Boot morphius
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ic85e1f457c8932d933d8645738de68319dbf375a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-10 12:37:29 +00:00
Yu-Ping Wu aa78c9ea4a mb/google/asurada: Add config for hayato
BUG=b:163789704
TEST=emerge-asurada coreboot
BRANCH=none

Change-Id: I1a5928fb81356aaf040534e1675933a504aa9f95
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45163
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 06:39:45 +00:00
Elyes HAOUAS 1a8b50089d soc/mediatek: Drop unneeded empty lines
Change-Id: Ia419de14614a7a1b583e0870e9ca2fcdc8cf815a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-09-10 06:37:52 +00:00
Maxim Polyakov f8f8615eef mb/siemens/mc_apl2/gpio: Fix code style
Use the 96 character limit for pad macros.

Change-Id: I03fd2f9309c04628c46e3473bed280edc57e215c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2020-09-10 05:35:11 +00:00
Maxim Polyakov e05aafbc67 mb/siemens/mc_apl2/gpio: Undo set DRIVER for GPO
GPIO Driver mode is used for configuration interrupt routing for
external devices through GPI. But there is no point in configuring
this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro
with others that do not set the corresponding bit in the Host Software
Pad Ownership register.

Change-Id: I406a08e526a6c655f38e4c0a355957c98e93881c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2020-09-10 05:34:49 +00:00
Subrata Banik 2ee4c0d7f4 vendorcode/intel/fsp/alderlake: Fix FSPS_ARCH_UPD redefinition issue
FSPS_ARCH_UPD struct is part of edk2-stable202005 branch (FspApi.h)
hence local definition of FSPS_ARCH_UPD inside FspsUpd.h is causing
compilation issue.

Change-Id: Id5b3637d9ab6d87aab6da810f9c83d3258900a29
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-10 05:27:03 +00:00
Subrata Banik fed1a1a8b0 soc/intel/alderlake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init to
maintain the parity with previous generation SoC code block.

Refer to commit 1201696.

Change-Id: Id2a89b2f64b58079062d79e07efbdcfad7ed3d2d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45189
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 05:26:46 +00:00
Subrata Banik 4df75dc498 soc/intel/tigerlake: Maintain consistent tab in iomap.h
This patch converts inconsistent white space into tab.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: If5e191b92e3e53b43335136ef51bc62589b955a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-10 05:26:21 +00:00
Vinod Polimera 3b4c45efa2 sc7180: Add display hardware pipe line initialization
Add sc7180 display hardware pipeline programming support
and invoke the display initialization from soc_init.

Changes in V1:
- added display init required check.
- added edid read function using i2c communication.
- added sn65dsi86 bridge driver to init bridge.
- moved display initialization to mainboard file.

Changes in V2:
- moved diplay init sequence to mainboard file
- moved edid read function to bridge driver.
- calculated timing paramters using edid parameters.
- removed command mode config code.
- moved bridge driver to drivers/ti.
- seperated out bridge and soc code with mainboard file as interface.

Changes in V3:
- add GPIO selection at runtime based on boardid.
- add vbif register struct overlay.

Changes in V4:
- update gpio config for lazor board.

Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10 00:25:26 +00:00
Vinod Polimera c4e0b0a313 sc7180: Add support for sn65dsi86 bridge
Add sn65dsi86 bridge driver to enable the eDP bridge.
Datasheet used : https://www.ti.com/lit/ds/sllseh2b/sllseh2b.pdf

Changes in V1:
- fix the dp lanes using mask
- separate out the refclk and hpd config to init function

Change-Id: I36a68f3241f0ba316c261a73c2f6d30fe6c3ccdc
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10 00:24:42 +00:00
Vinod Polimera c6880b3e9d sc7180: Add display dsi interface programming
This change adds support for sc7180 dsi interface host programming.

Changes in V1:
- remove dual dsi config code.
- update register access using struct overlays.
- remove dsc config & command mode code.

Changes in V2:
- remove dsi read and write functions.
- remove target and panel related code.

Changes in V3:
- move prototypes to headers.
- define macros for constants.

Changes in V4:
- define register bits instead of hardcoded values.

Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10 00:22:50 +00:00
T Michael Turney 0b493bbb9e sc7180: enable bl31
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/28014/44

Change-Id: Ia961ee0e30478e21fd786ce464655977449df510
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10 00:22:39 +00:00
Angel Pons 43810cb179 soc/intel/common/block/imc: Drop unused code
Nothing uses this code anymore.

Change-Id: I5da1020597c126a40b015beb6e43fb0168aa330f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-09-09 23:21:19 +00:00
Vinod Polimera 4cdd0979ca sc7180: Add display 10nm phy & pll programming support
Adds basic headers as well as source required for display
dsi 10nm phy & pll programming.

Changes in V1:
- add struct overlays to model hardware registers.
- remove typedef structures.
- remove dead code such as dual dsi,split config etc.

Changes in V2:
- remove panel related header files.
- update the bitclock calculation using edid parameters.
- add phy timing calculation function.
- update copyright license.

Changes in V3:
- update the mdss clock structure.
- remove dsi_phy_configinfo_type struct.
- remove unused struct fields.

Changes in V4:
- update clock apis.
- remove unused structures.

Change-Id: I8ff400922ae594f558cf73a5aaa433a3a93347c2
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09 22:09:09 +00:00
Taniya Das dc92cea680 sc7180: clock: Add display external clock in coreboot
Add support for display external clock in coreboot for SC7180.

Tested: Display clocks are configured.

Change-Id: Ida222890252b80db738fa1f685b212b3f7c6e689
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09 22:08:49 +00:00
Ashwin Kumar 6856ae468e trogdor: Change Memlayout to increase QcLib region from 512 to 596kB
Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09 22:08:34 +00:00
vsujithk 32aed01c6a sc7180: GPIO: Add I2S configuration for google/trogdor
Configure GPIO pins as I2S mode for audio speaker.

The audio speaker does not work on Trogdor revision 1, as the
layout was changed.

Developer/Reviewer reference, be aware of this issue:
https://partnerissuetracker.corp.google.com/issues/146533652

Change-Id: Ia4bbfea591a3231640b53e64f0e4e9d43c4437a3
Signed-off-by: vsujithk <vsujithk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09 22:08:19 +00:00
ashk b05e540217 trogdor: SoC makefile blob support
Following blobs will includes with SoC makefile:
  * AOP
  * BOOT
  * QTISECLIB
  * QCSEC
  * QUPV3FW

Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09 22:07:31 +00:00
David Wu 43e601312b mb/google/volteer/var/trondo: Add memory parts and generate DRAM IDs
Add memory parts and generate DRAM IDs for trondo.

BUG=None
TEST=FW_NAME=trondo emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2e89ecaf73a30595ed48ac9ce94ccbd4bb7ed3c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45164
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 14:58:07 +00:00
Johnny Lin d04c06b472 drivers/ipmi: Add CONFIG_IPMI_KCS_TIMEOUT_MS for IPMI KCS timeout value
With the current timeout of 1000 cycles of 100 microsecond would see
timeout occurs on OCP Delta Lake if the log level is set to values
smaller than 8. Because the prink(BIOS_SPEW, ..) in ipmi_kcs_status()
creates delay and avoid the problem, but after setting the log level
to 4 we see some timeout occurs.

The unit is millisecond and the default value is set to 5000 according
to IPMI spec v2.0 rev 1.1 Sec. 9.15, a five-second timeout or greater
is recommended.

Tested=On OCP Delta Lake, with log level 4 cannot observe timeout
occurs.

Change-Id: I42ede1d9200bb5d0dbb455d2ff66e2816f10e86b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45103
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 13:39:36 +00:00
nick_xr_chen 44097e21cc mb/google/volteer/variants/eldrid: add memory.c for ddr4 support
Add new memory.c to support DDR4 memory types.

Use the new meminit_ddr() and variant_memory_sku() for eldrid variant
code on memory.c

The initial settings override the baseboard from volteer and fine tune
gpio.c and overridetree.cb on eldrid's configuration.

BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that Eldrid
can boots. NOTE that tests the ddr4 side of the implementation.

Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-09 13:37:41 +00:00
Philipp Deppenwiese 404a42bb3a 3rdparty: Add submodule intel-sec-tools
Project: https://github.com/9elements/converged-security-suite
License: BSD-3

Tooling for Intel platform security features

Change-Id: I7421b30eb38e64cf6b77b7e1c485c5700728997b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 13:08:25 +00:00
Sam Lewis 266c136304 soc/ti/am335x: Fix MLO build
Allows the AM335X to boot from the coreboot generated MLO by:

- Fixing the load address in the MLO header to be the start of SRAM
- Fixing the way that the bootblock size is calculated (which is
  embedded into the MLO so that the MLO knows how much to load into
  SRAM). The previous method relied on parsing cbfstool output - the
  output has changed format since this was originally written so this no
  longer works. Directly using the filesize of the built binary is
  probably a more stable way of doing this.

As part of this, the start addresses of SRAM and DRAM were fixed to be
consistent with the AM335x Technical Reference Manual (spruh73, rev Q).

TEST: Booted Beaglebone Black from MLO placed at offset 0x00 on an SD card

Change-Id: I514d7cda65ddcbf27e78286dc6857c9e81ce6f9e
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44381
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 10:49:05 +00:00
Sam Lewis f58fb59ea0 mb/ti/beaglebone: Init UART in early init
The console is initialized before mainboard_init, so the peripheral
should be initialized in bootblock_mainboard_early_init rather than
bootblock_mainboard_init.

Change-Id: I9f4ba29798eb0b1efea76f5ade4a234fb35a2f83
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-09 10:48:56 +00:00
Angel Pons 3ecee09ebb soc/intel/common/block/uart/Kconfig: Drop unused symbols
They are not referenced anywhere.

Change-Id: Iff2d3b0063da5796e0bff1ada08b0a544c3f9a5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-09 10:47:21 +00:00
Rob Barnes 97dd498815 util/mb/google: Update dalboz/trembyle template
- Fix relative path to spd folder.
- Add spd folder with empty files.

BUG=None
TEST=None

Change-Id: Iae88ff9c8255f60544312f0eeadf1ce617437baf
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-09 10:46:43 +00:00
Rob Barnes ad1da3a326 util/spd_tools: Support comments in mem_parts_used
Allow comments prefixed with '#' in mem_parts_used csv file.

BUG=None
TEST=Run gen_part_id with mem_parts_used file containing comments

Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-09 10:46:03 +00:00
Angel Pons eeb4705fff soc/intel/xeon_sp: Select CPU_INTEL_COMMON
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select
CPU_INTEL_COMMON directly, to avoid dependency problems.

Tested with BUILD_TIMELESS=1: Without including the config file in the
coreboot.rom, both OCP Tioga Pass and Delta Lake remain identical.

Change-Id: I565e75869be730e7c2fe7114b829941bc9890e6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45041
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 10:40:40 +00:00
Patrick Rudolph 9d63a6b46d drivers/aspeed/common: Support disabled P2A bridge
This ports Linux commit 71f677a91046599ece96ebab21df956ce909c456
"Handle configuration without P2A bridge".

Quote:

    The ast driver configures a window to enable access into BMC
    memory space in order to read some configuration registers.

    If this window is disabled, which it can be from the BMC side,
    the ast driver can't function.

    Closing this window is a necessity for security if a machine's
    host side and BMC side are controlled by different parties;
    i.e. a cloud provider offering machines "bare metal".

P2A stands for primary to AHB.

Tested on Prodrive Hermes, which uses an AST2500. The machine still
boots, has a high resolution framebuffer working in EDK2, and its
boot time has been reduced by 2.5 seconds as it no longer runs into
a timeout due to disabled P2A bridge.

Change-Id: I3293dc35ae89c010154e02eff904ec3a68c96683
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-09-09 10:37:13 +00:00
Patrick Rudolph 7f29896c77 soc/intel/cannonlake: Add PCIe ports on PCH-H
Fixes complains about missing INT configuration by the pciexp kernel
modules.

Tested with Linux 5.5 on Prodrive Hermes.

Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-09 10:36:11 +00:00
Angel Pons c6c9b9cf48 apollolake: Define MAX_CPUS at SoC scope
The three Intel Apollo Lake boards (apl_rvp, leafhill and minnow3) do
not define MAX_CPUS, which would then default to 1. Since this is most
likely an oversight, use the same value as other Apollo Lake boards.

To ensure this does not happen again, factor out MAX_CPUS to SoC scope.

Change-Id: I5ed98a6b592c8010b59eca7ff773ae1ccc4cd7b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45144
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 10:35:34 +00:00
Angel Pons c95f507fc7 apollolake: Limit MAX_CPUS to 4
APL does not support Hyper-Threading, and has at most four CPU cores.

Change-Id: Ib2ffadc0c31cdd96bec8eed5364c984acb2e1250
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45143
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 10:35:13 +00:00
Angel Pons f4779e8679 geminilake: Factor out MAX_CPUS value
Both Gemini Lake boards in the tree use the same value.

Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-09 10:34:51 +00:00
Angel Pons b36100faf4 soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbol
For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`.

Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-09 10:34:32 +00:00
Subrata Banik ee73594575 vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332
List of changes:
1. Select FSP_HEADER_PATH
2. Select FSP_FD_PATH
3. Select PLATFORM_USES_FSP2_2
4. Select UDK_202005_BINDING

Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-09 05:16:34 +00:00
David Wu 299cb4bb8a mb/google/puff: Increase DPTF parameters for faffy
Update critical and passive policy for TSR0.

BUG=b:167477885
BRANCH=puff
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 00:11:58 +00:00
Julius Werner 8e0f9f30f6 3rdparty/qc_blobs: Uprev to new HEAD (6b7fe498eb)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2de0c13000e5b1e32e9c1a6de3daa09acf6c321b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45057
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 00:02:00 +00:00