Commit Graph

35590 Commits

Author SHA1 Message Date
Angel Pons a92878152f 3rdparty/libhwbase: Update submodule pointer
This brings in 5 new commits:
* 69e9086 mutime: Make Sinfo an imported constant
* 9f87a10 time: Add T_First constant
* 4e22910 Makefile: Adapt $(space) definition
* d822df5 Makefile: Delay expansion of `$(ADAFLAGS)`
* a3edc6e Makefile: Add `-gnatw_R` to suppress spurious warning

Change-Id: I907e66fcf85da256a112a7069a3c551a6d8caaf0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43558
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 12:09:30 +00:00
Srinidhi N Kaushik 9ea45ffb39 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3274
Update FSP headers for Tiger Lake platform generated based FSP
version 3274.

Compared to the current version 3197, v3274 adds most of the legacy UPDs
in both FSPM and FSPS.

BUG=b:159151231
BRANCH=none
TEST=build and boot volteer proto2

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Id3f957aa9d9ad9710a3c930717c22f485699315e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43473
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 03:59:46 +00:00
Angel Pons 45d5f8f163 sio/nuvoton/common/early_serial.c: Guard serial enable
If CONSOLE_SERIAL is not set, do not reconfigure the UART LDN.
Otherwise, SerialICE stops working when the UART LDN is disabled.

Change-Id: Ie3113e6b7b830dfdddc4d7709f00719f29e094bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-19 18:18:12 +00:00
Maxim Polyakov 75db8c8ea8 soc/intel/common/gpio_defs: Fix coding style
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.

Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41035
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Michael Niewöhner
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-19 16:25:05 +00:00
Nico Huber 666c8f8fc5 mb/qemu-i440fx/memmap: Add warning when falling back to CMOS infos
Change-Id: Iefac6fd45791cf6a051450b41046f7e7ebc1dc41
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19 11:20:15 +00:00
Nico Huber d2245d890b mb/qemu/fw_cfg: Fix return code check for fw_cfg_e820_select()
Change-Id: I22b9eb6ead37dbba6807d145468843bd01c94c84
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19 11:20:10 +00:00
Nico Huber ef59c93f77 mb/qemu/fw_cfg: Add info messages about (not) found files
Print some more information at BIOS_INFO, like our CBFS code does.

Change-Id: I1431d569c57634277ea5cf7feb352419db432b44
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43444
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-19 11:20:05 +00:00
Tim Wawrzynczak 0115ba8835 Documentation: Add documentation for drivers/intel/dptf chip driver
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8915ead08a89dcf95fd92983eca5f85b82916dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-18 16:05:43 +00:00
Tim Wawrzynczak f524188f48 ec/google/chromeec: Fix oversights in ec_dptf_helpers
GTSH was 2 instead of 20 (so it's 2 degrees K hysteresis), and TSRD was
accidentally defined to take 0 arguments, instead of 1.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I14d28bacf44ac65043060b8579b3fbcec758c56c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-18 16:05:33 +00:00
Tim Wawrzynczak bec6731c76 ec/google/chromeec: Fix \_SB.DPTF._OSC
The DPTF._OSC method incorrectly assumed that all available UUIDs would
be present in the IDSP package, but this is not always the case. Instead
of matching an incoming UUID against an index into IDSP, search the IDSP
package for the matching UUID.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I718b6abe09152647b14f7c1405b2d0d20035726b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-18 16:05:22 +00:00
Tim Wawrzynczak 752c471348 mb/google/dedede: Convert static DPTF ASL into devicetree entries
Since there is now a mechanism to generate DPTF ACPI tables and methods
at runtime, dedede should switch to using that instead of raw ASL files.
This patch converts the existing .asl files into devicetree entries.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6bb6e6e15f50a1e510080e16bbca09dfc5f16b1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43422
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18 16:05:07 +00:00
Tim Wawrzynczak c6a593bc3e drivers/intel/dptf: Add missing scope operator around TSR options
The previous DPTF patch train missed the proper scope operator around
all of the TSR options. Without this, the optional GTSH and/or _STR
Methods end up in the wrong scope.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9298c442c047c5f7f606574d900057a7c004b47f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43458
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18 16:04:51 +00:00
Tim Wawrzynczak 5212ece6cf dptf: Fix scope of TCPU device
In the initial DPTF refactor, the scope of the TCPU device was
incorrectly set as \_SB, instead of \_SB.PCI0. However, because of the
way that the acpi_inject_dsdt() callback currently works (it injects
contents before the dsdt.aml file), the Scope where the TCPU
device lives (\_SB.PCI0) doesn't exist yet. Therefore, to avoid playing
games with *when* things are defined in the DSDT, switch to defining all
of the DPTF devices in the SSDT.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia4922b4dc6544d79d44d39e6ad18c6ab9fee0fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43529
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18 16:04:42 +00:00
Tim Wawrzynczak 6d391e649f mb/google/volteer: Update DPTF with temp sensor 3
While the DPTF refactor was in progress, TSR3 was added to volteer's
dptf.asl file, and I forgot to update the devicetree with TSR3 as well.
Also missed a swap in the passive policies of TSR0 and TSR1. This patch
fixes those.

BUG=b:149722146
TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-18 16:04:31 +00:00
Furquan Shaikh ff75c21e6d mb/google/zork/var/vilboz: Use AMDI1015 HID for I2S machine device
Vilboz requires a different HID than rest of the zork variants. Hence,
this change sets the HID to AMDI1015 for I2S machine device in vilboz
overridetree.cb.

BUG=b:157708581

Change-Id: Ibae343f21cf8f0c782dc8a461f69172bf0da7eba
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43545
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 23:33:48 +00:00
Furquan Shaikh 0fba23bc64 soc/amd/picasso: Drop the addition of I2S machine device from ACP driver
I2S machine device has its own driver now. So, this change drops the
support for adding I2S machine device ACPI node from ACP driver.

BUG=b:157708581

Change-Id: I9069d92ae991e05fddcc7d45a2fd21e98c3b0de8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17 23:33:41 +00:00
Furquan Shaikh 24ec79c39b mb/google/zork: Switch to using newly added i2s_machine_dev driver
This change switches zork devices to use the newly added
i2s_machine_dev driver in devicetree rather than passing
dmic_select_gpio in SoC config.

BUG=b:157708581

Change-Id: I76c633694cbfb454c081ab2a4af4765bfbbae16b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17 23:33:35 +00:00
Furquan Shaikh de4baffb6b soc/amd/picasso: Add .scan_bus operation for ACP device
This change adds `.scan_bus` device operation for ACP device to allow
mainboards to add devices under it.

BUG=b:157708581

Change-Id: I088bf81d7c7c5f59ade1d2f0dd24e5fc2b1ff876
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43542
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 23:33:28 +00:00
Furquan Shaikh 03294a3849 drivers/amd/i2s_machine_dev: Add a driver for AMD I2S machine device
This change adds a new driver for AMD I2S machine device. Currently,
this device is added as part of `acp_fill_ssdt()` in Picasso, but with
addition of this driver, this device can be added just like any other
device in the devicetree.

BUG=b:157708581

Change-Id: I49d1a867d7941397acca1054632b6ad855a021de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17 23:33:23 +00:00
Furquan Shaikh 550cd05995 device: Increase DEVICE_PATH_MAX to 40
This change increases the maximum length of device path string to 40
characters to accommodate growing hierarchy of devices.

TEST=Ensured that "\_SB.PCI0.LPCB.EC0.CREC.TUN0.RT58" is correctly
added to SSDT.

Change-Id: Id2ef71a32b26e366b56c652942a247de4889544a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17 23:32:59 +00:00
Angel Pons 9837493e4f mb/asrock/b85m_pro4: Select MAINBOARD_USES_IFD_GBE_REGION
This board uses the in-PCH GbE controller, and its IFD has a GbE region.

Change-Id: Ifc09640b2ebd613d3d5566a13b50d36c11e3c346
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43522
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 20:20:01 +00:00
Furquan Shaikh b88409deb1 soc/amd/common/gpio: Add macro for PAD_NC
This change adds a macro `PAD_NC` for configuring no-connect pads. This
configures the pad as input with pull-down.

Change-Id: I47c41c88ccfebe2c5dd9a24f85a120af9c8f56b5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17 18:30:20 +00:00
Furquan Shaikh 538de782b1 mb/amd/mandolin: Drop mainboard.asl
This change drops mainboard.asl from zork because none of the objects
defined in it are used.

Change-Id: I879b5614fb5d12c4814ee52f840a000744a7aab9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43520
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 18:30:04 +00:00
Furquan Shaikh 538ebafe54 mb/google/zork: Drop mainboard.asl
This change drops mainboard.asl from zork because none of the objects
defined in it are used.

BUG=b:153879530

Change-Id: If5440bcbce39b4461b44acaec69561663b1ea329
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43519
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 18:29:56 +00:00
Furquan Shaikh 1917a3525c soc/amd/picasso: Drop _INI and OSFL methods
This change drops _INI and OSFL methods under \_SB since they are not doing
anything useful. _INI only calls OSFL and OSFL initializes OSVR if not
already initialized and returns OSVR value. However, OSVR is not used
anywhere and hence both these functions can be dropped.

BUG=b:153879530

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4f3e1c93a855006cc115087fded20bfb76c1133e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43515
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 18:29:44 +00:00
Furquan Shaikh dbac2b5912 soc/amd/picasso: Move PMOD global variable to globalnvs.asl
Global variable `PMOD` that stores the interrupt mode used by OS is
required by all mainboards. This change moves the variable definition to
globalnvs.asl under picasso.

Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC
until _PIC() method is called by OS. Thus, this change also updates the
default value of PMOD as 0 i.e. PIC mode.

BUG=b:153879530

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I731c03d965882281a7a23f55894451210ba72274
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 18:29:37 +00:00
Furquan Shaikh d2b173657a soc/amd/picasso: Drop empty method CIRQ
This change drops empty method CIRQ() from pci_int.asl.

BUG=b:153879530

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib342dcbc52cfacbd73a8a50ee087d97562d94c97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43513
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 18:29:28 +00:00
Aaron Durbin c1122168de mb/google/zork: correct wake gpe value for gpio 9
GPIO_9 is associated with gevent 22. Correct all the misconfigurations
and use macros for clarity as to what bit offset is being used instead
of open coding things.

BUG=b:161205804

Change-Id: Ic4cfd62763d72d12a55f89585f24e07df6af0f4f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43516
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 14:34:03 +00:00
Furquan Shaikh 28980fdf85 soc/amd/picasso: Use read-modify-write for ACP_I2S_PIN_CONFIG
This change uses read-modify-write to update ACP_I2S_PIN_CONFIG instead of
a write operation since the other bits in the register are reserved.

Change-Id: Ic64e1907858ec293c5f759e627d19c00d748a30e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43503
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 05:04:02 +00:00
Furquan Shaikh a469736cca mb/google/zork: Enable ACP_PME_EN and ACP_I2S_WAKE_EN
This change enables ACP_PME_EN and ACP_I2S_WAKE_EN for dalboz and trembyle
boards using devicetree settings.

BUG=b:161328042,b:146317284

Change-Id: Ie367a9ba878a1892177df874bbcb8005efeb0880
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43496
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 05:03:00 +00:00
Akshu Agrawal 42d4a57b77 soc/amd/picasso: Configure ACP_PME_EN and ACP_I2S_WAKE_EN
This change adds support for configuring ACP_PME_EN and ACP_I2S_WAKE_EN
using the mainboard setting for `acp_pme_enable` and `acp_i2s_wake_enable`
in the devicetree. This is required to get I2S_Wake event on headset jack
plug/unplug when using CODEC_GPI pad.

BUG=b:146317284,b:161328042

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Change-Id: I522d7497940f499fbc3181d866f2b44e979bba7a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1969104
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43495
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17 05:02:50 +00:00
Felix Held 34aab089e3 soc/amd/picasso: remove unused fadt_pm_profile devicetree setting
commit 56da63c3dc removed overriding that
field in the FADT.

Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 23:58:30 +00:00
Felix Held 12732536df mb/amd/mandolin: add SATA DXIO descriptor for Dali SKUs
Dali supports two SATA ports, but no PCIe alternate function on those
pins.

Change-Id: I27a13100e80565eb1dade2d703ba3d1f8b5f630f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16 23:39:06 +00:00
Felix Held 4794264ff1 mb/amd/mandolin: fix DXIO lane numbers
The DXIO descriptors use the logical and not the physical lane numbers,
which are different.

Change-Id: I7a90056d782d8d32fe34a0f5bdb61c3b61df1af8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16 23:38:44 +00:00
Martin Roth b39e10dbaa soc/amd/common: Don't get eSPI address from PCI if not on x86
Exclude lpc_get_spibase() on the PSP.  This also simplifies the
espi_get_bar() function.

BUG=b:159811539
TEST=Build & boot trembyle; Verify address in PSP & x86

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5927dd40610860b54bb35a7e5b03ddb731597745
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43468
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 22:20:53 +00:00
Martin Roth 37d1206c6e soc/amd/picasso: Get rid of VERSTAGE_SIZE
Currently, the code and data in psp_verstage is ~59K.  Adding the code
to save vbnv to the SPI rom increases that to 66K.

Getting rid of VERSTAGE_SIZE allows verstage to grow as it needs to.

BUG=b:161366241
TEST=Build & Boot Morphius with VBOOT_VBNV_CMOS_BACKUP_TO_FLASH enabled

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic6853b70073f9e781fc10402a2a47c9c8e0d49d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43486
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 22:20:27 +00:00
Martin Roth 6812626382 soc/amd/stoneyridge: Remove unused SPI #defines
These #defines are not used, and conflict with #defines in
amdblocks/spi.h

BUG=None
TEST=Build stoney platforms

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I29b77a6b21a4deda6f28f5b057988cf3921540e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-16 17:38:57 +00:00
Raul E Rangel 79ab7d7780 soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatus
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390
No reason to have the firmware do it as well.

BUG=b:153001807, b:154756391
TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI
errors.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16 17:20:04 +00:00
Raul E Rangel d458358379 soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variable
PMx0EE is not defined in the Picasso PPR.

BUG=b:153001807, b:154756391
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16 17:11:29 +00:00
Raul E Rangel b20a16ef4e mb/amd/mandolin/.../sleep.asl: Remove unnecessary variable
There is no reason to create a named variable. We can just return the
package.

BUG=b:153001807, b:154756391
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic0ca2e6d4fb833c68d29e9948a670ace7c89b6a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16 17:10:34 +00:00
Ronald G Minnich a92a07d9c0 libpayload: allow nonblocking delay and more than one delay
Extend the local APIC timer delay so that it can be started,
and waited for, independently.

Add an EOI so that more than one APIC timer interrupt is possible.
Previous to this, because there was no EOI, the first timer
interrupt the CPU took was also the last it would take --
apic_delay would only work one time.

Change-Id: Ib11aeee5b7da81287166ac68fc327e7ae62d1b84
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-16 16:48:42 +00:00
Furquan Shaikh bf6541d876 soc/amd/picasso: Drop mainboard_romstage_entry_s3
mainboard_romstage_entry_s3() was dropped from zork (CB:43476). This
function call in picasso does not do anything and hence is being dropped.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I10e15422d7eef5af9c19737c32e433718b6479d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43477
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 16:45:57 +00:00
Furquan Shaikh bf9eb00c11 mb/google/zork: Move variant_pcie_gpio_configure() to bootblock
On zork, bootblock is part of RW firmware in non-recovery mode, so PCIe
GPIOs can be configured early on in bootblock rather than waiting until
romstage. This change moves the call to variant_pcie_gpio_configure() to
happen in bootblock and drops romstage.c file.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic515304f35fe5623d58d6000efcb11fb9039e137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43476
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 16:45:48 +00:00
Furquan Shaikh 56f949cd0c mb/google/zork: Drop variant_romstage_gpio_table()
gpio_set_stage_rom table is now configuring only PCIe related GPIOs in
romstage. This change moves the configuration of PCIe related GPIOs to
variant_pcie_gpio_configure() to keep all the configuration for WiFi and
non-WiFi PCIe pads in one place. It also drops the function
variant_romstage_gpio_table() as it is unused.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 16:45:27 +00:00
Furquan Shaikh 6a5c77cc84 mb/google/zork: Drop redundant romstage GPIO table
Now that the power and reset GPIO configuration for non-PCIe devices is
dropped from romstage GPIO table, the tables for pre-v3 and v3 version of
schematics are exactly same. So, this change drops the duplicate table and
also removes the check for v3 schematics when configuring the pads in
romstage.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I67ca9f587c3f47912393ebaf38badcc9d76cc393
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16 16:39:25 +00:00
Furquan Shaikh ddfec569d1 mb/google/zork: Drop power and reset control in romstage for dalboz
This change drops power and reset control for non PCIe devices in
romstage for dalboz reference as this is not required.

 +---------------------------------------------------------------------------------------+
 | GPIO|    Net name   | External| Internal| Domain| State at reset | State on S3 resume |
 |  #  |               | Pull    | Pull    |       |                |                    |
 +---------------------------------------------------------------------------------------+
 |  5  | PEN_POWER_EN  | 100K PD |   PD    | S5    | Powered off    | Powered on         |
 |     |               |         |         |       | (because of    | (since power is not|
 |     |               |         |         |       |  internal PD)  |  disabled when     |
 |     |               |         |         |       |                |  entering S3)      |
 +---------------------------------------------------------------------------------------+
 |  6  |EN_PWR_TOUCHPAD| 499K PD |   PU    | S5    | Powered on     | Powered on         |
 |     |               |         |         |       | (because of    | (since trackpad    |
 |     |               |         |         |       |  internal PU)  |  is wake source)   |
 +---------------------------------------------------------------------------------------+
 | 68  | EMMC_RESET_L  | 100K PU |   PD    | S0    |  Asserted      | Asserted           |
 |     |               |         |         |       |  (because of   | (because of        |
 |     |               |         |         |       |   internal PD) |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 | 76  | EN_PWR_CAMERA | 499K PD |   PD    | S0    | Powered off    | Powered off        |
 |     |               |         |         |       | (because of    | (because of        |
 |     |               |         |         |       |  internal PD)  |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 | 140 | USI_RESET     | 10K PD  |   PD    | S0    | Deasserted     | Deasserted         |
 |     |               |         |         |       | (because of    | (because of        |
 |     |               |         |         |       |  internal PD)  |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 | 141 | USB_HUB_RST_L | 10K PU  |   PD    | S0    | Asserted       | Asserted           |
 |     |               |         |         |       | (because of    | (because of        |
 |     |               |         |         |       | internal PD)   |  internal PD)      |
 +---------------------------------------------------------------------------------------+
 +---------------------------------------------------------------------------------------+
 | 67  |EN_PWR_TOUCHPAD| 10K PU  |   PD    | S0    | Powered off    | Powered off        |
 |     |_PS2 (pre-V3)  |         |         |       | (because of    | (because of        |
 |     |               |         |         |       |  internal PD)  |  internal PD)      |
 +---------------------------------------------------------------------------------------+

GPIO_140 starts deasserted out of reset and S3 resume, but gets
asserted in ramstage since it is eventually deasserted by OS using
ACPI methods.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie792a5a9d6420763ff10d1e475c094b6ee514888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16 16:39:16 +00:00
Furquan Shaikh 9961343e67 mb/google/zork: Drop power and reset control in romstage for trembyle
This change drops power and reset control for non PCIe devices in
romstage as this is not required.

+---------------------+--------------------------------------------+--------------------+
| GPIO|    Net name   | External| Internal| Domain| State at reset | State on S3 resume |
|  #  |               | Pull    | Pull    |       |                |                    |
+---------------------------------------------------------------------------------------+
|  5  | PEN_POWER_EN  | 100K PD |   PD    | S5    | Powered off    | Powered on         |
|     |               |         |         |       | (because of    | (since power is not|
|     |               |         |         |       |  internal PD)  |  disabled when     |
|     |               |         |         |       |                |  entering S3)      |
+---------------------------------------------------------------------------------------+
| 13  |EN_PWR_TOUCHPAD| 499K PD |   PU    | S5    | Powered on     | Powered on         |
|     |_PS2           |         |         |       | (because of    | (since trackpad    |
|     |               |         |         |       |  internal PU)  |  is wake source)   |
+---------------------------------------------------------------------------------------+
| 68  | EMMC_RESET_L  | 100K PU |   PD    | S0    |  Asserted      | Asserted           |
|     |               |         |         |       |  (because of   | (because of        |
|     |               |         |         |       |   internal PD) |  internal PD)      |
+---------------------------------------------------------------------------------------+
| 76  | EN_PWR_CAMERA | 499K PD |   PD    | S0    | Powered off    | Powered off        |
|     |               |         |         |       | (because of    | (because of        |
|     |               |         |         |       |  internal PD)  |  internal PD)      |
+---------------------------------------------------------------------------------------+
| 140 | USI_RESET     | 10K PD  |   PD    | S0    | Deasserted     | Deasserted         |
|     |               |         |         |       | (because of    | (because of        |
|     |               |         |         |       |  internal PD)  |  internal PD)      |
+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------+
| 67  |EN_PWR_TOUCHPAD| 10K PU  |   PD    | S0    | Powered off    | Powered off        |
|     |_PS2 (pre-V3)  |         |         |       | (because of    | (because of        |
|     |               |         |         |       |  internal PD)  |  internal PD)      |
|     |               |         |         |       |                |                    |
+-----+---------------+---------+---------+-------+----------------+--------------------+

GPIO_140 starts deasserted out of reset and S3 resume, but gets
asserted in ramstage since it is eventually deasserted by OS using
ACPI methods.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ieadc62f1a13857209cf0a62f204efb9278e0e97d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16 16:39:09 +00:00
Furquan Shaikh eb912ed9ad mb/google/zork: Keep USI_RST asserted in ramstage
This change keeps USI_RST(GPIO_140) asserted in ramstage since it gets
deasserted by OS using ACPI methods.

BUG=b:160854397

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I8feced788e471a0efb2358d42b2146df04fb7a0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43461
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 16:38:55 +00:00
Furquan Shaikh 19a2a2db7e mb/google/zork: Keep pen power enabled in sleep state
This change keeps pen power enabled in sleep state to allow it to
charge in S3.

BUG=b:155422911

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6190496653878327f34a01f6a743db474d32e929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43452
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16 16:37:06 +00:00
Philipp Deppenwiese 96dc015519 Revert "mb/ocp/deltalake: Select IPMI OCP to send POST start/end command"
This reverts commit a5ca4a0c75.

Reason for revert: Breaks coreboot tree because of non existent kconfig symbol

Change-Id: Ib8f55dc2f6444690945bc2dc64baad5d0c39cdf4
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16 16:32:46 +00:00