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Author SHA1 Message Date
Tim Chu 0c094aeb0e arch/x86/smbios: Update SMBIOS type 17 type detail 
Update SMBIOS type 17 type detail. Define this field by module type.

Tested=Execute "dmidecode -t 17" to check type detail is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I6700056edad5db2b86f6da526329b1343b026385
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
 2021-01-19 09:02:25 +00:00
Johnny Lin 9918c34d87 mb/ocp/deltalake: Make use of vpd_get_int to clean up code 
Tested=On OCP Delta Lake, verify the VPD values can be read
correctly.

Change-Id: I1c27cb61cd52902c92b3733e53bc8e6fd6a5fe7f
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-19 09:00:58 +00:00
Arthur Heymans 418bc72d01 nb/intel/ironlake/ironlake.asl: Remove sandy bridge copy pasta 
Change-Id: Ic5a49a81a886aecde0fbaae3ecfa6b0504a4e3ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-19 09:00:35 +00:00
Arthur Heymans 1a98880228 nb/intel/ironlake: Remove chromeos copy pasta 
Change-Id: Ic2582dbf70e11e0566ba525c72300a6248807512
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-19 08:59:36 +00:00
Elyes HAOUAS 02d4318ae2 security/tpm/tss/tcg-1.2/tss.c: Use __func__ 
Change-Id: I51e7111b17274b8951925d1c13e2f1386778b93a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
 2021-01-19 08:58:50 +00:00
Elyes HAOUAS 103c1205e7 drivers/spi/tpm/tpm.c: Use __func__ 
Change-Id: I8a8b0575689d7b63fd37edc457abc42710a13e97
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
 2021-01-19 08:58:41 +00:00
Angel Pons b600d41c3f nb/intel/ironlake: Print MCH dev/revision IDs and CAPID 
Given the lack of documentation for this platform, having this info
in coreboot logs (e.g. from board_status) can be pretty useful.

Change-Id: I6a743c1efc1b6da71589460a69bfe4785e3e77a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-01-19 08:58:17 +00:00
Elyes HAOUAS d0a62c667d drivers/spi/tpm/tis.c: Use __func__ 
Change-Id: I2941d4480a7c88b6c020a9da584135a0030fccfe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
 2021-01-19 08:58:04 +00:00
Elyes HAOUAS 52016659a4 drivers/i2c/tpm/cr50.c: Use __func__ 
Change-Id: If2751f3672072b7fa421ae33dc6e1490fdf35247
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
 2021-01-19 08:58:00 +00:00
Elyes HAOUAS b45219e720 drivers/i2c/tpm/tpm.c: Use __func__ 
Change-Id: I28f976118a380ef05a98257e9d57aadc26b69cb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
 2021-01-19 08:57:55 +00:00
Elyes HAOUAS 421285ebc0 drivers/i2c/tpm/tis.c: Use __func__ 
Change-Id: I598d27995fad7582ff41f4e7deaeb2e75e8ebde9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
 2021-01-19 08:57:53 +00:00
xuxinxiong 9448682239 mb/google/kukui: Add discrete EMCP LPDDR4X table for Kakadu/Katsu 
Add EMCP LPDDR4X DDR MT29VZZZCD9GQKPR for ram id 8.

BUG=b:176262460
BRANCH=master
TEST=emerge-jacuzzi coreboot

Change-Id: If00478b9b05ab3ec48b6a8dec37e9f2f9f04e188
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49447
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-19 08:57:12 +00:00
Peter Marheine 64fad6feb3 mb/google/zork: remove MST i2c from dalboz 
Dalboz variants do not use an MST hub; remove the i2c tunnel for it.
That bus is actually connected to the battery on these devices, which
should not be exposed to the AP.

BUG=b:175658311
TEST=builds
BRANCH=zork

Change-Id: If1714a5c441bf185efd2517c7c94e57b5f351f5a
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49628
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-19 08:56:51 +00:00
Elyes HAOUAS 9f23583fa7 soc/mediatek/mt8173/dramc_pi_calibration_api.c: Use __func__ 
Change-Id: I461012b164bbd6f2d1162a793903aafe0b15e234
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
 2021-01-19 08:56:30 +00:00
Elyes HAOUAS e795772585 soc/mediatek/mt8173/pmic_wrap.c: Use __func__ 
Change-Id: I3fb4db3fbb72d1444c84b9b66193c26a07561a3f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
 2021-01-19 08:56:27 +00:00
Hsin-Hsiung Wang 5497194334 soc/mediatek/mt8192: pmic: enable pwrkey long-press shutdown setting 
Update the settings of long press shutdown to avoid rtc alarm boot.

BUG=b:174546890
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I0841e55674f6b26f355ab678a73d4060fe93f27c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49354
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-19 08:27:27 +00:00
Hsin-Hsiung Wang cad3f47cda soc/mediatek/mt8192: pmic: update initial setting 
We found that the switch frequency of vgpu is at 4~5Mhz with high
current case (> 3.5A) and is at 2.5Mhz with low current case(< 2.8A).
The switch frequency of vgpu should be kept at 2.5Mhz.

The root cause is that phase config of vcore is not disabled, it will
affect the switch frequency of vgpu. Corret the phase setting at
initialization.

BUG=b:172636735
BRANCH=none
TEST=boot asurada correctly

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49005
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-19 08:26:41 +00:00
Yuchen Huang ec39cb3a80 soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driver 
Add clkbuf and srclken_rc init for low power.

Reference datasheet:
  Document No: RH-D-2018-0205.

TEST=boot asurada

Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Change-Id: I947bf14df7a307bf359c590c2a20265882b3f1be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-01-19 04:02:07 +00:00
Huayang Duan 68cb9ed068 soc/mediatek/mt8192: Save dramc shuffle result after calibration 
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-01-19 01:32:31 +00:00
Huayang Duan 7ce9883058 soc/mediatek/mt8192: Add dramc ac timing setting 
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-01-19 01:31:14 +00:00
Huayang Duan c37b9aa9f0 soc/mediatek/mt8192: Get DDR base information after calibration 
After calibration, we can get ddr vendor id or density info from
MR5 or MR8, this helps to make sure the DDR HW is as we expected.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ie62948368716d309aab8149372b2b6093fc33552
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2021-01-19 01:30:55 +00:00
Nico Huber 58ba83fe74 nb/intel/gm45: Reserve MMIO and firmware memory below 1MiB 
It looks like we didn't care to reserve the VGA MMIO (a & b segments)
and the c..f segments, initially. It was probably never needed until
the new resource allocator that will make use of any unclaimed space.

Change-Id: Iebdae64914d9f8301cafc67a5aba933c11294707
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-18 23:01:28 +00:00
Kyösti Mälkki 5fde1b7669 mb/apple,lenovo,roda: Drop reference to OSYS 
It is claimed getac/p470 has this implemented and not
as a TODO.

Change-Id: Ifa9ec5bcb8b25b6334b589e4bc7bcb915e85e349
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49349
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-18 18:05:02 +00:00
Kyösti Mälkki 3b947e2094 mainboards: Move get_cst_entries() 
Change-Id: I02cfbcb7a340bd574290e4ac486010fc4cbcd3be
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49351
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-18 18:04:28 +00:00
Kyösti Mälkki 66c6413c69 ACPI: Refactor ChromeOS specific ACPI GNVS 
The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.

If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.

If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.

Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.

Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-18 18:02:27 +00:00
Zheng Bao c4a6628a6f mb/amd/majolica: Add option of ROM size 
Change-Id: I07740285658aa098d3785cbead173b2f3acca42d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-01-18 14:21:46 +00:00
Elyes HAOUAS 1bc87143a4 device/oprom/x86emu/sys.c: Use __func__ 
Change-Id: Ia278e1f2d1162fa9541bf0cead3b2734144190be
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-01-18 09:44:02 +00:00
Patrick Georgi 8e400f0cca Revert "nb/intel/gm45/gm45.h: Remove duplicated include" 
This reverts commit 27af8a7e5d.

Reason for revert: This depends on CB:45517 which hasn't landed yet.

Change-Id: I2a6fbf54cfe01bf25e9ea8da84f6f2a17418f0ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49647
Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-01-18 09:40:00 +00:00
Elyes HAOUAS 2e2f72ec8a drivers/ocp/dmi/Kconfig: Set FRU_DEVICE_ID depend on OCP_DMI 
This will remove "CONFIG_FRU_DEVICE_ID=0" from ".config" when unused.

Change-Id: Ic50de165c1f3de3886d3cd1ae66853c9fad35ed2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-01-18 07:50:46 +00:00
Elyes HAOUAS 2826cdccd1 drivers/ti/sn65dsi86bridge: Add parentheses to Macros 
Change-Id: I2f3a9885171995633d0bfb22b7ff8ef8a68683b8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-01-18 07:48:09 +00:00
Elyes HAOUAS 1e4779e87e soc/intel/braswell/chip.c: Use __func__ 
Change-Id: I96b302f5a1f10daaed017a2453d1568a2e49e4ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-01-18 07:47:24 +00:00
Elyes HAOUAS ce5b1d1ec7 mb/ocp/tiogapass/ramstage.c: Remove duplicated include 
Change-Id: I6549ad6704c62b968ff9eb59cc698107c0120fb8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-01-18 07:46:47 +00:00
Elyes HAOUAS 5edd51f3c2 security/intel/stm/StmPlatformSmm.c: Remove repeated word 
Change-Id: I45adc4622f2d3358c703259931bafc4511395a5a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-01-18 07:46:13 +00:00
Elyes HAOUAS f669c81cf4 northbridge/intel/x4x/dq_dqs.c: Remove repeated word 
Change-Id: Iee24c6bf82ab6ff6691707ed0c388cfe492cc925
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-18 07:45:55 +00:00
Elyes HAOUAS 4ff66dc08f soc/intel/xeon_sp/uncore.c: Remove duplicated include 
Change-Id: I2ac1035585b32ba65d0725067cff0c12c9f748c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-01-18 07:45:05 +00:00
Elyes HAOUAS 266c313bc1 soc/intel/xeon_sp/skx/soc_acpi.c: Remove duplicated include 
Change-Id: Icf4247a0a5fb7950c69c8f229a6629a4fa6980f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-01-18 07:44:39 +00:00
Elyes HAOUAS c36650143b drivers/maxim/max77686/max77686.h: Remove repeated word 
Change-Id: Iac77f401d80027231f8b6a3449cb57abf3d337ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:39:21 +00:00
Elyes HAOUAS 0afaff2611 lib/device_tree.c: Remove repeated word 
Change-Id: Id5279587231c539bd3ffc75b75b29d88ef30e56a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:38:49 +00:00
Elyes HAOUAS ba4dbf8c4c soc/amd/stoneyridge/romstage.c: Remove repeated word 
Change-Id: I38974b532f41830f49b54444d98e6bd7aa417aba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:38:33 +00:00
Elyes HAOUAS 4537332d64 northbridge/intel/gm45/bootblock.c: Remove repeated word 
Change-Id: Ie3bfdb27aa7c981a500e82b6a6958576e0048bcd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:38:22 +00:00
Elyes HAOUAS 1550469234 ec/google/chromeec/ec_commands.h: Remove repeated word 
Change-Id: I87d5a5fa584b4250bc8b532c046e6bd070e33e81
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:38:09 +00:00
Elyes HAOUAS 6538d91bc3 northbridge/intel/x4x/raminit_ddr23.c: Remove repeated word 
Change-Id: I9763499ad5cf0395c83770908a277f089ceed475
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:37:17 +00:00
Elyes HAOUAS 5345a3841d include/edid.h: Remove repeated word 
Change-Id: Ia6dfc89e575e1a47f980a008ae7334fc21afde89
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:37:04 +00:00
Elyes HAOUAS 2d634c9069 security/vboot/secdata_tpm.c: Remove repeated word 
Change-Id: Idc17a4305398defd19e7f6ba2fc00bf69af34c4b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:36:49 +00:00
Elyes HAOUAS 98d6f33c0b northbridge/intel/sandybridge/bootblock.c: Remove repeated word 
Change-Id: I9e723e1d31b093a4781413efe7f290a295b833dc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:36:31 +00:00
Elyes HAOUAS 5323bf422f include/memrange.h: Remove repeated word 
Change-Id: Id010c72bbbb302f1756a53a228fa0bdd7ec7654b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:36:18 +00:00
Elyes HAOUAS 3ef8e21f33 soc/intel/broadwell/bootblock.c: Remove repeated word 
Change-Id: I3aec07d782e4315120a4365a65bdbcbf4a22e6f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:36:04 +00:00
Elyes HAOUAS 26e880e8a3 soc/intel/common/block/include/intelblocks/pmc_ipc.h: Remove repeated word 
Change-Id: I646583f7f0d0e0f6a91bc99b7edda964337d837e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:35:48 +00:00
Elyes HAOUAS 9148cd145f soc/intel/common/block/itss/itss.c: Remove repeated word 
Change-Id: Icc4954bcc1540f1935b0e34107febb4a1e947a36
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:35:33 +00:00
Elyes HAOUAS 59ab203f1c soc/intel/skylake/chip.h: Remove repeated word 
Change-Id: Id5bf9255e9a16a4f311e3b15eb77ad6e4bb13f66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
 2021-01-18 07:35:14 +00:00