Commit Graph

36694 Commits

Author SHA1 Message Date
Patrick Rudolph 49ae596a59 soc/intel/common: Add support for LPSS UART in ACPI mode
Emit ACPI code for LPSS UARTs operating in ACPI mode. In this mode the
device vendor ID reads as 0xffff, the PCI devices is still operate.

Add ACPI device IDs for APL, GLK, SPT, SPT_H and CNP_H.

The mainboard's devicetree needs to be adapted to include the chip
driver and the PCI ID when it wouldn't have been hidden.

Example:
 chip soc/intel/common/block/uart
  device pci 19.2 hidden
   register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
  end # UART #2
 end

Tested on Linux 5.6 with Sunrise Point ACPI ID for UART2.
Tested on Windows for all other UARTs.

Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18 05:53:43 +00:00
Aaron Durbin 6dbec2d81b soc/amd/common: add GPE event logs
GPE events were not be recorded in the eventlog. Add those
to the eventlog when the status register indicates those events.

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifb3167fd24f2171b2baf1a65eb81a318eb3e7a86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17 17:41:22 +00:00
Aaron Durbin c30981c952 soc/amd/picasso: snapshot chipset state early in boot sequence
Previously the chipset state was snapshotted very late in the boot
(ramstage). Instead start gathering the state early in romstage
prior to calling any FSP routines so there's a clean snapshot.

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17 17:41:01 +00:00
Aaron Durbin d24e5f15f2 soc/amd/stoneyridge: remove unused soc_power_reg object
Now that no one is consuming this object, remove its definition.

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib5aeec1733b6c9fa49569e30c4c369f70af0939c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17 17:40:52 +00:00
Aaron Durbin 51c3ae4330 soc/amd/picasso: remove unused soc_power_reg object
Now that no one is consuming this object, remove its definition.

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I60e4a9bfdf2752923f46a35aaab7034f9fa9b309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17 17:40:39 +00:00
Aaron Durbin 9bed96eb56 soc/amd/common: removed unused functions
Now that all users of the functions manipulating global state
and using soc-specific objects are removed remove those functions.

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I18c4c8b0c7852dde8cf0b6b3f11e43e15c3ce155
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17 17:40:31 +00:00
Aaron Durbin 404a5c3b60 soc/amd/picasso: use new ACPI helper functions from common
Transition the current call sequence to using the newly added common
ACPI helper functions. Semantically, the expectations are that this
sequence is the equivalent of previous acpi_clear_pm1_status(). However,
in subsequent patches picasso will be snapshotting state way sooner than
ramstage.

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I34e2ba7c5cd123b98c39291537e74175ec043e85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17 17:40:23 +00:00
Aaron Durbin 5a5e4d05eb soc/amd/stoneyridge: use new ACPI helper functions from common
Transition the current call sequence to using the newly added common
ACPI helper functions. Semantically, the expectations are that this
sequence is the equivalent of previous acpi_clear_pm1_status().

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id3ae19013c68d2c97b084046f600596ecc462374
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17 17:40:11 +00:00
Aaron Durbin a244eb3dad soc/amd/common: add acpi_fill_gnvs()
In order to reduce code duplication provide an acpi_fill_gnvs()
helper function. Intent is to move stoneyridge and picasso over
to using this common implementation instead of duplicating it.

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I21c6e2c24eaf42f31ae57c05df7f633d7dc266d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17 17:40:01 +00:00
Aaron Durbin 746e598d07 soc/amd/common: add single function ACPI PM1 GPE helpers
The existing code in common/block/acpi is mixing multiple operations:
saving things to cbmem in common code but then soc code uses that
information, reliant upon soc-specific struct soc_power_reg object,
and only saving/snapshotting ACPI registers very deep in ramstage.

To unwind the above provide some functions that are more targeted:
- Add struct acpi_pm_gpe_state object
- Add acpi_fill_pm_gpe_state()
- Add acpi_pm_gpe_add_events_print_events()
- Add acpi_clear_pm_gpe_status()

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia7afed2861343802b3c78728784f7cfaf6f53f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17 17:39:54 +00:00
Harshit Sharma ac8e1062cb crossgcc: Enable GCC to get asan shadow offset at runtime
Unlike Linux kernel which has a static shadow region layout, we have
multiple stages in coreboot and thus require a different shadow offset
address. Unfortunately, GCC currently only supports adding a static
shadow offset at compile time using -fasan-shadow-offset flag.

For this reason, we enable GCC to determine asan shadow offset address
at runtime using a callback function named __asan_shadow_offset().
This supersedes the need to specify this address at compile time. GCC
then makes use of this shadow offset to protect stack buffers by
inserting red zones around them.

Some other benefits of having this GCC patch are:
a. We can place the shadow region in a separate linker section with
   all its advantages like automatic fit insurance. This ensures if
   a platform doesn't have enough memory space to hold shadow region,
   the build will fail. (However, if we use a fixed shadow offset on a
   platform that actually doesn't have enough memory, it may still
   build without any errors.)
b. We don't modify the memory layout compared to the current one, as
   we are placing the shadow region at the end of the space already
   occupied by the program.
c. We can be much more flexible later if needed (thinking of other
   stages like bootblock).
d. Since we are appending the shadow buffer to the region already
   occupied, we make efficient use of the limited memory available
   which is highly beneficial when using cache as ram.

Further, we have made sure that if you compile you tree with ASan
enabled but missed this patch, it will end up in the following
compilation error:
"invalid --param name 'asan-use-shadow-offset-callback'"
So, you cannot accidentally enable the feature without having your
compiler patched.

Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-17 09:03:19 +00:00
Mike Banon 367298b2b4 vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable
This fix is required to avoid the division-by-zero error described at
https://mail.coreboot.org/pipermail/coreboot/2014-March/077418.html
while trying to run the DDR3 memory at 1866 MT/s (933 MHz).

With this fix in place, ASUS A88XM-E boots fine with RAM at 1866 MT/s.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I8e7d00e362879b1247ecf2ab828936268bf9075f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:14:03 +00:00
Mike Banon d5ffa6e1b3 nb/amd/agesa: read 256 bytes to SPD buffer instead of 128
Required for adding the XMP profiles support. SPD buffer is
already 256 bytes at AMD AGESA vendorcode, so this is fine.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I7340b110477a4cc1ecb1c239181436e51952568f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40484
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:13:05 +00:00
Benjamin Doron 2875df1c9e soc/intel/skylake/acpi.c: Name devices on secondary bus
Naming a device allows an ACPI _ROM method to be written for it. GPUs
may require this to make the configuration data contained within
available to an OS driver. This may be required for GPUs that do not
contain their vBIOS, or perhaps the drivers require it in this form/fashion.

Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully
obtains the vBIOS via ACPI (kernel 5.7.11).

Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-17 07:12:46 +00:00
Jes Klinke 6fd87ffe2e soc/intel/tigerlake: Allow fine grained control of S0iX states
Expose devicetree parameter to enable/disable each individual substate.

See https://review.coreboot.org/c/coreboot/+/43741 for context.

TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
BUG=b:154333137

Change-Id: I8a0cf820e20961486813067c6945fe07bc4899f7
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44355
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:11:19 +00:00
Brandon Breitenstein 1df3b70c6a mb/google/volteer: Make devicetree default as Aux Orientation retimer controlled
With new board designs being introduced it does not make sense for the default
devicetree setting to be retimer disabled on port 0 for Aux Orientation.
Change the default to be Aux Orintation retimer controlled on all ports and
move the SOC controlled overrides to the corresponding overridetree files.

BUG=NONE
BRANCH=NONE
TEST=Built image for delbin and verified that port 0 flip is working.

Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2020-08-17 07:11:02 +00:00
Furquan Shaikh ad8cf6209f mb/google/zork: Switch to normal read mode for EM100
This change sets the EFS config for SPI read mode to normal read mode
when using em100. With this, the boot is stable again without any
random hangs in PSP.

BUG=b:164429022

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4cd3673dcc44a61905719a57f734df2fb9f4e6e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-17 07:09:53 +00:00
Pandya, Varshit B b6feee0c74 mb/intel/jasperlake_rvp: Configure GPIOs related to UFC
This change configures user facing camera related GPIOs
as per schematics.
1. GPP_D5 pwr_en
2. GPP_B14 reset
3. GPP_E0 clock
4. GPP_D12 I2C4b
5. GPP_D13 I2C4b

Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: I026c16f73cf597614efaea3e0f0ab1e2cfe1e211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44416
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:09:27 +00:00
Elyes HAOUAS 30201d4ab3 Makefile.inc: Remove redundant warning flag
'-Wstrict-aliasing' is turned on by '-Wall'.
'-Wstrict-aliasing' is only active when -fstrict-aliasing is active, so add it.

'BUILD_TIMELESS=1' on gigabyte/ga-945gcm-s2l  gives the same binary.

Change-Id: I51eb8241389f13d2659aef0a3b4b376ce9c651cf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44216
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:08:31 +00:00
Elyes HAOUAS d592909014 crossgcc: Upgrade IASL to version 20200717
Summary of changes: https://acpica.org/node/183

Change-Id: Ib325fa5c37c32702c572ab56c99e1f8f785cbe53
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-17 07:07:33 +00:00
Elyes HAOUAS 384e2c9218 crossgcc: Upgrade Python to version 3.8.5
Change-Id: I660994ece28f04d97de2fe3a074ebcf93fb4d2f4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:05:56 +00:00
Elyes HAOUAS 2574590f8c crossgcc: Upgrade nasm to version 2.15.03
Change-Id: I4b38595cef72053f82216df43f3667abed4c1989
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42855
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:05:36 +00:00
Elyes HAOUAS a15a7a5c13 crossgcc: Upgrade binutils to version 2.35
Using "MAKEINFO = @MAKEINFO@", it fails to compile, so
binutils-2.35_no-makeinfo.patch will change that to "MAKEINFO = true"

Change-Id: I0ad01e5da34c96fee6a9b1a63897a9fb28471c75
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38666
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:05:11 +00:00
Elyes HAOUAS 150c438334 crossgcc: Update MPFR to version 4.1.0
Changes: https://www.mpfr.org/mpfr-current/#changes

Change-Id: I1df2c952229056b44d4c618cebe774ea27b55bd1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43360
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:04:14 +00:00
Elyes HAOUAS e541268b0a crossgcc: Upgrade GMP to v6.2.0
gmp_freebsd-configure.patch is integrated in upstream so we don't need
it anymore.
Changes: https://gmplib.org/gmp6.2

Change-Id: I8404872f1b65e9173c1fcbd24d7da7bdd7937503
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38465
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:03:11 +00:00
Elyes HAOUAS a4dd33cc8b src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers
Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44371
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 07:00:37 +00:00
Elyes HAOUAS a3022056a2 {soc/intel/common,sb/intel/lynxpoint}/hda_verb.c: Reduce differences
Change-Id: Ie63d7671eb19f0d4c4f67dfe242193e7949afdea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17 06:59:24 +00:00
Elyes HAOUAS 6ea24ffa8f {sb/intel/*/azalia.c,device/azalia_device.c}: Reduce differences
Remaining notable differences at function 'codec_detect(u8 *base)'.

Change-Id: Ia64e0ba10f145cf2eae0cb2ff4951b1455963d5d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-08-17 06:58:45 +00:00
Elyes HAOUAS 59236d526a sb/intel/ibexpeak: Use <device/azalia_device.h> registers
Change-Id: Ic257a11ec2a2f8b1809ed40ae0f9468574dfd009
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44131
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:46:25 +00:00
Elyes HAOUAS 388c88b72c sb/intel/i82801jx: Use <device/azalia_device.h> registers
Change-Id: Ic661a1339892dad668ad3f9e68cab70bf380505f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44130
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:46:08 +00:00
Elyes HAOUAS e5954bad5b sb/intel/i82801ix: Use <device/azalia_device.h> registers
Change-Id: Id6c2c7b474ad8f57294bae67c33b2dd26a6a95ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44129
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:45:54 +00:00
Elyes HAOUAS f1da909dd4 sb/intel/i82801gx: Use <device/azalia_device.h> registers
Change-Id: I1a5b0b9db0cc3847693934de20b5d27605617637
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44128
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:45:39 +00:00
Elyes HAOUAS 11178bd305 sb/intel/bd82x6x: Use <device/azalia_device.h> registers
Change-Id: I1e30dd7b300d7975e7a89fbe1e66aaf7affd1702
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44127
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:45:11 +00:00
Elyes HAOUAS eaf2ae764e sb/intel/lynxpoint: Use <device/azalia_device.h> registers
Change-Id: Ib4929e3213676056ff3f8116d226fd38132baa28
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44126
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:44:47 +00:00
Elyes HAOUAS d8c4799b89 device/azalia_device.c: Use <device/azalia_device.h> registers
Change-Id: Ia0ba6c2f76221123acd3c5303b0a018c651f3617
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44125
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:44:27 +00:00
Elyes HAOUAS 899d5bdefa soc/intel/common: Move common HDA registers to <device/azalia_device.h>
Change-Id: I9ea191e5076e2f055405dc34d46dbbb8cfb0015e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44106
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:44:04 +00:00
Ren Kuo 9a9d10f7f5 mb/google/dedede/var/magolor: Generate SPD ID for supported parts
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR

And also remove the deprecated by cl#43989
https://review.coreboot.org/c/coreboot/+/43989

BUG=None
TEST=Build the magolor board

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I3348b7fbeff038b85e7d3c9137517e05a35bf3dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44408
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:42:40 +00:00
Anil Kumar f4fa906270 mb/tglrvp: Update SPD files for Hynix
- Increase DDR Frquency limit to support data rate 4266 Mbps

Bug=None
Test=Build and boot on tglrvp hardware;
     $dmidecode --type 17 reflects memory Speed = 4266

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I8185ebbaa32a01fee104bc0b757fc4adb58bba97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44149
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:41:10 +00:00
Reto Buerki 5b40682313 mb/up/squared: Increase MAX_CPUS from 2 to 4
The board also supports Atom processors, which have four physical cores.

Signed-off-by: Reto Buerki <reet@codelabs.ch>
Change-Id: I98a3da660052eb7ad2f18b0c7fc0e67a609eac54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-08-17 06:40:34 +00:00
Kevin Chiu bed0965442 mb/google/zork: adjust i2c2 data hold time for TP
current setting got 0.278us which is less than the min 0.3us.
increase i2c2 data hold time for TP.

BUG=b:163613330
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. data hold time measured by scope: 0.3805us

Change-Id: I2d564983383c17ed43cc5cc5aaff0fcd67ce6928
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-17 06:39:38 +00:00
Caveh Jalali eb9337c9cc mb/google/volteer: Define stop_gpio for goodix touch screen
This applies to the goodix touch screen on both the volteer and
volteer2 variants: Define GPP_E3 as the stop_gpio for the touch screen
"Report_Switch" signal. Goodix defines a 1ms (minimum) delay after
stop off. In addition, no longer drive this GPIO high by default as it
is now controlled by the kernel through ACPI.

BUG=b:153705232
TEST=touch screen still functional on volteer; confirmed timings with
	scope (VDD, RESET, REPORT_SWITCH)

Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-17 06:39:23 +00:00
Elyes HAOUAS ac66bda47c payloads/seabios: Update stable version to 1.14.0
see https://seabios.org/Releases

Change-Id: I20e57314b867581f41921178ff1ffcbaa50a0843
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2020-08-17 06:37:57 +00:00
Karthikeyan Ramasubramanian 8beb5ba230 mb/intel/jasperlake_rvp: Re-organize the FMAP layout
More space is required in the COREBOOT CBFS to accommodate some features.
Currently no alternate firmware is stuffed into RW_LEGACY CBFS and has
~1 MB of unused space. Borrow some space from RW_LEGACY CBFS and extend
the RO_SECTION. Even within RO_SECTION, GBB requires only 12 KiB. So
adjust the GBB region accordingly and extend the COREBOOT CBFS.

BUG=b:162159386
TEST=Build the JSLRVP mainboard.

Change-Id: Ia8bb381c31ddf76f3211f9d4ac5c8c18c27834b7
Signed-off-by: Karthikeyan Ramasubramanain <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-08-17 06:37:26 +00:00
Elyes HAOUAS 2a66dd2cc2 sb/intel/lynxpoint/smihandler.c: Remove dead assignment
Also remove unused 'data'.

Change-Id: Icaae8a986cd375e2b67f05883688847e1a174082
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44288
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:29:14 +00:00
Elyes HAOUAS 83b6283e61 drivers/intel/fsp2_0/hand_off_block: Remove dead decrement
Value stored to 'size' is never read.
Also drop unused parameter.

Change-Id: If3e96ac90f06966ee408964e0748730bc237ec19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17 06:26:29 +00:00
Iru Cai 2a59db7573 mb/hp: select TPM and TPM1 for all EliteBook laptops
All the Sandy/Ivy Bridge EliteBook and ProBook laptops currently
supported by coreboot and on review all support TPM 1.2 according the
maintenance and service guide manuals of these laptops. So select the
Kconfig options of TPM and TPM 1.2 and add the entry of it to the
common device tree.

The device tree C source files of 8460p generated by sconfig before
and after this change are compared. All the device nodes still exist
with nodes under LPC having different device number.

Tested with 2560p, which still works without problems, and the TPM can
be detected and used in the system.

Change-Id: Ic6158d3346a55e3d09c0a4ced9fd141b9a6c4256
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17 06:25:42 +00:00
Iru Cai 1bda1c356a mainboard: Add HP EliteBook 2560p
Most of the code is generated by autoport. The laptop works well under
coreboot with SeaBIOS 1.13.0 payload, running Arch Linux with kernel
5.4.39 and 5.6.11.

Change-Id: I126916e201fb8e4b9067f2dececebfb5bae6df73
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17 06:25:19 +00:00
Arthur Heymans 89f182ae12 cpu/Makefile.inc: Clean up non-existing directory inclusion
The Allwinner code has been removed from the master branch for quite
some time now.

Change-Id: I9e5fd267140c180ae145d12b325cc489725f9ad0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44316
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17 06:24:23 +00:00
Arthur Heymans 54a4f172d8 lib/imd_cbmem.c: Add a helper function to indicate that cbmem is ready
This can be used in romstage in particular to know if dram is ready.

Change-Id: I0231ab9c0b78a69faa762e0a97378bf0b50eebaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17 06:22:58 +00:00
Arthur Heymans a6a2f9372c arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dram
INVD is called below so if postcar is running in a cached environment
it needs to happen.

NOTE: postcar cannot execute in a cached environment if clflush is not
supported!

Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17 06:22:41 +00:00