Commit Graph

30646 Commits

Author SHA1 Message Date
Nico Huber 5936ba43f3 drivers/i2c/at24rf08c: Add proper Kconfig option
The existing Kconfig code made SMBIOS_PROVIDED_BY_MOBO depend
on VENDOR_LENOVO. Thus, it couldn't be selected by boards from
other vendors. So we add another Kconfig that selects it
here.

NB. It's still unclear how the two drivers in this directory
are related (at24rf08c and lenovo_serial). From the code, it
doesn't look like the latter belongs here.

Change-Id: Iaa5c5a584f2a5e2426352ec6aa681f99a55efa49
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30 11:50:42 +00:00
Nico Huber 9734af6697 device/i2c_bus: Add i2c_dev_read_at16()
i2c_dev_read_at16() sends a 16-bit offset to the I2C chip (for larger
EEPROM parts), then reads bytes up to a given length into a buffer.

Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30 11:50:16 +00:00
Maxim Polyakov 9529530766 pci_ids: fix PCI ID for Intel Iris HALO GT4 iGPU
According to the documentation [1], SKL-H Halo GT4E (Iris Pro Graphics
P580) PCI ID should be 0x193B.

[1] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM)
    Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference
    Manual. Volume 4: Configurations. May 2016, Revision 1.0
    Doc Ref # IHD-OS-SKL-Vol 4-05.16

Change-Id: Id62fe3ec26779d51b748efd271db565ade1e3ee0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-30 11:49:07 +00:00
Maxim Polyakov dde937cce3 pci_ids: rename PCI_DEVICE_ID_INTEL_SKL_ID_H
The new macro name contains the number of cores:
PCI_DEVICE_ID_INTEL_SKL_ID_H_4 - 4 core
PCI_DEVICE_ID_INTEL_SKL_ID_H_2 - 2 core

Change-Id: I190181b213d55865aa577ae5baff179fef95afde
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35302
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30 11:48:50 +00:00
Paul Fagerburg 4ab023329d util/mb/google/hatch: update CRC calculation for correctness
The CRC result is treated as a signed value, and so in certain
situations, the calculated value for the last four digits will not
be correct. Ensure that the CRC is treated as an unsigned 32-bit
value prior to converting the last 4 decimal digits to a string.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I92f9ce1ceb7450f90b89c94e0ace6f79a9419b42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35604
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30 11:43:28 +00:00
Paul Fagerburg 39f3f52b3e util/mb/google/hatch: script can take optional bug parameter
When creating a new variant, adding a bug parameter after the name
of the variant will populate the BUG= field in the commit message.
If the parameter is not present, then BUG=None.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I3e08df5d80a5684c9f3675e3c0a8346240171cd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-30 11:42:17 +00:00
Paul Fagerburg cad708d210 util/mb/google/hatch: fix style issues in shell script
* Use all caps for variables.
* Use a single exit code for failures.
* No need to popd before exiting the script.
* Do ${var,,} and ${var^^} into variables instead of using it everywhere.
* Add more punctuation in comments.
* Specify LC_ALL=C so that upper/lower case show the desired behavior.

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I63aa0aa633f36b9543e809fc42fac955da5960a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-30 11:42:01 +00:00
Dawei Chien 2422f8c21e mediatek/mt8183: Init SPM driver
To support mt8183 power saving during suspend to RAM, this patch loads
SPM firmware to support SPM suspend. SPM needs its own firmware to do
these power saving in the right timing under correct conditions. After
linux PM suspends, SPM is able to turn off power for the last CPU and do
more power saving for the SoC such as DRAM self-refresh mode and turning
off 26M crystal.

BUG=none
BRANCH=none
TEST=suspend/resume passes for LPDDR4 3200

Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-30 11:38:42 +00:00
Patrick Rudolph 45ffee8346 soc/intel/skylake: Fix ACPI exception AE_NOT_FOUND
Make sure to match devices on the root bus only. This fixes an issue
where the SoC returned "MCHC" as ACPI name for devices behind bridge
devices, as the DEVFN matched.

Fixes observed "ACPI exception: AE_NOT_FOUND" in dmesg, as the ACPI
path no longer contains invalid names.

Tested on Supermicro X11SSH-TF.

Change-Id: I6eca37a1792287502a46a90144f2f0d8e12ae5d4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30 11:38:08 +00:00
Michael Niewöhner 6ba9b5a86f mb/supermicro/x11-lga1151-series: x11ssh-tf: remove unneeded ACPI ifdef
This removes the "ifdef ACPI" which is not needed here as we currently
don't include gpio.h in any asl file.

Change-Id: I803bbee5933eda9423a9bc9fcaea9e905e3ac78e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35543
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30 11:35:00 +00:00
Michael Niewöhner cc0dd5f8a2 mb/supermicro/x11-lga1151-series: fix cmos layout and add default config
This fixes the warning that power_on_after_fail could not be found,
adds a default config and adds the parameter hyper_threading.

Change-Id: I10b0aa71fa7916b01e93e16cbd81e427fd14f6a4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35526
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30 11:34:25 +00:00
Hung-Te Lin 4b5d17ebb3 mb: remove test-only HWIDs
The CONFIG_GBB_HWID can be generated automatically now so we can remove
the test-only HWIDs set in board config files.

BUG=b:140067412
TEST=Built few boards (kukui, cheza, octopus) and checked HWID:
     futility gbb -g coreboot.rom

Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30 11:33:35 +00:00
Hung-Te Lin 117453e890 vboot: create board-specific test-only GBB HWID if not set
The HWID in vboot GBB is an identifier for machine model. On Chrome OS,
that should be provisioned in manufacturing process (by collecting real
hardware information), and will be checked in system startup.

For bring up developers, they usually prefer to generate a test-only
string for HWID. However that format was not well documented and cause
problems. Further more, most Chromebooks are using HWID v3+ today while
the test-only HWID is usually v2. Non-Chrome OS developers may also
prefer their own format.

To simplify development process, the GBB_CONFIG now defaults to empty
string, and will be replaced by a board-specific test-only v2 HWID
automatically. Developers can still override that in mainboard Kconfig
if they prefer v3 or other arbitrary format.

BUG=b:140067412
TEST=Built 'kukui' successfully. Removed kukui GBB config and built
     again, still seeing correct test HWID.

Change-Id: I0cda17a374641589291ec8dfb1d66c553f7cbf35
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-30 11:33:20 +00:00
Hung-Te Lin 544bc2693a util/chromeos: revise description for more utility scripts in future
The description.md and README.md was explicitly made for downloading or
extracting some resources, but we need to add more Chrome OS related
scripts soon; so the description should be revised.

Also changed README.md for better markdown style, for example
 - Use #, ## to replace the old '-' headers
 - Use code format for file names
 - Use code block for example of shell execution

Change-Id: Icc3677fa318b03f4aee1b0f5fb13b2095f2afe64
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-30 11:09:22 +00:00
Kyösti Mälkki e088721f71 device,drivers/: Drop some __SIMPLE_DEVICE__ use
The simple PCI config accessors are always available
under names pci_s_[read|write]_configX.

Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-30 11:07:46 +00:00
Kyösti Mälkki 1463a2a04d getac/p470: Drop unused PCI secondary bus reset
Change-Id: I959cdc08d43fea28f8bbc649cd46bab5656d6ca8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-30 11:06:12 +00:00
Kyösti Mälkki 92bb8320d6 console: Declare empty printk() for __ROMCC__
The typical do { } while (0) did not work, so
provide empty stub function instead.

Change-Id: Ieb0c33b082b4c4453d29d917f46561c0e672d09a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30 08:40:58 +00:00
Kyösti Mälkki 01b60633a8 soc/intel/fsp_baytrail: Drop some __BOOTBLOCK__ guards
Change in ssus_disable_internal_pull() is for romcc
compatibility.

Change-Id: Ib72a669a3b5cd90e74d917f74f35453a85941658
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-30 08:31:33 +00:00
Werner Zeh 3356305ca6 mb/siemens/mc_bdx1: Enable VBOOT
Enable VBOOT in Kconfig and provide a flashmap that includes all the
needed sections for VBOOT support.

Change-Id: Iee12a5d1781c869b20bc14a52ecbf23474caa3fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-30 05:11:06 +00:00
Werner Zeh f553ae4bf3 fsp_broadwell_de: Enable early write access to the SPI flash
If VBOOT is used on a mainboard based on fsp_broadwell_de then VBOOT
needs to be able to write to its NV data which may be stored on the SPI
flash. Enable write access to the SPI flash on SoC level. If the
mainboard does not use VBOOT the linker will drop the extra code. The
benefit is that this code is at least compiled and therefore build
tested with fsp_broadwell_de.

Change-Id: I90a2d30f5749c75df2b286dce6779f10dde62632
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-30 05:10:55 +00:00
Bora Guvendik 6aeed16422 mb/google/drallion: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cometlake pch EDS vol1 section 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.

BUG=N/A
TEST=Hook up XDP on drallion platform, able to boot up into OS and stay
at power up state.

Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-09-30 04:51:31 +00:00
Aamir Bohra b09d44ef2d mb/google/drallion: De-assert WWAN reset signal
BUG=b:141734594

Change-Id: I419f7d11dffebe6c44eefa05750834d07d19857b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-30 04:31:10 +00:00
Kyösti Mälkki 23d4d9f368 amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE
Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29 03:39:33 +00:00
Kyösti Mälkki 0f639750a1 device/pnp_ops: Add ENV_PNP_SIMPLE_DEVICE
Source files including this may have locally defined
__SIMPLE_DEVICE__ so this cannot be placed in <rules.h>.

Change-Id: I2336111b871203f1628c3c47027d4052c37899dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35653
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29 03:39:20 +00:00
Kyösti Mälkki 9d5af5b0c2 device/pci_ops: Add ENV_PCI_SIMPLE_DEVICE
Source files including this may have locally defined
__SIMPLE_DEVICE__ so this cannot be placed in <rules.h>.

Change-Id: If700dd10fd5e082568cd6866bfd802fc2e021806
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35652
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29 03:39:06 +00:00
Kyösti Mälkki 91f2f03759 intel/fsp_baytrail: Drop unnecessary lookup for PCI 0:0.0
It is safe to assume this to be copy-paste from eg. i945
where registers of said PCI device were read.

Change-Id: I387b7fd6caf317543a6438f973d9e1d96e418de3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35668
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29 03:38:41 +00:00
Kyösti Mälkki 32d47eb688 soc/intel: Rename <intelblocks/chip.h>
The filename chip.h has a special purpose with the generation
of static devicetree, where the configuration structure name matches
the path to the chip.h file. For example, soc/intel/skylake/chip.h
defines struct soc_intel_skylake_config.

The renamed file did not follow this convention and the structure it
defines would conflict with one defined soc/intel/common/chip.h if such
is ever added.

Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-29 03:38:13 +00:00
Kyösti Mälkki 44da9e201c cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ use
Change-Id: I62d7450c8e83eec7bf4ad5d0709269a132fd0499
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:18:03 +00:00
Kyösti Mälkki f2cc3dd8ea usbdebug: Remove some __SIMPLE_DEVICE__ use
We can always PCI config accessors with pci_devfn_t.

Change-Id: I6d98c2441cc870cdcadbe8fabc9f35b9ffc652d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:17:33 +00:00
Kyösti Mälkki 8f5138d8a5 drivers/net/ne2k: Remove some __SIMPLE_DEVICE__ use
Note that the code assumes mainboard code to configure
any PCI bridges prior to calling console_init().

Change-Id: I0312d359f153c02e4afcf1c09d79f9eb3019a8b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:16:40 +00:00
Kyösti Mälkki a67eaec0d0 arch/arm,mips: Use generic PCI MMCONF
We need the stub header file. If PCI was implemented, assume
generic MMIO mapped configuration space would work here.

Change-Id: Ia731e5c5a6725fe22ab8b0398cafa1127ed90891
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:16:23 +00:00
Kyösti Mälkki f485d91141 nb/via/vx900: Remove some __SIMPLE_DEVICE__ use
Change-Id: I840131f91e79c740c0c8784c252723ae90ded458
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:16:02 +00:00
Kyösti Mälkki 13ad740701 device/pci: Replace some __SIMPLE_DEVICE__ use
Change-Id: Ide9df46b5ff47fea54b9de0e365638a6223c8267
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:15:47 +00:00
Kyösti Mälkki d7205bebd5 nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ use
Change-Id: Ie3f3c043daa6ec18ed14929668e5acae172177b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28 21:15:27 +00:00
Kyösti Mälkki 197a3c6cea nb/intel/x4x: Avoid x4x.h header with romcc-bootblock
Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-28 21:15:02 +00:00
Alexander Couzens 3b8deeefa5 superiotool: add basic support for SCH5545
Based on the SCH5627 datasheet which is similiar
SCH5545 id 0xc4, SCH5627 id 0xc6.

Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20237
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28 18:39:10 +00:00
Aamir Bohra f3c485e21f mb/google/variants/drallion: Update the spd index map
BUG=b:141575294

Change-Id: I1b2b4362b84b170bd73b760828ca300ec86c4534
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-28 13:24:22 +00:00
Aamir Bohra 78d6ce45d4 mb/google/drallion: Set UART for console to UART controller 0
Drallion uses UART 0 for console, change the config accordindly.

BUG=b:139095062

Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28 13:22:07 +00:00
Arthur Heymans 965881b7ce Kconfig: Hide CONFIG_CBFS_SIZE when an FMDFILE is provided
CONFIG_CBFS_SIZE should only be used as a parameter to generate the
default FMAP.

This also swaps around FMDFILE and CBFS_SIZE to avoid that the
CBFS_SIZE entry disappears when filling in the FMDFILE entry below it.

One advantage is that if code references CONFIG_CBFS_SIZE the jenkins
buildtest will most likely fail as many boards provide an FMD file.

Change-Id: Ic7926e1638d7fb49ba61af28d682315786c3c39e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-28 12:14:12 +00:00
James Ye ef2e86edeb mb/lenovo/x131e: enable mSATA slot
Per google/stout.

Tested with SanDisk SSD U110.

Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2019-09-28 10:46:24 +00:00
James Ye 59de112995 mb/lenovo/x131e: correct USB port config
Based on schematic and register dumps.

Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-27 22:27:45 +00:00
Furquan Shaikh b33a2b05af fmap: Add get_fmap_flash_offset()
CB:35377 changed the behavior of find_fmap_directory() to return
pointer to CBMEM_ID_FMAP if fmap is cached in
cbmem. lb_boot_media_params() calls find_fmap_directory to add offset
of fmap in flash to coreboot table. However, because of the change in
behavior of find_fmap_directory(), it ended up adding 0 as the offset.

This change adds a new function get_fmap_flash_offset() which returns
the offset of fmap in flash. Ideally, all payloads should move to
using the FMAP from CBMEM. However, in order to maintain compatibility
with payloads which are not updated, ensure that fmap_offset is
updated correctly.

Since find_fmap_directory() is no longer used outside fmap.c, this
change also removes it from fmap.h and limits scope to fmap.c.

In a follow up patch, we need to push a change to libpayload to expose
the fmap cache pointer to lib_sysinfo.

BUG=b:141723751

Change-Id: I7ff6e8199143d1a992a83d7de1e3b44813b733f4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-27 21:59:44 +00:00
Aaron Durbin 55ef0d25d3 device: add commentary to dev_find_slot()
dev_find_slot() can sometimes fail to return the desired device object
prior to full PCI enumeration. Comment the declaration and
implementation accordingly to help the user understand the problem and
avoid its usage.

Change-Id: I3fe1f24ff015d3e4f272323947f057e4c910186c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35632
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27 21:08:24 +00:00
Michael Niewöhner 9965553011 mb/supermicro/x11-lga1151-series: remove unneeded vendor id config
The vendor id option set here is useless as most SSVID registers get
filled with 0x8086 (their VID) by default, anyway.

Besides that the Kconfig option isn't meant for retrofit ports, cf.
commit 7e1c83e31b (Add Kconfig options to override Subsystem Vendor and
Device ID). The right place would be the devicetree.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: If67c679bb342f63096902535734106e4f1651118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-27 16:22:08 +00:00
Patrick Rudolph 0c9d8a4ef5 configs: Build test CONFIG_BOOTSPLASH
Change-Id: I306d107720d51c2b378f739f68c31b8642f7354a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35615
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27 16:20:16 +00:00
Patrick Rudolph 5ebe431087 lib/bootsplash: Fix compilation
Add missing include.
Tested on Supermicro X11SSH-TF.

Change-Id: Id0c80ac646001a497e96cae4d48a0f09762eb936
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35613
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27 16:20:04 +00:00
Kyösti Mälkki 9e77d4d037 arch/: Replace __BOOTBLOCK__ with ENV_BOOTBLOCK
Change-Id: I294a3fd7be57b505cd209f7c2718a05770786c51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-26 17:27:45 +00:00
Himanshu Sahdev d1e18d9a44 coreboot/Makefile: display error when spaces in path of toplevel makefile
coreboot toplevel makefile breaks when path to the coreboot directory
contains spaces.
This patch displays a reasonable message to the user whenever spaces
are found within the path to the coreboot direcrory.

This commit addresses coreboot ticket #179.

Change-Id: Id11deffa01ddca1ff9332d67c7aa33a382b4cdc7
Signed-off-by: Sourabh Kashyap <sourabhka@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35434
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26 10:11:14 +00:00
Richard Spiegel 7ae4a268eb soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id code
All solid state devices have vendor id defined by JEDEC specification JEP106,
which originally allocated only 7 bits for it plus parity. When number of
vendors exploded beyond 126, a banking proposition came maintaining
compatibility with older vendors while allowing for 4 extra bits (16 banks)
through the introduction of the concept "Continuation code", denoted by the
byte value of 0x7f.
Examples:
0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o
0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2

BUG=b:141535133
TEST=Build and boot grunt.

Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-26 09:33:00 +00:00
Andrey Petrov 6aea9f9923 soc/intel/fsp_broadwell_de: move get_busno1() into vtd.c
TEST=just build it

Change-Id: I34aee507b8c322c816f92cfcae177c069c749ed7
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-26 09:30:24 +00:00