Commit Graph

30646 Commits

Author SHA1 Message Date
Michael Niewöhner 0a6c62fbbe mb/supermicro: restructure x11ssh-tf to represent a x11 board series
Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.

There are about 20 boards that can be added, if there is a community for
testing.

To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.

It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").

The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.

X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.

Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.

Documentation is reworked in CB:35547

Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26 09:29:25 +00:00
Peichao Wang b68ebfa8fc mb/mainboard/hatch: support elan touchpad for Akemi
Modify IRQ pin from D21 to A21 and support wake-up from touchpad

BUG=b:141519690
TEST=build bios and verify elan touchpad works fine

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35551
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26 06:02:49 +00:00
Peichao Wang c7d2235899 google/grunt: add new two DDR source for Treeya
new DDR particle:
1. Samung K4A8G165WC-BCWE
2. Hynix H5AN8G6NCJR-XNC

BUG=b:139085024
BRANCH=master
TEST=rework new source to DUT and re-flash bios to DUT and
verify DUT will bring up successfully

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-26 05:46:41 +00:00
Kyösti Mälkki 89c0ef7395 cpu/intel/: Clean up microcode update from __PRE_RAM__
Change-Id: Ib12985dd9a12495533a82be556405f975a0abe27
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-26 01:16:54 +00:00
Kyösti Mälkki 3de8f8c137 cpu/amd/pi/00730F01: Clean up microcode update from __PRE_RAM__
It is only called in ramstage. Even if it was called in
romstage, execution flow is such that BSP and AP CPUs
should not be able to enter update_microcode() routine
concurrently.

Also the Kconfig guarding the spin_lock() calls are not
selected nor are the lock variables declared for these
platforms.

Change-Id: I1c2e106f10e8420e942b3ed082c677c0db95557c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35586
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26 01:16:44 +00:00
Edward O'Callaghan da33246bc5 util/mainboard/google: Fix hatch variant script
The script had a couple of bugs:
 * It didn't create the required directory under variants/
 * It was treating the wildcard as literal and so couldn't
   find variant files to copy.

V.2: Drop verbose cp && fixup wild card usage.

Change-Id: Ie6f4179014b79ea45d0fcf406ca192046438dbf7
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-09-25 13:31:03 +00:00
Matt DeVillier 4721e47064 soc/fsp_broadwell_de: fix flashconsole support for platform
CB:29633 switched platform to use sb/common spi implementation,
which worked until CAR_GLOBAL was removed in CB:30506.

Revert the changes back to usage of CAR_GLOBAL in the common spi
driver so that flashconsole will work again in romsatge for
fsp_broadwell_de.

Test: verify flashconsole functional on out-of-tree Broadwell-DE board

Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-25 12:56:56 +00:00
Hung-Te Lin 266c58a20b mb/google/kukui: Add new build target 'Juniper'
Add the configuration 'Juniper' for the new mainboard.

BUG=b:137517228
TEST=make menuconfig; select 'juniper' and build

Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-25 12:56:26 +00:00
Furquan Shaikh d1a4a7a7fa util/mb/google/hatch: Update kconfig.py to not select SOC_INTEL_COMETLAKE
Now that SOC_INTEL_COMETLAKE is selected by default in Kconfig,
utility to create a new variant does not need to do that anymore in
Kconfig.name

Change-Id: If68bcf14e2e0812d4f4dcb99371c65790154ff62
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-25 12:56:13 +00:00
Furquan Shaikh d6d416cc96 mb/google/hatch: Move SOC_INTEL_COMETLAKE selection to Kconfig
All variants of hatch are using Comet Lake and so the selection can be
done in Kconfig without requiring each variant to do the same.

Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-25 12:56:00 +00:00
Frans Hendriks ee8ca86dd6 Documentation/vendorcode: Add Eltan to vendor index
Eltan is missing in the vendor index.

Documentation of the eltan vendorcode is availlabe already.
Add eltan to vendor index.

BUG=N/A
TEST=N/A

Change-Id: I51fe64da91499f0ea7bf97fc240f4e263470c146
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-25 12:53:07 +00:00
Werner Zeh f57b05b573 mb/siemens/mc_apl1: Sort the names of all variant mainboards
Sort the names of all variant mainboards in an ascending order.

Change-Id: I19d502298744c0e0cbc91eb836c62ca90cdb9a5c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-25 08:14:56 +00:00
Werner Zeh 255748ea5d mb/siemens/mc_apl{2,4,5}: Enable VBOOT
Enable VBOOT in Kconfig and provide a flashmap that includes all the
needed sections for VBOOT support.

Change-Id: I3d58094256d2730dbd249291a8f1ed8df9dfe62d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-25 08:14:46 +00:00
Sridhar Siricilla f35eee94bd soc/intel/(apl,skl,cnl,common): Move mkhi_hdr structure definition to common
Removed mkhi_hdr structure definition from multiple SOCs, and moved to common.

TEST=Built code for Hatch, apollolake boards.

Change-Id: Ifeba0ed4d98975049179d1b47fb22c06a927dc29
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35545
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-25 06:26:14 +00:00
Kyösti Mälkki e39becf521 intel/cpu: Switch older models to TSC_MONOTONIC_TIMER
The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.

Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24 22:56:52 +00:00
Kyösti Mälkki c00e2fb996 cpu/intel: Use CPU_INTEL_COMMON_TIMEBASE
Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-24 22:56:16 +00:00
Kyösti Mälkki 52b1e2814a intel/socket_mPGA604: Enable TSC_CONSTANT_RATE
We can use intel/common implementation for tsc_freq_mhz().

Change-Id: I728732896ad61465fcf0f5b25a6bafd23bca235e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34199
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24 19:03:57 +00:00
Kyösti Mälkki fe26be1181 cpu/intel/common: Fix invalid MSR access
Fix regression from commit ecea916

   cpu/intel/common: Extend FSB detection to cover TSC

MSR_EBC_FREQUENCY_ID (0x2c) was not defined for affected
CPU models and rdmsr() caused reset loops. Implementations
deviate from public documentation.

Change to IA32_PERF_STATUS (0x198) already used in i945/udelay.c
to detect FSB to TSC multiplier.

Change-Id: I7a91da221920a7e7bfccb98d76115b5c89e3b52e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-24 19:03:10 +00:00
Alexander Couzens be756f18df Makefile: set TZ LANG LC_ALL
To be reproducible, TZ LANG LC_ALL should be set early
in the build process to be always used.

Change-Id: Iad802968347c8d41f974af930e0d0ad5b66719cb
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-09-24 10:37:06 +00:00
Martin Roth ad84062b0d Makefile: Create the build directory before bootblock.bin
This was causing a failure when building platforms with no bootblock
when building with make -jXX

Change-Id: Ic4cd4fe8ac82bd1e9ce114dbd53763538d125af3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-09-24 10:36:24 +00:00
Johanna Schander 431d0083a8 Add Razer Blade Stealth (2016) H2U
The Razer Blade Stealth H2U is a KabyLake System using:
- Intel KBL 7500U
- ITE8528E SuperIO
- Intel 600P Series NVMe SSD
- Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB)
  of soldered memory in dualchannel mode
- (Optional) Touchscreen
- HDMI 2.0a via DP-1: Paradetech PS175
- AlpineRidge Thunderbolt 3 controller
- TPS65982 USB-PD power switch / multiplexer

Even though it has a 16MB chip equipped (W25Q128.V) only the first 8MB
are used and mapped via IFD. The rest is left empty (0xFF). The flash is
not secured in any way and can be read via flashrom. It should be the
source for this port's IFD and ME blobs.

Working:
- USB-A Ports left and right
- Speakers
- Touchscreen (USB)
- Onboard Keyboard in Linux
- NVMe SSD
- SeaBIOS, Tianocore and Grub Payloads
- Webcam
- Powersaving Modes
- Battery state and LID switch, sometimes slow to update.
- Touchpad (I2C-HID)
- Headphones

Not part of this commit:
- Thunderbolt / USB-C (Requires advanced EC signaling)
- Full HDMI support (Currently requires plugged connection at boot)

Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2019-09-24 10:35:31 +00:00
Selma BENSAID b458a4f745 depthcharge: add CONFIG_MAINBOARD_DEPTHCHARGE
CONFIG_MAINBOARD_DEPTHCHARGE is used to override the Board
config for depthcharge which inherit from CONFIG_MAINBOARD_PART_NUMBER.
This is mainly to avoid depthcharge config duplication.

Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: I6cbc93ca38ad6deeca2c2fb7770024a24233b6f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2019-09-24 10:34:42 +00:00
Hung-Te Lin 0962b1fa5d device/mmio.h: Add bit field helpers
When accessing register with multiple bit fields, the common approach is
to use clrsetbits_le32, for example:

  clrsetbits(&reg, (1 << 0) | (0x3 << 1) | (0x7 << 10),
                   (1 << 0) | (0x1 << 1) | (0x5 << 10));

This hard to maintain because we have to calculate the mask values
manually, make sure the duplicated shift (offset) was set correctly.
And it may be even worse if the value to set will be based on some
runtime values (that many developers will do a if-block with two very
similar argument list), and leaving lots of magic numbers.

We want to encourage developers always giving field names, and have a
better way of setting fields. The proposed utility macros are:

 DEFINE_BITFIELD(name, high_bit, low_bit)
 EXTRACT_BITFIELD(value, name)
 WRITE32_BITFIELDS(addr, name, value, [name2, value2, ...])
 READ32_BITFIELD(addr, name)

Where a developer can easily convert from data sheet like

 BITS  NAME
 26:24 SEC_VIO

Into a declaration

 DEFINE_BITFIELD(SEC_VIO, 26, 24)

Then, a simple call can set the field as:

 WRITE32_BITFIELDS(&reg, SEC_VIO, 2);

That is much easier to understand than

 clrsetbits_le32(&reg, 0x7 << 24, 0x2 << 24);

And to extract the value:

 READ32_BITFIELD(&reg, SEC_VIO)

That is equivalent to:

 (read32(&reg) & 0x3) >> 24

Change-Id: I8a1b17142f7a7dc6c441b0b1ee67d60d73ec8cc8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35463
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24 10:32:50 +00:00
Andrey Petrov b5598cee7e mainboard/ocp/monolake: Hide internal NIC
Disable root port IOU0 to which built-in NIC is attached.

TEST=on OCP monolake, hide built-in NIC and make sure OS does not report
built-in NIC

Change-Id: I2384e7dd073355f0ced2902ac2d8418996b1c5aa
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-09-24 10:30:11 +00:00
Andrey Petrov 2fa4938796 soc/fsp_broadwell_de: Add devhide functionality
Add function to hide IIO PCIe root ports.

TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3]
and make sure OS does not detect built-in NIC.

Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-24 10:29:58 +00:00
Himanshu Sahdev 8dc95ddbd4 emulation/qemu-i440fx: use fw_cfg_dma for fw_cfg_read
- configure DMA fw_cfg
- add support to read using fw_cfg_dma
- provide fw config version id info in logs

BUG=N/A
TEST=Build and boot using qemu-i440fx.

Change-Id: I0be5355b124af40aba62c0840790d46ed0fe80a2
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-24 10:29:28 +00:00
Seunghwan Kim df02f7aed8 mb/google/kohaku: Update DPTF parameters and TCC offset setting
This change applies fine-tuned DPTF parameters and TCC offset setting
for kohaku. Also enables EC_ENABLE_MULTIPLE_DPTF_PROFILES for tablet
mode.

BUG=b:137688474
BRANCH=none
TEST=built and verified the setting values

Change-Id: I92e268b2e07ca5a04e29bda84ddb8fc21eb23251
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-24 10:28:42 +00:00
Huayang Duan 9400f84d31 mediatek/mt8183: Use different DRAM frequencies for eMCP DDR
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps)
while those with discrete DRAM can only run at 3200Mbps. This patch
enables 3600Mbps for eMCP DDR for better system performance.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test passes on Kukui

Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-24 10:28:01 +00:00
Kyösti Mälkki 1011ed76a6 vendorcode/cavium: Replace use of __PRE_RAM__
Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-23 21:39:22 +00:00
Kyösti Mälkki 7596c54dba lib/trace: Replace __PRE_RAM__ use
Change-Id: I957be92594aced2e8465e7f94d8d42e44c3418d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35399
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-23 21:38:50 +00:00
Patrick Rudolph bd17f7b877 mb/up/squared: Fill LPDDR4 dimm info
Fill the dimm info struct to make SMBIOS type 17 appear.

TESTED=Up Squared

Change-Id: I4de63362c8fea8a886594cdcf0eec48421afb605
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34564
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-23 08:48:20 +00:00
Patrick Rudolph 6d787c2590 lib/fmap: Cache FMAP in cbmem
For platform independend exposure of FMAP through a kernel module
cache the FMAP in CBMEM. In addition add a pointer in coreboot tables
pointing to the introduced CBMEM area.

To not waste the allocated DRAM, use the cached CBMEM in RAM enabled
stages if possible.

Tested on qemu using
https://github.com/9elements/linux/commits/google_firmware_fmap2

Tested on QEMU and Supermicro X11SSH-TF.

Change-Id: I4e01c573c3edfa34dbba5fe7604d4f6e18b584d5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-23 08:46:13 +00:00
Angel Pons afa6a2de48 mb/gigabyte/ga-h61m-s2pv: Improve LPC decoding
Drop unused CNF2_LPC_EN, as there is no device which uses IO 0x4e/4f.

Do not use the mainboard model to set COMA_LPC_EN. Make use of
NO_UART_ON_SUPERIO instead, as it is more future-proof.

Change-Id: Iac49250b0f509a42012f82db8aa85ba85559c66f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-22 20:14:27 +00:00
Peichao Wang 8eb34dbe57 mb/mainboard/hatch: add spd: 8G_3200 for Akemi
BUG=b:140545732
TEST=build bios and spd index set to 6, verify DUT bring up normally

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I337b0bdcd37a9c4baacccbc6786968031a41b31e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35511
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-22 20:13:29 +00:00
Philipp Deppenwiese 58d668c387 mb/ocp/monolake: Add vboot RO only support
Change-Id: I28a21d64e2781af294670a94c1fc88fb81e80f9e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35492
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-22 20:12:54 +00:00
Wisley Chen 31f5283563 mb/google/hatch: Add G2Touch Touchscreen support
Add G2Touch Touchscreen support for dratini

BUG=b:141281841
TEST=emerge-hatch coreboot chromeos-bootimage, and check touchscreen
work.

Change-Id: I0dbde7f8396da6335b22aeb4a9703336e2b862b8
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-22 20:12:43 +00:00
Philipp Deppenwiese 7f443e1e38 mb/facebook/watson: Enable vboot for measurements
Signed-off-by: Philipp Deppenwiese <philipp.deppenwiese@9elements.com>
Change-Id: I8287d475301aaaae736df9cc95fcd18cc04b40fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
2019-09-22 20:12:26 +00:00
Paul Menzel 3b99d6298e Documentation: Capitalize Super I/O
Change-Id: I6bfe11abc1b3763f3d6c390bbccd9191b417945d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-22 20:11:49 +00:00
Kyösti Mälkki fca9907c49 sb/intel/i82870: Drop unused file
Change-Id: I024805769ad05f995a23669a82f5482ce3e7ae70
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-22 18:39:27 +00:00
Kyösti Mälkki ca7580c064 device/cardbus: Remove unnecessary bridge_ctrl bitmask
The bits PARITY and SERR are set unconditionally below.

Change-Id: I03f53fe7f436f8feed7b34756439077f02a85565
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
2019-09-22 18:39:08 +00:00
Kyösti Mälkki 0bca050f2c device/cardbus: Fix use of PCI_CB_BRIDGE_CONTROL
Read-modify-write needs to access the same register. Numerically
both used defines are 0x3e, while register implementations are
not identical but only similar.

Change-Id: I9348b855320f86868e2d3ef76d3b8d7a4ab7fae0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
2019-09-22 18:38:20 +00:00
Kyösti Mälkki 382e2167cc device/pci: Replace add with bitwise-or
Change-Id: I9fbefac3bef7425d6f5ea1bcc01eb21485315c36
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-22 18:37:57 +00:00
Michael Niewöhner 853c1afac2 mb/supermicro/x11ssh: remove unnecessary fsp setting CdClock
CdClock does not need to be set because the board does not use IGD.

Change-Id: I6835ccdf80530f9efc6fdeb0363dcf9267f99d21
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-22 09:48:33 +00:00
Michael Niewöhner 5a7dc9eb62 soc/intel/skylake: lock down TCO on pch finalize
Change-Id: I5bd95b3580adc0f4cffa667f8979b7cf08925720
Signed-off-by: Michael Niewöhner <michael.niewoehner@8com.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-09-22 04:04:27 +00:00
Andrey Petrov 3dd6867ea9 soc/fsp_broadwell_de: Move function to get CPUBUSNO(1) into common file
Change-Id: I189eb8ffce2f0735ad9ba603b1d96786aa00fafb
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-09-21 20:38:10 +00:00
Andrey Petrov b18946a557 mb/ocp/monolake: Implement bank/locator scheme
Implement Locator and Bank fields (as reported by dmidecode) to match
vendor BIOS.

TEST=on OCP monolake, run dmidecode tool and see that "Locator" field
matches expectation.

Change-Id: Ia271ff1e596ba469cf42e23d8390401c27670a27
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-21 20:36:26 +00:00
Andrey Petrov 91f955e31f soc/fsp_broadwell_de: Use DIMM numbers relative to channel
Currently "DIMM numbers" increase monotonically for all the channels. However,
commonly DIMMS are numerated on per-channel basis. This change makes numeration
match the convention.

TEST=on OCP monolake, run dmidecode tool and see that "Locator" field matches
expectation.

Change-Id: I3e7858545471867a0210e1b9ef646529b8e2a31c
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35318
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-21 20:36:01 +00:00
Richard Spiegel 65562cd654 soc/amd/picasso: Use new common SPI code
Use the new SPI code from common folder, delete spi.c. SPI related macros
must be single defined, in southbridge.h if they are used by files other
than the common SPI code, fch_spi.h if they are only used by the common
SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h,
because it can change between SOC.

BUG=b:136595978
TEST=None, code already tested with grunt.

Change-Id: I68008ce076d348adbdabf7b49cec8783dd7134b4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-21 20:35:03 +00:00
Richard Spiegel bf1712422a soc/amd/stoneyridge: Use new common SPI code
Use the new SPI code from common folder, delete spi.c. SPI related macros
must be single defined, in southbridge.h if they are used by files other
than the common SPI code, fch_spi.h if they are only used by the common
SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h,
because it can change between SOC.

BUG=b:136595978
TEST=Build and boot grunt using new SPI code, with debug enabled. Check
output.

Change-Id: I639973d993316a10daa7564462e689b2c183f536
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-21 20:34:44 +00:00
Richard Spiegel e512bce189 soc/amd/common/block: Create new SPI code
Create a new SPI code that overrides flash operations and uses the SPI
controller within the FCH to its fullest.

Reference: Family 15h models 70h-7Fh BKDG revision 3.06 (public)

BUG=b:136595978
TEST=Build and boot grunt using this code, with debug enabled. Check
output.

Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-21 20:34:27 +00:00