This to fix following error using Clang-16.0.0:
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.backlight_enable = 0x01,
^~~~
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.dock_event_enable = 0x01,
^~~~
Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This to fix following error using Clang-16.0.0:
/cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:66:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.c4onc3_enable = 1,
^
/cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:75:32: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.p_cnt_throttling_supported = 1,
^
Change-Id: I691b51a97b359655c406bff28ee6562636d11015
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This to fix following error using Clang-16.0.0:
CC romstage/mainboard/emulation/qemu-i440fx/static.o
build/mainboard/emulation/qemu-i440fx/static.c:31:17: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.ide0_enable = 1,
^
build/mainboard/emulation/qemu-i440fx/static.c:32:17: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.ide1_enable = 1,
^
Change-Id: I36cc19bc2908119fe940941e108ee217a7b26f50
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This reverts commit 89b4f69746.
SI_BIOS is mostly used to indicate the BIOS region in Intel IFD. Not all
platforms are Intel platforms with an IFD, so revert this change. Also
tooling often depends on names not changing so renaming things should
not be done lightly. The default region should also be in sync with
non-x86 and made systematic across the tree.
Change-Id: I46f52494498295ba5e2a23d0b66b56f266293050
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74290
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Currently coreboot presents the BSP core first, then efficient cores and
Performance cores as indicated below:
```
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3
```
Existing code presents mix of different cores to OS and causes CPU load
balancing and power/performance impact. So, the patch fixes this
disorder by ordering the Performance cores first, compute die efficient
cores next, and finally SOC efficient cores if they are present. This
is done to run the media applications in a power efficient manner,
please refer the ChromeOS patches for details:
https://chromium-review.googlesource.com/c/chromiumos/platform2/+/3963893
BUG=b:262886449
TEST=Verified the code on Rex system
After the fix:
```
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
```
Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.
BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
coreboot supports three instances of sending EOP:
1. At CSE `.final' device operation
2. Early as with Alder Lake in chip_operations.init if
`SOC_INTEL_CSE_SEND_EOP_EARLY' is selected
3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if
`SOC_INTEL_CSE_SEND_EOP_LATE' is selected
Currently, Alder Lake uses #3 as it results in better and more stable
boot time. However, what would deliver even better result is to not
actively wait for CSE completion.
This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig
which split the action of sending EOP request and receiving EOP
completion response from the CSE.
This patch used in conjunction with #1 can significantly
improves the overall boot time on a Raptor Lake design. For example
`SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36
ms boot time improvement as illustrated below.
| # | Late EOP | Async EOP |
|----------+----------+-----------|
| 1 | 1020.052 | 971.272 |
| 2 | 1015.911 | 971.821 |
| 3 | 1038.415 | 1021.841 |
| 4 | 1020.657 | 993.751 |
| 5 | 1065.128 | 1020.951 |
| 6 | 1037.859 | 1023.326 |
| 7 | 1042.010 | 984.412 |
|----------+----------+-----------|
| Mean | 1034.29 | 998.20 |
| Variance | 4.76 % | 5.21 % |
The improvement is not stable but comparing coreboot and FSP
performance timestamps demonstrate that the slowness is caused by a
lower memory frequency (SaGv point) at early boot which is not an
issue addressed by this patch.
We also observe some improvement on an Alder Lake design. For example,
the same configuration on a kano board can deliver up to 10 ms boot time
improvement as illustrated below.
| # | Late EOP | Async EOP |
|----------+----------+-----------|
| 0 | 1067.719 | 1050.106 |
| 1 | 1058.263 | 1056.836 |
| 2 | 1064.091 | 1056.709 |
| 3 | 1068.614 | 1055.042 |
| 4 | 1065.749 | 1056.732 |
| 5 | 1069.838 | 1057.846 |
| 6 | 1066.897 | 1053.548 |
| 7 | 1060.850 | 1051.911 |
|----------+----------+-----------|
| Mean | 1065.25 | 1054.84 |
The improvement is more limited on kano because a longer PCIe
initialization delays EOP in the Late EOP configuration which make it
faster to complete.
CSME team confirms that:
1. End-Of-Post is a blocking command in the sense that BIOS is
requested to wait for the command completion before loading the OS or
second stage bootloader.
2. The BIOS is not required to actively wait for completion of the
command and can perform other operations in the meantime as long as
they do not involve HECI commands.
On Raptor Lake, coreboot does not send any HECI command after
End-Of-Post. FSP-s code review did not reveal any HECI command being
sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or
`END_OF_FIRMWARE' notifications.
If any HECI send and receive command has been sent the extra code
added in `cse_receive_eop()' should catch it.
According to commit 387ec919d9 ("soc/intel/alderlake: Select
SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first
boot after flashing of a Marasov board for instance) request coreboot
to perform a global request out of AFTER_PCI_ENUM notification. Global
request relies on a HECI command. Even though, we tested that it does
not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not
be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent
potential a global reset command to "conflict" with the EOP command.
This patch also introduces a new code logic to detect if CSE is in the
right state to handle the EOP command. Otherwise, it uses the
prescribed method to make the CSE function disable. The typical
scenario is the ChromeOS recovery boot where CSE stays in RO partition
and therefore EOP command should be avoided.
[DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
[INFO ] HECI: coreboot in recovery mode; found CSE in expected
SOFT TEMP DISABLE state, skipping EOP
[INFO ] Disabling Heci using PMC IPC
[WARN ] HECI: CSE device 16.0 is hidden
[WARN ] HECI: CSE device 16.1 is disabled
[WARN ] HECI: CSE device 16.2 is disabled
[WARN ] HECI: CSE device 16.3 is disabled
[WARN ] HECI: CSE device 16.4 is disabled
[WARN ] HECI: CSE device 16.5 is disabled
BUG=b:276339544
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post sent soon after FSP-s and EOP message receive at
`BS_PAYLOAD_BOOT'. Verify robustness by injecting a
`GET_BOOT_STATE' HECI command with or without `heci_reset'. The
implementation always successfully completed the EOP before
moving to the payload. As expected, the boot time benefit of the
asynchronous solution was under some injection scenario
undermined by this unexpected HECI command.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I01a56bfe3f6c37ffb5e51a527d9fe74785441c5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
For compatibility reasons, egrep is just a wrapper around grep today.
Thus, replace it with `grep -E`.
Change-Id: Ief08a22e4cd7211a3fee278492c95d37f9e058fa
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This function calls into `set_feature_ctrl_lock()` to lock
IA32_FEATURE_CONTROL MSRfeature control.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9a03ee6786144dae6fd3a18bcc53cb62919dd42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This function calls into `set_feature_ctrl_vmx_arg()`
to enable VMX for virtualization if not done by FSP (based on
DROP_CPU_FEATURE_PROGRAM_IN_FSP config is enabled) in MeteorLake
SoC based platform.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This function performs locking of the AES-NI enablement state.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch calls into API to disable 3-strike error on
Meteor Lake SoC based platform.
TEST=Able to build and boot google/rex to ChromeOS.
Dumping MSR 0x1A4 shows BIT11 aka 3-strike error is disabled
```
localhost ~ # iotools rdmsr 0 0x1a4
0x0000000000000900
```
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This patch introduces a new config named
`DROP_CPU_FEATURE_PROGRAM_IN_FSP` to avoid FSP running basic CPU
feature programming on BSP and on APs using the "CpuFeaturesPei.efi"
module.
Most of this feature programming is getting performed today in scope
of coreboot doing MP Init. Running this redundant programming in
scope of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled)
results in CPU exception (for example: attempting to reprogram CPU
feature lock MSR is causing CPU exception).
SoC users should select this config after dropping "CpuFeaturesPei.ffs"
module from FSP-S Firmware Volume (FV). Upon selection, coreboot runs
those additional feature programming on BSP and APs.
This feature is by default enabled, in case of "coreboot running MP
init" aka `MP_SERVICES_PPI_V2_NOOP` config is selected.
At present, this option does not do anything unless any platform
eventually decides to drop FSP feature programming module and choose
coreboot CPU feature programming over it.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
In Intel designs, internal processor errors, such as a processor
instruction retirement watchdog timeout (also known as a 3-strike
timeout) will cause a CATERR assertion and can only be recovered from by
a system reset.
This patch prevents the Three Strike Counter from incrementing (as per
Intel EDS doc: 630094), which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74158
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Restrict DPTC to 15W boards, since we only have 15W values defined in
the devicetree. This will revert the 6W boards back to their default
values, rather than (incorrectly) configuring them with 15W values.
BUG=b:253301653
TEST=Verify DPTC values are set for 15W boards
TEST=Verify DPTC values are set not set for 6W boards
Change-Id: I94f3974fce6358e3cbb0c30c1af33eb7ecb29ad7
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74127
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP will return the TDP in the format 0xX0000, where 'X' is the
value we're interested in. For example: 0xF0000 (15W), 0x60000 (6W).
Re-interpret the value so the caller just sees the TDP directly, without
needing to re-interpret things themselves.
BUG=b:253301653
TEST=Manually verify value is correct
Change-Id: I632e702d986a4ac85605040e09c1afab2bbdc59d
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74126
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is needed to generate MADT and SRAT where lapicid for threads need
to be added last. When CPUID leaf '0xB' is not present assume some
defaults that would result in identical ACPI code generation.
Change-Id: I2210eb9b663dd90941a64132aa7154440dc7e5a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69222
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On some systems the BSP cannot know how many CPUs are present in the
system. A typical use case is a multi socket system. Setting the enable
flag only on CPUs that actually exist makes it more flexible.
Change-Id: I6c8042b4d6127239175924f996f735bf9c83c6e8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68892
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the current design the relocatable parameters are used to know the
offset of the 32bit startpoint. This requires back and forward
interaction between the stub, the loader and the mp init code. This
makes the code hard to read.
This is static information known at buildtime, so a better way to deal
with this is to generate a header that contains this offset.
Change-Id: Ic01badd2af11a6e1dbc27c8e928916fedf104b5b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64625
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's quite confusing to keep track of lapic ID inside the device
struct and initial lapic ID inside an array.
Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64342
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CONFIG_ARCH gives false positives for CONFIG_ARCH_X86_64_PGTBL_LOC so
use a different string: 'CONFIG_MAINBOARD_DIR'.
Change-Id: Ie5d4fc4693bc303afb16884c53c9ca4d1778a5cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74220
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Currently this is only used in bootblock and expects a fixed offset.
Change-Id: I3c4db6fffe3343f12383fe9585620ffefb01cf81
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add possibility to clone edk2-platforms repository. Some edk2
repositories may use modules from edk2-platforms which contains
various feature packages for Intel platforms, e.g VT-d driver if DMA
protection is enabled.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iabd0793dfdcb95260046dc992ff30ef581159db9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68872
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It will cache decoded EDID string in a static array. If called more
than once, a pointer to the static array is directly returned, without
reading EDID again.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74180
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drop devicetree setting X2apic as the same functionality is already
exposed in Kconfig.
To activate X2apic select X2APIC_ONLY or X2APIC_RUNTIME in
the "APIC operation mode".
Note: Your OS must have support for X2APIC. If you are using less
than 256 CPU cores select XAPIC_ONLY here.
Test:
- Booted to OS in X2APIC mode when X2APIC_ONLY or X2APIC_RUNTIME
was selected.
- Booted to OS in XAPIC mode when XAPIC_ONLY was selected.
Change-Id: I65152b0696a45b62a5629fd95801187354c7a93b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When more than 255 CPU cores are present on a board
the X2APIC must be used.
Select DEFAULT_X2APIC_RUNTIME to support X2APIC by
default when a mainboard enables it in the devicetree.
Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74184
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch renames debug FMD file (chromeos.debug-fsp.fmd) to
chromeos-debug-fsp.fmd in order to match the file path name in `FMDFILE`
config.
TEST=Able to build intel/mtlrvp with this code change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic8de07e4befa6b1ab8ab57d593c6939d87c48e9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Because Markarth PCIe port 1 use for eMMc not SD. So we need override
PCIe config for Markarth. And also the Markarth have NVMe and eMMC
SKU. Follow Winterhold to look at the NVMe CLKREQ signal before
initializing the ports allowing us to identify which device is populated
and only initialize that device.
BRANCH=none
BUG=b:275669215
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74133
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Inject ACPI code for all generated ASL templates.
This fixes ACPI errors shown in linux when not all sockets
are currently plugged in or some have been disabled.
Test:
Boot Archer City with CONFIG_MAX_SOCKET=4
Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74183
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
The RTD3 driver should have its 'use_rp_mutex' set in the devicetree.
BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the WWAN
The RTD3 RPMX mutex should be used in the reset Methods
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ic3fe20c56b67c2b5177f55f4845610087a30dc7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73381
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
When 'use_rp_mutex' (default = 0) is set in the device tree, a root
port mutex will be added. This mutex is used in _ON and _OFF method,
where the GPIO reset and/or enable GPIO value is changed. The
companion driver, such as WWAN driver, needs to acquire this root
port mutex when accessing the same GPIO pins. Using this common mutex
prevents those invoked methods from being called from different thread
while one is not completed.
An example is that WWAN driver calling _RST method to reset the device
and does remove/rescan for the device while the pm runtime work might
call RTD3 _OFF.
For those root port without additional driver, this mutex is not needed.
BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated and _ON and _OFF should use this
mutex.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ibc077528692b2d7076132384fb7bd441be502511
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
On Skyrim, there isn't a need for a sleep GPIO table. Remove the TODO
and filler table and function to reduce unnecessary function overhead.
BUG=None
BRANCH=Skyrim
TEST=Build Skyrim BIOS image.
Change-Id: Ia9d55a5e2295bb2e2c2957c4f5207362f616022c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
IF its first call is get_blc_pwm_freq_value(NULL), null dereference
will occur.
Now when the parameter is NULL, it will return the value of the static
blc_pwm_freq directly, so the original behavior is kept.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I32354aa0fe1a3ca725c2031f973ffad0bda81ad5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Update spd_gen and part_id_gen utilities to accommodate Phoenix platform
so that SPD can be generated for the memory parts used in that platform.
SPD requirements for Phoenix and Mendocino platforms are identical.
BUG=b:273383819
TEST=Run spd_gen and ensure that both Mendocino and Phoenix platforms
share the platform manifest for LP5 memory parts.
Change-Id: I7a12f73065864f08db8922c1a69eb503865a25b1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
This reverts commit e7a1204f26.
This initial change was causing a boot failure when transitioning into
recovery mode.
BUG=b:276927816
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas
SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into
recovery mode.
Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74207
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 11f2f88a27.
Revert initial change as it was causing a boot failure when
transitioning into recovery mode.
BUG=b:276927816
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas
SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into
recovery mode.
Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the newly introduced 'all_x86' make target to add the mode_switch.S
compilation unit to all stages that run on the x86 cores, but not to
verstage on PSP.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8950375d31557d9a38169869c1d250417261c31c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Use the 'verstage_x86' make target for the mode_switch.S compilation
unit instead of making adding it to the 'verstage' target depending on
VBOOT_STARTS_BEFORE_BOOTBLOCK not being selected. The only case where
VBOOT_STARTS_BEFORE_BOOTBLOCK is selected is the verstage on PSP case,
so I find using the 'verstage_x86' target here a bit easier to
understand.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab618d4b9e325b07a648b91fcdce99c63644fbfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74196
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the newly introduced 'all_x86' make target to add the compilation
unit to all stages that run on the x86 cores, but not to verstage on
PSP.
TEST=Timeless build for Mandolin results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23c6977ae8acebb8dcd546f86f7f7b677272a6cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74153
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the newly introduced 'all_x86' make target to add the compilation
unit to all stages that run on the x86 cores, but not to verstage on
PSP.
TEST=Timeless build for Mandolin results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I181c3207bb1ebe9c5080ef3a3cdda8146ed05822
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74152
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the newly introduced 'all_x86' make target to add the compilation
unit to all stages that run on the x86 cores, but not to verstage on
PSP.
TEST=Timeless builds for Mandolin without verstage on PSP and Guybrush
with verstage on PSP result in identical images with and without this
patch applied.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94de6de5a4c7723065a4eb1b7149f9933ef134a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74151
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
For compilation units that should be built for all stages that run on
the x86 cores in a newer AMD SoC, but can't be built for verstage on PSP
which is an ARM core, the 'all' target can't be used, since that would
result in the compilation unit also being added to the verstage target
in the verstage on PSP case. In order to not need to add a compilation
unit to the 'bootblock', 'verstage_x86', 'romstage', and 'ramstage'
targets in separate lines in the Makefile, introduce the 'all_x86'
target that adds a file to 'bootblock', 'verstage_x86', 'romstage',
'postcar', and 'ramstage'. The compilation units also need to be added
to the 'postcar' stage which is only present on the pre-Zen SoCs to be
able to also use the 'all_x86' target in common AMD code that is also
used in those pre-Zen SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d0184182b931185990094d0874b49c0b5cb9f7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74150
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add the required CMOS entries for the mirror flag, so that it can
be enabled from a defconfig.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I174ac896df050480ee90c8141c5536b628c98432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73682
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When enabled, the EC will mirror the firmware contained inside the
coreboot ROM. This allows it to be updated at the same time as
coreboot.
Enable the mirror flag if the installed EC firmware does not match
the target version or if a CMOS option, "manual_mirror_flag" is
set.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I377abbb37dc4d3e535e518a73e73969b25967daa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some third-party SSDs, from Samsung and WD, such as the 990 Pro and
WD Black 850X aren't initialised by coreboot, seemingly as coreboot
is too quick; debug builds work, and enabling hotplug does.
Add a cmos option `pci_hot_plug`, defaulting to enabled to allow these
SSDs to work.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I680211bc87153a5e6005d58040a94725c0973451
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
ASPM is already configured by FSP so disable it in coreboot to
reduce boot time by a whopping 34ms.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I073c68dafa9baa90e253b5230f84b0de6a7e5c47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
This was added to solve Debian 10 not booting. Debian 10, which
now isn't the latest stable version works, so remove the
workaround that was included in the original port.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Elyes Haouas