This change only enables the IOMMU device. We still require the IVRS
table to take advantage of the IOMMU. This will happen when the picasso
IVRS code is moved into common.
BUG=b:190515051
TEST=lspci shows IOMMU device
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The new function is called acpigen_write_if_cond_refof(), and it must
be paired with a following acpigen_write_if_end() call.
Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently, we get PLD information from USB port structure itself, so
devicetree does not need to fill PLD structure anymore. Thus remove
obsolete variable.
Change-Id: I7a561677ab65ddb870d1b00b35ee9d7a22ef9c70
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We need to reference correct USB port number for driver to
identify type-C port number correctly.
BUG=b:189476816
BRANCH=None
TEST=Check the transactions are happening on correct port. Also checked
retimer firmware update on both the ports.
Change-Id: I20c088ee81610155067abad086eba8d72f73ad60
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since TBT controller can have maximum 2 ports per controller, our
code will loop over DFP structure twice and determine port number.
Retimer driver used to assign port number as below:
1. Check if power GPIO is assigned for particular DFP entry or not
2. If entry is there, assign loop count as port number
Since loop count is 2, retimer will never assign port number = 2
even if it's present. In case of more than 1 controller, port number
assigned will still be 0 or 1 even though actual port index might
be 2 or 3. This will create an issue where even if you do transaction
on device on controller 2 (port index 2 or 3), EC will route it on
port 0 or 1 due to incorrect port index.
Update the driver flow as per below to handle this scenario:
1. Check if power GPIO is assigned for particular DFP entry or not
2. Get USB port number from config since it's stored in usb port
information under devicetree
3. Pass the port number to ACPI SSDT and EC code
Above changes will ensure that we're assigning correct port
number as per calculation and EC will use correct port index.
BUG=b:189476816
BRANCH=None
TEST=Checked that retimer firmware update works on both ports and update
happens on correct port index.
Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create a separate function to get PLD information from USB device.
This is helpful in retimer driver where we can attach same USB
port information to retimer instance and we can avoid duplication
of information.
BUG=None
BRANCH=None
TEST=Check if code compiles and function returns correct value
Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The Majolica UEFI ACPI tables have this listed as shared. It's already a
level interrupt, so no reason it shouldn't be shared.
This change makes it so Windows can correctly initialize the GPIO
controller.
BUG=b:186212501
TEST=Boot guybrush to windows and see GPIO controller functional. Also
boot guybrush to windows and verify GPIO controller still works.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Previously, irq_program_non_pch() was only programming the IRQ line, but
the pin is required as well.
BUG=b:176858827
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I2a2823c183a3495721a912de285cddb4a9444c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56174
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures max Pkg C-state to Auto which limits the max
C-state to deep C-state
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create the kano variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:193052432
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KANO
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the implementation for vcore voltage control.
Also remove the reporting of vio18 because it is fixed during DRAM init,
and we won't provide drivers for reading or writing it.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56106
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to
identify implementations for Chromebooks (in coreboot) so we want to
introduce a new flag FOR_COREBOOT to prevent confusion.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56158
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 1aa60a95bd broke microcode loading for chipsets that have a
microcode blob with a total_size field set to 0. This appears to be
support for older chipsets, where the size was set to 0 and assumed to
be 2048 bytes. The fix is to change the result of the subtraction to a
signed type, and ensure the following comparison is done without
promoting the signed type to an unsigned one.
Resolves: https://ticket.coreboot.org/issues/313
Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56153
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All of the build configuration is set to produce big endian image on PPC64.
In addition, the toolchain produced by coreboot-sdk does not include little
endian libraries so it is not possible to build LE image even when that
configuration is changed.
This patch changes byte order definition which is required for proper work
of functions that deal with endianness, like read_{le,be}*() or
{le,be}*toh().
It also revealed bugs related to the endianness on BE targets that are
addressed in the following patches.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: Id31328a832d11db20822733304b0ae477e858d25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The second generation EFS (offset 0x24[0]=0) uses
"binary relative" offsets and not "x86 physical
MMIO address" like gen1.
Chips like Cezanne can run in both cases, so no problem
comes up so far.
BUG=b:188754219
Test=Majolica (Cezanne)
Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove register "generic.stop_delay_ms" and measure data, it still
can meet elan touchscreen specification that reset pull high to
I2C time > 150ms (T3 > 150ms).
BUG=b:185308246
TEST=Measure the T3 delay time is greater than 150ms on voema
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56087
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the redrix variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:192052098
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_REDRIX
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch sets the disable the external voltage rails since brya
board doesn't have V1p05 and Vnn bypass rails implemented.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update Power Limit2 (PL2) minimum value to the same as maximum value.
DTT does not throttle PL2, so this minimum value change here does not
impact any existing behavior on the system.
BUG=None
BRANCH=None
TEST=Build and test on tglrvp system
Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Coverity detects dereference pointers req and res that are NULL when
calling the pmc_send_ipc_cmd function. This change prevents NULL
pointers dereference.
Found-by: Coverity CID 1458077, 1458078
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Due to new sku id apply for AMP ALC1015Q-VB. Modify correct WIFI-SAR
detect condition for boten/botenflex sku.
BUG=b:186174768
TEST=build and test on boten/botenflex
Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Configure I2C high / low time in the device tree to ensure I2C
CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
touchpad:390.4 kHz
BUG=b:192601250
BRANCH=dedede
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
There is a 16 MB flash chip on mc_ehl. Set the ROM size accordingly and
provide a flashmap for partitioning. Select the used flashmap on variant
level to allow different layouts for different variants.
Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Remove Kconfig switches that are not needed for mc_ehl based mainboards.
Change-Id: If231f37f06c6763d52a821799e87fdb3010af0aa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Currently ifdtool breaks the descriptor because it treats it as IFDv1.
This change adds it to the list of IFDv2 platforms.
Fixes boot for X11SSH-LN4F.
Fixes: 8c082e5fef ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset")
Change-Id: I3f92b090e929336b5c18b442d1504ee1000f5594
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56070
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In x86_64, the first function parameter is passed in rdi register, and
the 32-bit code after exiting long mode reads the resume vector in
4(%esp), so it's needed to save the resume vector from rdi to 4(%rsp).
Also note that the function attribute "regparm" only works on x86-32
targets according to the GCC manual, so "asmlinkage" doesn't change
the ABI of an x86_64 function.
Tested on HP EliteBook 2560p. The laptop can resume from S3 in x86_64
mode after this change.
Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55947
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pointer to the header has a x86 top mmaped address even though the
boot medium is not mapped that way. If no pointer is used to find the
header FMAP is needed. If FMAP is used anyway there is no need for a
cbfs master header.
Change-Id: I6d693bdd4ddaf4c9b3cffb4ea9879c761200aca9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add IFITTOOL as a dependency where needed and remove where it is
unneeded.
Change-Id: I88c9fc19cca0c72e80d3218dbcc76b89b04feacf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is already handled in $(prebuild-files).
Change-Id: I648f97198772d30d6d267ab9d6f7fa8d1d5d0e91
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The dramc_param.h defines the header version,
structure and APIs for the DRAM calibration parameters
stored on the flash, and should be platform independent.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Enable DCM settings on the MT8195 platform.
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
Change-Id: Ib431a0334c157d440d6e89dcb154241d980d97ce
Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Raul E Rangel