Commit Graph

24718 Commits

Author SHA1 Message Date
Nico Huber e100fe4a59 Revert "3rdparty/blobs: Update submodule marker for Intel microcode updates"
This reverts commit 0ff9daac45.

It points to a stale commit under review; i.e. not to a commit on
blob.git's master branch like it's supposed to.

Change-Id: I19cb8a32b3971c3104e381673ca08ae4d3979128
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-12 20:17:02 +00:00
Furquan Shaikh c6141b9451 mb/google/poppy/variants/nami: Provide implementation of mainboard_vbt_filename
This change adds board-specific implementation of
mainboard_vbt_filename which returns "vbt.bin" by default. This is in
preparation to allow multiple vbt binaries to be added to single
image. More sku_id specific names will be added in follow-up CLs.

BUG=b:79396300

Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-12 08:13:38 +00:00
Youness Alaoui d319b98279 purism/librem_bdw: Rename Broadwell baseboard from BDL to BDW
My bad, it seems the acronym for Broadwell is BDW, and not BDL, so
I'm renaming librem_bdl into librem_bdw and changing the KConfig
options accordingly.

Change-Id: I8e992aa3474863236adf8893fcbe37c1b801fa25
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26237
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11 18:23:48 +00:00
Aaron Durbin 44f80657fd drivers/intel/gma: honor vbt_size parameter to locate_vbt()
In 4a3956d7 (drivers/intel/gma, soc/intel/common: improve
cooperation) the vbt_size parameter was not honored leading to
the use of unitialized variables from the caller. Instead, keep
track of if the vbt is already loaded by using the size returned
from the load. If it's non-zero the vbt has been loaded.

BUG=b:79562868

Change-Id: Ia1c47f0d982fae74e0223922f83943c68a846aa9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26236
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11 18:16:13 +00:00
ren kuo f064c75ae2 mainboard/google/coral: Override VBT selection for epaulette
Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.

Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms

BUG=b:78541692
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
     Run on DUT and check panel sequence meets spec.

Change-Id: I5f9103aca7871095a828a74cd6a97e1951adb81f
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/26214
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11 13:01:38 +00:00
ren kuo 88c9d98b64 mb/google/reef/variants/: Add new memory ID
Add a new RAM ID of memrory PN:MT53E512M32D2NP

BUG=b:78491470
TEST= emerge-coral coreboot chromeos-bootimage.

Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>

Change-Id: I855702c2850887df74941e00da69322124557498
Reviewed-on: https://review.coreboot.org/26213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
2018-05-11 13:01:15 +00:00
Iru Cai 056cbbe3f5 asrock/b75pro3-m: Add superio ACPI declarations
Without it the PS/2 keyboard doesn't work after booting into the OS.

Change-Id: Idcb0ea0779fcd5dfd6e0fbf33a532ecf0caec420
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/26131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 09:14:19 +00:00
Youness Alaoui 0cf89bf20a purism/librem_bdl: Add support for Librem 15 v2
Adding new librem_bdl variant for the Librem 15 v2, which is very similar
to Librem 13 v1, with the following differences:
- SATA ports 0 and 1 instead of 0 and 3
- SATA DTLE IOBP value is 7 instead of 9 for port 0
- There is no LAN device
- There are two SODIMM slots, and DQs are interleaved
- USB ports are different

Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 09:09:20 +00:00
Youness Alaoui b799e0df3d purism/librem_bdl: Convert to variant setup
Convert the purism/librem13v1 to a variant setup, in
preparation for adding the librem15v2 board as a new variant.
The Librem 13 v1 and Librem 15 v2 are nearly identical, so
this minimizes new code to add support for the latter.

Also update the URL in board_info to an archive.org link.

Change-Id: I00bb82b9e895e2464ddaa92915c01ce0e35933a2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 09:08:18 +00:00
Elyes HAOUAS 96184e9f2d nb/intel/i945/bootblock.c: Correct comment
Change-Id: Ic28ff80eb1dae6d0a307e2a1b73e8129fffbac13
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 09:05:40 +00:00
Elyes HAOUAS 322fa32e5e nb/intel/i440bx: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I69c8b95ff1937c0b08147d9e26a3118c58129cf5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-11 09:02:55 +00:00
Duncan Laurie 3e7197a59e acpi: Add support for writing ACPI _PLD structures
This commit adds support for writing ACPI _PLD structures that
describe the physical location of a device to the OS.

This can be used by any device with a physical connector, but is
required when defining USB ports for the OS.

A simple function is provided that generates a generic _PLD
structure for USB ports based on the USB port type.

Change-Id: Ic9cf1fd158eca80ead21b4725b37ab3c36b000f3
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-11 09:00:33 +00:00
Duncan Laurie beb2af4e35 acpi: Add support for generating ACPI _UPC
This commit adds support for writing ACPI _UPC structures that
help describe USB ports for the OS.

This is a simple structure format which indicates what type of
port it is and whether it is connectable.  It should be paired
with an ACPI _PLD structure to define USB ports for the OS.

Change-Id: Ide3768f60f96e9ad7f919ad3fb11d91045dc174a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11 09:00:20 +00:00
Duncan Laurie bae9f85ddb devicetree: Add USB device type
This commit adds support for describing USB ports in devicetree.cb.
It allows a USB port location to be described in the tree with
configuration information, and ACPI code to be generated that
provides this information to the OS.

A new scan_usb_bus() is added that will scan bridges for devices so
a tree of ports and hubs can be created.

The device address is computed with a 'port type' and a 'port id'
which is flexible for SOC to handle depending on their specific USB
setup and allows USB2 and USB3 ports to be described separately.

For example a board may have devices on two ports, one with a USB2
device and one with a USB3 device, both of which are connected to an
xHCI controller with a root hub:

     xHCI
       |
    RootHub
    |     |
USB2[0]  USB3[2]

device pci 14.0 on
  chip drivers/usb/acpi
    register "name" = ""Root Hub""
    device usb 0.0 on
      chip drivers/usb/acpi
        register "name" = ""USB 2.0 Port 0""
        device usb 2.0 on end
      end
      chip drivers/usb/acpi
        register "name" = ""USB 3.0 Port 2""
        device usb 3.2 on end
      end
    end
  end
end

Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11 08:59:51 +00:00
Philipp Deppenwiese 57df088816 Dokumentation: Sphinx add RST in markdown support
* This feature embedds RST into markdown for
table generation.

For more information, see
http://recommonmark.readthedocs.io/en/latest/index.html#autostructify

Change-Id: Iefebb3b7857bc98818e345f7d0e95fbf987305a8
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/26190
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11 08:58:08 +00:00
Caveh Jalali 129cee4d04 mb/google/poppy/variants/atlas: add SPD for new samsung 4GB memory
This adds a new SPD entry for samsung's new 4GB memory and updates
atlas to use it instead of the previous gen memory.

BUG=b:79444337
TEST=booted on atlas

Change-Id: I19567736c45a1321586378c3d964c2cbebe24755
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/26185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11 08:57:50 +00:00
Shamile Khan 644b2dd6e0 mb/google/octopus: Ignore standby state for DMIC pins
This keeps Audio clock and data pins ON in S0ix to support
Wake on Voice.

BUG=b:77605180
BRANCH=none
TEST=Checked that S0ix suspend/resume works. Validation of WoV
was done on glkrvp previously. For Yorp, audio topology firmware
updates are required for testing WoV.

Change-Id: Idafe4e7d24fe16f8e8ff3dd86e299776ea860d03
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/26202
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11 08:57:35 +00:00
Martin Kepplinger 0ff9daac45 3rdparty/blobs: Update submodule marker for Intel microcode updates
This moves the blobs submodule marker forward to include the following:

b45abbd cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models

in short: bump Intel's microcode updates to the latest version. This
includes Spectre/Meltdown mitigations.

Change-Id: I4ab74ae0bdcf2a109b0697ad233fbb812b5c4544
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/25505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11 06:33:43 +00:00
T.H. Lin 925b91a807 mb/google/poppy/variants/nami: add 2-channel LPDDR3 memory
hynix/H9CCNNNCLGALAR-NUD
nayna/NT6CL256T32CM-H1

BUG=b:79443146
BRANCH=Nami
TEST=emerge-nami coreboot chromeos-bootimage

Change-Id: I3a362080b9e60adecbac14d5cfe193da44bf87c8
Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-11 00:57:05 +00:00
Kyösti Mälkki 5023c328e2 AGESA f14: Remove OPTION_DDR2
Was never used for the boards in our tree.

Change-Id: Ib9e9ab25ccb8d1d556fdeb8bb4c6558f25bb81b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-10 17:54:39 +00:00
Kyösti Mälkki ba4e695d83 AGESA f14 vendorcode: Only have f14 Ontario config
Change-Id: I8cf2f23d785e934371dfa687483491cd22b9863d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-10 17:54:17 +00:00
Julius Werner ae05d095b3 bootmem: Keep OS memory map separate from the start
The patch series ending in 64049be (lib/bootmem: Add method to walk OS
POV memory tables) expanded the bootmem framework to also keep track of
memory regions that are only relevant while coreboot is still executing,
such as the ramstage code and data. Mixing this into the exsting bootmem
ranges has already caused an issue on CONFIG_RELOCATEABLE_RAMSTAGE
boards, because the ramstage code in CBMEM is marked as BM_RAMSTAGE
which ends up getting translated back to LB_RAM in the OS tables. This
was fixed in 1ecec5f (lib/bootmem: ensure ramstage memory isn't given to
OS) for this specific case, but unfortunately Arm boards can have a
similar problem where their stack space is sometimes located in an SRAM
region that should not be made available as RAM to the OS.

Since both the resources made available to the OS and the regions
reserved for coreboot can be different for each platform, we should find
a generic solution to this rather than trying to deal with each issue
individually. This patch solves the problem by keeping the OS point of
view and the coreboot-specific ranges separate from the start, rather
than cloning it out later. Ranges only relevant to the coreboot view
will never touch the OS-specific layout, to avoid the problem of losing
information about the original memory type of the underlying region that
needs to be restored for the OS view. This both supersedes the
RELOCATABLE_RAMSTAGE fix and resolves the problems on Arm boards.

Change-Id: I7bb018456b58ad9b0cfb0b8da8c26b791b487fbb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-10 01:24:40 +00:00
Martin Roth 40e6d2ebbd mainboard/google/.../terra: Fix ACPI external definition errors
According to ACPI 6.1 spec 19.6.44, External informs compiler that
object is external to this TABLE, no necessary for object in same DSDT
tables.

A name cannot be defined and declared external in the same table (GPID)
A name cannot be defined and declared external in the same table (CTOK)

Change-Id: Ica80b59ad6a8af865bf1551ac4e014ec5f4e7d08
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26122
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09 16:21:40 +00:00
Sathyanarayana Nujella 9146ccd7e3 mb/google/poppy/variants/nocturne: update Audio configuration
This patch updates the below:
1)
Nocturne board has only Max98373 speaker amp.
Update both NHLT and DT entries to include only Max98373
and not include DA7219.

2) I2S2 is used for Boot Beep.
   So, update GPP_F0 ~ F2 pins accordingly.

3) Include DMIC-4ch configuration.

BUG=b:79362472
TEST=None [Waiting for HW to verify]

Change-Id: I0e9b3a564c22de6e84e96e5e937a3aca4ae73d75
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26143
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09 16:20:18 +00:00
Patrick Rudolph f706f8bffd lenovo: Add various data.vbt
Add the Video Bios Table to improve user experience when running
coreboot's blob free graphics init.
As it's not a binary blob it should not be added to the blobs repo.

This is taken from vendor BIOS and contains purely documented
configuration data, so it should not be subjected to copyright.

Extracted using intelvbttool with applied patch
I8cbde042c7f5632f36648419becd23e248ba6f76 "util/intelvbttool: Rewrite tool"

Change-Id: I15573ddd37ee9738df1f7178f967131687a50f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-09 16:19:48 +00:00
Martin Roth dea13331a1 util/lint: Ignore whitespace, newlines, and licenses in vbt files
Change-Id: I84f612db058d83936ddd5a6baa32c993e5b0f594
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09 16:19:36 +00:00
Patrick Georgi 4a3956d7cc drivers/intel/gma, soc/intel/common: improve cooperation
Instead of both featuring their own VBT loaders, use a single one.
It's the compression-enabled one from soc/intel/common, but moved to
drivers/intel/gma.

The rationale (besides making all the Kconfig fluff easier) is that
drivers/intel/gma is used in some capacity on all platforms that load a
VBT, while soc/intel/common's VBT code is for use with FSP.

BUG=b:79365806
TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected
code paths.

Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/26039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09 13:48:07 +00:00
Gergely Kiss 60ad1a7132 mainboard/asus/am1i-a: fix interrupt routing definitions in DSDT
Incorrect interrupt routing configuration prevented handling
interrupts for devices behind PCIe bridges 00:02.1 and 00:02.5.
With the new configuration, devices work as expected.

Tested with Linux 4.10 booted with the "pci=nomsi" parameter.

Change-Id: I3c95be7ba6207697afc7983d4b5f9d9a28584723
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09 13:17:34 +00:00
Elyes HAOUAS 0a06325907 mb/technexion: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I6efd1675b1124b200b5ff16fdef91c10b77b69d1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09 13:16:25 +00:00
Elyes HAOUAS 477a516ec3 mb/avalue: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I7f1276ee593928956913eaeecd62fd3018cc9ae2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09 13:16:12 +00:00
Elyes HAOUAS 51c6a610d8 mb/asrock: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I4b2b8593c98791dac7a5c016e75d2c05bcfbf890
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09 13:16:07 +00:00
Elyes HAOUAS a07b542fad mb/a785e-i: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I15f160c1e30496461f7100e3bd3a2e2467c64c4a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09 13:15:59 +00:00
Elyes HAOUAS 99f0a51de3 cpu/amd/quadcore: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I6cb8f36dea4a22fdf05c57bb3e3dcaeb2da8020f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09 13:15:53 +00:00
Elyes HAOUAS 02b05d1f6b mb/asus: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I8fe817bb514c69a647c2208a0573a2c5fe98722d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09 13:14:37 +00:00
Elyes HAOUAS 5a0757cf74 mb/bap: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I6fc056acb8ff16a943352342b99a9ede6558d438
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09 13:13:17 +00:00
Elyes HAOUAS 4b2c71f657 mb/amd: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I01270248bddf07df4c959f0c632e722728d0cd03
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09 13:12:46 +00:00
Elyes HAOUAS 1943f3798d {device,drivers,lib,mb,nb}: Use only one space after 'if'
Change-Id: I390191fb58605d1bd6a2e5d19a9dfa7c8493e6b2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09 13:11:04 +00:00
T Michael Turney 5b66288d51 sdm845: Add DRAM resources
TEST=build

Change-Id: Icf934caf8b4584ef2633054a5cc7f5be7cc734ee
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-09 10:15:58 +00:00
Martin Roth 621e4d8b48 src/southbridge: Serialize methods with named objects inside
Change-Id: Ia9d884d7247f0cc3a175de31649d0163c69f1299
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09 10:14:27 +00:00
Martin Roth 49a4c6af58 src/mainboard: Serialize methods with named objects inside
Change-Id: I90e1d8b9f8e37bec8fc2796637b4548ea17e076b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-09 10:14:01 +00:00
Martin Roth 0ba2652837 mainboard/bap/ode_e20xx: Remove commented out asl code.
Change-Id: I64229d12e9e7fd54eaae3425ae9546872c5bf8f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-09 10:13:39 +00:00
Richard Spiegel 4bb706555e vendorcode/amd/pi/00670F00: Control which procedure builds
Vendor code is compiled as a library, thus the whole library is included
into the final image. However, not all procedures are required, they are
there because original AGESA code had them. We cannot remove them, in order
to facilitate porting of fixed AGESA code. Therefor add #if throughout the
code to allow the control if unneeded procedures will be build.

BUG=b:78610011
TEST=Build and boot grunt; build kahlee and gardenia.

Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26135
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09 10:12:33 +00:00
Richard Spiegel 9c1dc7cbe1 vendorcode/amd/pi/00670F00: Remove unneeded includes
Vendor code has several headers included into source code that are not
needed in order to build them. Remove unneeded #include. This is part of
controlling the build of unneeded procedures within vendor code.

BUG=b:78610011
TEST=Build grunt.

Change-Id: Id7d451b6be564632836fc64fd343131edb85183a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-09 10:12:24 +00:00
Elyes HAOUAS ae27430a3c mb/gizmosphere: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I75258ecc5f3881012c3f767c8b970a1f10c6abbd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09 10:09:44 +00:00
Elyes HAOUAS 547c5aa2b5 mb/elmex: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: If4ec2e2e7cca8d8f3e5abfd9cd204f86e367b44a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09 10:09:39 +00:00
Elyes HAOUAS c390e7e605 mb/esd: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: I5928e871b8e9ba5964c02fbabb7a9d8dc9ecc0a8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09 10:09:35 +00:00
Harsha Priya 78ccdbf15b mainboard/google/eve: Add subsystem_id
This patch adds subsystem_id for eve as 0x006B. The value
is set in nhlt structure which will be used by endpoints as well.

Change-Id: Id6910678c4d6e92ed45c776f174855efd26f9e27
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-09 10:08:41 +00:00
Harsha Priya 5c31511f35 lib/nhlt: add support for passing subsystem_id to endpoint's structure
This patch adds subsystem_id to nhlt structure whose value is
passed on to the endpoint's structure. Its default value is
retained to be NHLT_SSID.

Change-Id: Iad53f27e958f50e02e928cd8fa60d8397ca0eb06
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26046
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09 10:06:04 +00:00
Patrick Georgi 3b755c20f8 util/xcompile: prefer riscv64 over riscv
gcc 8.1 insists.

Change-Id: I8cb00fafdfff7679e38f357c6e8968da656c351d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/25995
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09 10:00:32 +00:00
Kyösti Mälkki cebb684417 console: Skip non-BSP printk() earlier
Fix regression after commit:
  6032018 console: only allow console messages after initialization

Bail out early on AP CPUs, this avoids use of CAR_GLOBAL when
we have SQUELCH_EARLY_SMP=y.

Change-Id: I506c5fbec43a6eb6f6d9362d62a040def9e1e7bb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-09 05:21:21 +00:00