Commit Graph

2169 Commits

Author SHA1 Message Date
Myles Watson b8c2aa2ce8 Change references to qemu in Coreboot-v2 calls to qemu-x86.
The patch was followed by these svn commands:

svn mv targets/emulation/qemu-i386/ targets/emulation/qemu-x86
svn mv --force targets/emulation/qemu-i386/ targets/emulation/qemu-x86
svn mv --force src/mainboard/emulation/qemu-i386/
src/mainboard/emulation/qemu-x86
svn mv --force src/cpu/emulation/qemu-i386/ src/cpu/emulation/qemu-x86

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-07 20:37:37 +00:00
Myles Watson f2b380ad85 This patch changes the Config.lb files and adds Config-lab.lb files for
architectures supported by buildrom.

Myles

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-06 22:33:50 +00:00
Carl-Daniel Hailfinger c23b3a5732 Handle JEDEC JEP106W continuation codes in SPI RDID. Some vendors like
Programmable Micro Corp (PMC) need this.
Both the serial and parallel flash JEDEC detection routines would
benefit from a parity/sanity check of the vendor ID. Will do this later.

Add support for the PMC Pm25LV family of SPI flash chips.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Chris Lingard  <chris@stockwith.co.uk>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-06 22:07:58 +00:00
Myles Watson a7c92a6dc4 This patch changes all rom names that aren't coreboot.rom in Config.lb files.
I think that since the directory specifies the architecture and the
board, it is redundant information to name it something else, and it
makes it more difficult to automate the build process (buildrom).

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-05 21:53:15 +00:00
Carl-Daniel Hailfinger cb5c9fb9e3 Factor out print_conf() from Geode LX mainboard directories. The
following mainboard files had identical Geode LX specific print_conf()
implementations:
mainboard/amd/db800/mainboard.c
mainboard/amd/norwich/mainboard.c
mainboard/digitallogic/msm800sev/mainboard.c
mainboard/pcengines/alix1c/mainboard.c
Move print_conf() to northbridge/amd/lx/northbridge.c where it belongs.

Add a copyright notice to mainboard/digitallogic/msm800sev/mainboard.c.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-05 09:21:46 +00:00
Florentin Demetrescu 10aca3cae2 This patch fixes the decoding of the IO address range 0x0820->0x0827 into the
LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI
interface of the IT8716 SIO chip.
 Changes :
  1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some
functions of a PNP device can have more than 12 resources (ex the GPIO function
of IT8716f), in which case one could have an "array overflow" inside the device
structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at
device init time..)
  2) - define resource masks for the GPIO function in
src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO
ranges which are set into the LPC bridge of the SB are very strange (f.ex.:
0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the
GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching
by the init code
  3) - enable the flash SPI interface into
src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource
into the GPIO function). I know that this is problematic because not all m57sli
boards are SPI, but .. do anyone have a better idea how to handle this?..

Signed-off-by: Florentin Demetrescu <echelon@free.fr>

I (Ward) have verified your patch on a rev2 of this board (it works!) as well
as on a rev1 (plcc). It does not affect flashing on rev1 nor have any averse
side effects that I noticed, so I think this patch should go in.

Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-01 23:14:40 +00:00
Ward Vandewege d8a74c95d1 This patch reverses an erroneous change that sneaked in during r2972, and broke
flashrom on the plcc-based rev 1 and 1.1 of the Gigabyte m57sli-s4 board.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-01 23:07:04 +00:00
Jordan Crouse f3dd1b7e57 v2: Fix Serengeti-Cheetah flags too
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-28 22:55:47 +00:00
Jordan Crouse 71a82254ef [V2]: Add CFLAGS to targets to suck in any passed in flags
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-28 19:22:29 +00:00
Jon Dufresne ca31bc3cd5 Fix mptable util so the output will compile
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-28 00:04:23 +00:00
Uwe Hermann d27aa6eff5 Add support for the Abit BE6-II V2.0 board.
Tested on actual hardware by Sergei Antonov <saproj@gmail.com>. 

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Sergei Antonov <saproj@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 17:25:49 +00:00
Peter Stuge e2bbcb10d1 Make the vendor name optional in the -m flashrom parameter when there's only
one board name that matches. The full syntax still works, and is required
when two vendors have boards with the same names.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 16:21:21 +00:00
Patrick Georgi 3bbf2ff789 Add a new record type "console" for lbtable, and insert one record
for each output device we support, so the payload can figure out
where to find consoles that the user cares about.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 14:12:54 +00:00
Peter Stuge 2d94dead69 Forgot to add Spansion S25FL016A to README, trivial.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 07:17:14 +00:00
Ronald G. Minnich 25a37449c5 This patch fixes the remaining stack protector problem on v2. The DISTRO_CFLAGS were not being
included on the CC line for cache_as_ram_auto.c

Tested on ubuntu, where formerly it failed.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-26 16:57:03 +00:00
Marc Jones 2db9464299 Correctly disable the ROM area Write Protect bit in the Geode LX.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>

Tested on the pcengines alix1c and works fine.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-26 07:35:47 +00:00
Patrick Georgi 873312d699 bsh/ksh-clone and make(1)-syntax don't go well together
(unlike 5 lines later where make syntax is emitted into a file)

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 19:31:26 +00:00
Patrick Georgi 8c2a0c1445 This patch adds a new record type for lbtable to provide information
about a serial port. If a port is defined in the board configuration,
add it to lbtable.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 18:28:18 +00:00
Uwe Hermann 1a6177b720 Various small fixes and updates for lxbios (trivial).
- Update website URL to http://coreboot.org/Lxbios.

 - Use svn:keywords property to actually expand the $Id$ entries.

 - Update COPYING to the latest version from
   http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 15:08:37 +00:00
Peter Stuge f2a2a5ee2e Add ids and chip entry for Spansion S25FL016A to flashrom, tested,
working.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 01:52:45 +00:00
Marc Karasek 14a3af111d Use "--build-id=none" as linker flags if build-id is supported.
That fixes a compilation failure.

Signed-off-by: Marc Karasek <marc.karasek@sun.com> 
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 16:09:36 +00:00
Harald Gutmann bb9c1aa54e Here is just a little and simple patch to get the MX25L3205D working.
I've tested and verified the chip myself, and it seems to work
everything like supposted, since Carl-Daniel has patched flashrom to
use the read funktion on verifying. 

"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... 
Serial flash segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
MX25L3205 found at physical address 0xffc00000.
Flash part is MX25L3205 (4096 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.
benchvice flashrom # ls -l test.4mb
-rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 16:03:19 +00:00
Carl-Daniel Hailfinger a6941beb43 Flashrom did not use the read function for verifying, it used direct memory
access instead. That fails if the flash chip is not mapped completely.
If the read function is set in struct flashchip, use it for verification
as well.

This fixes verification of all SPI flash chips >512 kByte behind an
IT8716F flash translation chip.

"MX25L8005 found at physical address 0xfff00000.
Flash part is MX25L8005 (1024 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED."

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 15:19:01 +00:00
Carl-Daniel Hailfinger 468413a337 Make sure we delay writing the next byte long enough in SPI byte
programming.
Minor formatting changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 14:37:31 +00:00
Ronald Hoogenboom 21efd9ffe2 Omitting the wait for SPI ready when there is no data to be read, e.g.
readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing
programming time for SST25VF016B to 40-45 secs.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-21 23:55:08 +00:00
Bernhard Walle 679c62c083 This patch adds version information to flashrom. Because 'v' and 'V'
are already in use, the patch uses 'R' (for release) and, of course,
'--version'.

Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-21 15:24:22 +00:00
Stefan Reinauer 8ce4a19b20 last try i hope. Building with a payload changes the result of the rom
image. Even if the rom image size is not changed, it can make the linking fail.
It's almost a heisen-bug, only there if you don't watch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-20 01:59:43 +00:00
Stefan Reinauer c2bcc893ea give it 2k more space for abuild. let's look into this anyways, but get rid of
the impression that the cheetah on fam10 is broken just because we're using a
too new compiler for abuild. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-20 00:24:23 +00:00
Uwe Hermann 593f5aab03 Add Bingxun Shi <bingxunshi@gmail.com> to the list of contributors (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 09:43:48 +00:00
Uwe Hermann fb348035a3 Small superiotool fix to detect more Winbond W83627EHF chips. The
patch is tested on actual hardware.

As per datasheet the ID should be 0x886? for those chips.
Not mentioned in the datasheet, but sensors-detect says
0x8853 is also possible. Also, the ASUS A8V-E Deluxe
(W83627EHF) has an ID of 0x8854 (verified on actual hardware).

So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 09:40:17 +00:00
Bingxun Shi 34a576fb98 This patch is for winbond w83627DHG superio support in superiotool.
I have test that on my board, it works ;)

Signed-off-by: Bingxun Shi <bingxunshi@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 00:32:07 +00:00
Ronald Hoogenboom 2f0f561f89 Support SPI flash chips bigger than 512 kByte sitting behind IT8716F
Super I/O performing LPC-to-SPI flash translation.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 00:04:46 +00:00
Uwe Hermann cd474afd08 Document the --list-supported option. Various small fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 18:04:28 +00:00
Uwe Hermann d84d9ba445 Minor documentation improvements/fixes in the README and manpage (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 17:48:51 +00:00
Stefan Reinauer 7223ab7c4a rename linuxbios_* files in utils repository.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 16:17:44 +00:00
Stefan Reinauer ca374d455c rename linuxbios_* files, too.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 16:16:45 +00:00
Stefan Reinauer 997afe6ca5 util/ renames
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:34:24 +00:00
Stefan Reinauer f527e70333 rename linuxbios -> coreboot
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:33:49 +00:00
Stefan Reinauer 8df401db3b for some reasons the externals did not get committed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:33:10 +00:00
Stefan Reinauer f8ee1806ac Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:08:58 +00:00
Stefan Reinauer 7e61e45402 Please bear with me - another rename checkin. This qualifies as trivial, no
code is changed.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 10:35:56 +00:00
Stefan Reinauer c72fcde273 rename linuxbios to coreboot
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-16 16:25:13 +00:00
Robinson P. Tryon 552cfb7b74 Add new --list-supported switch for printing the list of Super I/Os
supported by superiotool (closes #91).

Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-15 22:30:55 +00:00
Rudolf Marek 6211ae13c3 Fix the documentation of GPIO setup, tell W83627EHF to use external
suspend clock (undocumented in datasheet, documented in 'W83627HG-AW').
Introduce sio_init function for all this.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-12 22:29:17 +00:00
Corey Osgood aeea7c1438 Via C3 datasheets don't make any mention of microcode updates, and the
C7 bios programmer's guide explicitly states they're not necessary, and
leaves it at that. Even if they are possible and exist, we don't have
any info on it, nor any updates, so drop these unneeded references.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-12 21:44:57 +00:00
Ronald G. Minnich c02d8d88dc Fix these to use a more standard relative path for payload.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-11 22:37:27 +00:00
Ronald G. Minnich 23b00b8909 Add the ability to extend CFLAGS as needed for several new distros
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-11 18:23:47 +00:00
Bernhard Walle 6322baa50c This patch removes '\n' from the help output since this looks a bit strange.
After the patch [...] The line length is still below 80 characters.

Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Torsten Duwe <duwe@lst.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-11 00:32:07 +00:00
Carl-Daniel Hailfinger ed8dc58efa Add a workaround for a bug in some binutils version which strictly
interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-10 17:59:25 +00:00
Carl-Daniel Hailfinger 1923fc41be This patch introduces 4k CAR size granularity for the AMD x86 CAR code.
For the old supported CAR sizes, the newly generated code is
equivalent, so it should be a no-brainer.

Benefits:
* a nice code size reduction
* less #ifdef clutter for Family 10h
* paranoid checks for CAR size
* clear abstractions

This has been tested by Marc Jones and Jordan Crouse.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-10 17:48:25 +00:00