Commit Graph

27963 Commits

Author SHA1 Message Date
Elyes HAOUAS d4cb736c31 crossgcc: Update LLVM to 7.0.1
Change-Id: I7d88f0c36a254d8b2e3e76f632f46f0d2a4ad6f8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05 14:41:30 +00:00
Shaleen Jain 2822d66238 util/inteltool: fix PCR init of Sunrise Point-LP devices
Fixes getting a dump of GPIO registers for these devices.

Change-Id: I80f05a170152969ba45d6aee33ab7ed5296ee496
Signed-off-by: Shaleen Jain <shaleen@jain.sh>
Reviewed-on: https://review.coreboot.org/c/30604
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-05 11:15:04 +00:00
Elyes HAOUAS 71a743e961 crossgcc: Update acpica and Expat versions
Update:
 * acpica to version 20181213
   changes in this version: https://acpica.org/node/163
 * Expat to version 2.2.6
   changes in this version:
   https://github.com/libexpat/libexpat/blob/R_2_2_6/expat/Changes

Change-Id: Ib67cf26497a0c2c2a364741675b13e4ce0190e41
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-04 22:04:31 +00:00
Kyösti Mälkki de7f0736a1 mb/*/chromeos.c: Fix PRE_RAM and unify style
Change-Id: I99b9c0452ed0e6d580edb5a4f3317d776085b382
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30399
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 21:23:21 +00:00
Kyösti Mälkki 1de326460e mb/google/jecht: Rename save_chromeos_gpios function
We have init_bootmode_straps() defined for the same purpose.

Change-Id: Ia2692d8f8986247ea4ce889d6252d3c4c8b27bc4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30398
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 21:22:55 +00:00
Kyösti Mälkki 4ad7f5b1a4 AGESA: Use pcidev_on_root()
We have constant CONFIG_CBB==0, replace ill dev_find_slot()
with safe pcidev_on_root();

Change-Id: Ieb2030fa3d77a9f49fc5faf12b92b5f00f49d354
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26482
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 21:22:04 +00:00
Kyösti Mälkki 33ff44c37c binaryPI: Use pcidev_on_root()
We have constant CONFIG_CBB==0, replace ill dev_find_slot()
with safe pcidev_on_root();

Change-Id: If536adf11aacef8faa3455692285552f97531df9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 21:21:42 +00:00
Patrick Rudolph 153ff207ad soc/intel/fsp_broadwell_de: Use BLOBs for microcode updates
Add possibility to update microcode from BLOBs repo.
No need to copy headers around which have an unclear license.

Tested on wedge100s:
* Microcodes are included into FIT.
* Still boots to Linux.
* 3rdparty/blobs at dd00ad1260ef1dc0ba8c55c06ab10c7639dc3eb1

Change-Id: I8ecfb7302a7fc847a51934942f6d323a4f96abba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-01-04 21:17:07 +00:00
Kyösti Mälkki 8803b21bbb amdfam10 boards: Use defaults for get_pci1234()
Note that while these boards had entry 0x0ff0 in comparison
to 0x0ffc of the get_default_pci1234() initialisation, the
implementation of get_pci1234() unconditionally overrides
the first entry.

Change-Id: I8bec612f84fe3c3a0c21fc1e10629368857e9c5e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:24:23 +00:00
Kyösti Mälkki f112f9f912 amdfam10 boards: Use defaults for get_pci1234()
All these boards use the same default initialiser.

As this is initialized late after device enumeration,
it can't really be used to alter platform configuration.

Change-Id: I30fc0298081df0442ec4e9a527340b93a3cd6106
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:23:56 +00:00
Kyösti Mälkki ee7e1300f4 amdfam10 boards: Drop array bus_sb700
Only bus_sb700[0] is evaluated.

Change-Id: Ie2cbbdebed3ae03da916d02919cd6a5d36f53562
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:23:44 +00:00
Kyösti Mälkki bf2d227135 amdfam10 boards: Drop array bus_sb800
Only bus_sb800[0] is evaluated.

Change-Id: I8ae0e6facbbe302b71692cf98a0292ee7d3bdca1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:23:31 +00:00
Kyösti Mälkki b30e2bfe34 amdfam10 boards: Drop array bus_sp5100
Only bus_sp5100[0] is evaluated.

Change-Id: I42a5040ea70a84fb674f2c616c6eba7b23dcdc29
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:23:17 +00:00
Kyösti Mälkki 21c60fa2b2 amdfam10 boards: Add temporary pirq_router_bus variable
It's expected that further analysis shows this to
always evaluate to 0.

Change-Id: I68599b961ca3b5e3652539c5d825a00444958d1b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:23:04 +00:00
Kyösti Mälkki 6bc6c5548e amdfam10 boards: Use PCI_DEVFN()
Change-Id: I301ed4024f1dd6fb2009d59b2992830d4f17ee2f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:22:49 +00:00
Kyösti Mälkki 651f4d231c amdfam10 boards: Drop array bus_sr5650
Values in the array are not used anywhere.

Change-Id: Iee92f903db97533709d54d1f214f2f23a1fab06b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:22:33 +00:00
Kyösti Mälkki af9e459d12 amdfam10 boards: Drop array bus_rs780
Values in the array are not used anywhere.

Change-Id: I608b8c2e21bc515c56a27982815c1da43f3bb976
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:22:04 +00:00
Kyösti Mälkki 228746b346 amdfam10 boards: Drop const variable sbdn_sp5100
Change-Id: I8756a81324ba3d4374bb6b06f7f0ddade6ba530f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:21:50 +00:00
Kyösti Mälkki af39e0ebc1 amdfam10 boards: Drop variable sbdn_sr5650
It mirrors value of sysconf.sbdn.

Change-Id: I3ea42280a1bdceffebb6b5c85aee18347734ee4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:21:38 +00:00
Kyösti Mälkki c9394017db amdfam10 boards: Drop extern on bus_sr5650 and sbdn_sr5650
Change-Id: I3b95ec5746077b49cd6dca64d0f884a3d1c362fb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:21:22 +00:00
Kyösti Mälkki 58954d2bf3 amdfam10 boards: Drop variable sbdn_rs780
It mirrors value of sysconf.sbdn.

Change-Id: I3cb611f1ea33da19e63523bc0fe99f2792eebc57
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:21:05 +00:00
Kyösti Mälkki 8052fe459c amdfam10 boards: Drop const variables sbdn_sb800 and sbdn_sb700
They evaluate to const zero and obscure PCI_DEVFN() use.

Change-Id: I8bd8dced62094d5ee8e957241ac29ead054f5c05
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:20:51 +00:00
Kyösti Mälkki 0571afe5d2 amdfam10 boards: Drop extern on bus_rs780 and sbdn_rs780
Change-Id: I7dc943f3376e9b706d3d486231525df85f806858
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:20:38 +00:00
Kyösti Mälkki c0b1be0ba1 amdfam10 boards: Call get_bus_conf() just once
It has to be called once before PIRQ and MP table generation.

Change-Id: I238c6b4810404d320b36d4f6b4a161c1ff11c8d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:20:24 +00:00
Kyösti Mälkki a2cfe9e900 amdfam10 boards: Add Makefiles and fix resourcemap.c
Also remove global ramstage-y += get_bus_conf.c, this is
specific to amdfam10.

Change-Id: I49b604ebff6bcfe85518b2c3896ab798c3c7878d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:20:08 +00:00
Kyösti Mälkki d482c7dace amdfam10 boards: Drop global bus_isa variable
Value of the global is never evaluated.

Change-Id: I74106b0f5f033053288882a5bcd3c1dba3235ac0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:19:48 +00:00
Kyösti Mälkki 1db4e3a358 amdfam10 boards: Declare get_pci1234() just once
Change-Id: I68bb9c4301c846fe2270cd7c434f35a79ab25572
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:19:34 +00:00
Kyösti Mälkki a79b3f1c63 amdfam10 boards: Drop unused mb_sysconf.h
Change-Id: I819cfcda55995237a8431fdb3291274ab968cd3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:19:16 +00:00
Kyösti Mälkki 9e7ac6b034 amdfam10 boards: Drop AMD_SB_CIMX
Copy-paste, boards do not set this.

Change-Id: I4c0795a483948b1e357388a5ad639c3f1950bbc8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:18:57 +00:00
Kyösti Mälkki 031dc67a61 util/superiotool: Add ITE IT8786E-I
Based on IT8786E-I V0.4.1 datasheet with following remark:

  "Please note that the IT8786E-I V0.4.1 is
   applicable only to the D version."

Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibf6e290abb01ae1b6b28173a83e88d1d99663ad4
Reviewed-on: https://review.coreboot.org/c/30334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-04 15:07:19 +00:00
Patrick Georgi 109b8589ca Documentation: Update 4.9 release notes
Change-Id: Ib1057541dc0decd98921f3c84de3c08f10cd802e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30344
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 13:12:42 +00:00
Angel Pons 782341dd3a util/autoport/readme.md: Correct minor inconsistency
Commit a5072af67d ("util/autoport: Use romstage.c instead of
early_southbridge.c") changed where the SPD map is. Reflect that.

Change-Id: Id0bd1778617371bac5921c4eae63d0beb088216c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30655
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 13:12:00 +00:00
Kyösti Mälkki 98a917443e device: Replace ugly cases of dev_find_slot()
These few cases lacked a proper devfn parameter in the
form of PCI_DEVFN(dev, fn).

Change-Id: Iad0b214df12dee65360d07e887a960b0c73a3e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-01-04 12:17:52 +00:00
Kyösti Mälkki ad7674ed00 device: Introduce pcidev_on_root() and friends
Semantics of dev_find_slot() are ill in the sense that
it only works after device enumeration has completed in
ramstage. Plan is to declare it as deprecated.

Introduce pcidev_on_root() and pcidev_path_on_root()
functions to replace cases where this was called with
static argument bus == 0. New implementation only walks
the root bus of the PCI tree, while old one walked
the entire linked list of devices.

Introduce pcidev_path_behind() to replace cases where
argument bus != 0. The required parent node is typically
one of the PCIe root functions that you locate using
pcidev_on_root() above.

New forms are safe to use with early devicetree and
before PCI bus numbers have been assigned.

Change-Id: Ie20598d48b4cf6e35e45fc90804bad4728437fc6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-01-04 12:14:42 +00:00
Elyes HAOUAS e3682b6c1c src: Move {pci,pnp}_devfn_t to common 'device/pci_type.h'
Definitions of these types are arch-agnostic. Shared device
subsystem files cannot include arch/pci_ops.h for ARM
and arch/io.h for x86.

Change-Id: I6a3deea676308e2dc703b5e06558b05235191044
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-04 12:13:20 +00:00
Elyes HAOUAS f9e47cc4c2 src: Get rid of device_t
Use of device_t is deprecated.

Change-Id: Ie05869901ac33d7089e21110f46c1241f7ee731f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30047
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 12:11:18 +00:00
Edward O'Callaghan 4139c15276 util/gitconfig/pre-commit: Use clang-format to sanitise commits
Use the `git-format' tool to sanitise coreboot commits such that
they conform to coreboot's coding style.

This fancy piece of machinary allows one to have LibFormat from
Clang to automatically check your commit conforms to coreboot's
coding style, fix any issues automatically and provides you a
diff you may review and apply at your convenience.

N.B. When the `clang-format' binary is not found we issue a warning
that the test was skipped and carry on as usual. Hence, this is
strictly non-enforcing at this current time. You may use it at your
leisure.

Change-Id: If49017ea82f0707efd47cae5978a286a9af8f3b7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/c/8037
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 10:37:10 +00:00
Stefan Reinauer d1584fb250 crossgcc: Update acpica to 20180927
Update to latest version of iasl:

(From the acpica.org changelogs)
* Fixed a regression introduced in version 20180927 that could cause the
  compiler to fault, especially with NamePaths containing one or more
  carats (^). Such as: ^^_SB_PCI0

* Added a new remark for the Sleep() operator when the sleep time
  operand is larger than one second. This is a very long time for the
  ASL/BIOS code and may not be what was intended by the ASL writer.

* Implemented detection of extraneous/redundant uses of the Offset()
  operator within a Field Unit list. A remark is now issued for these.
  For example, the first two of the Offset() operators below are
  extraneous. Because both the compiler and the interpreter track the
  offsets automatically, these Offsets simply refer to the current
  offset and are unnecessary. Note, when optimization is enabled, the
  iASL compiler will in fact remove the redundant Offset operators and
  will not emit any AML code for them.

Change-Id: I46a1b1be44328aa2172f4741e9fd0c9b0f4e0430
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28944
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 10:28:46 +00:00
Stefan Reinauer aedb1dfbbb crossgcc: Update software versions
Update toolchain to the following software versions:

 o Python 3.5.1 -> 3.7.0
 o LLVM   6.0.0 -> 7.0.0
 o Expat  2.2.1 -> 2.2.5
 o MPC    1.0.3 -> 1.1.0
 o MPFR   3.1.5 -> 4.0.1

Change-Id: I66c6138c7b65c73a89b3cf980bb08950d8fffe6a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28887
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 10:28:00 +00:00
Kyösti Mälkki c859f10eec intel/e7505: Drop ECC scrubber code
This was already disabled and mostly incompatible
with romstage having stack in CAR.

Change-Id: I1fe02bef668a5bc8ce3d5a1d8090670752b10c3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-04 04:50:40 +00:00
Lijian Zhao 768cd37bc3 mb/google/sarien: Add settings for noise mitgation
Enable acoustic noise mitgation for sarien platform, the slow slew rates
are fast time dived by 8.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I5d38a1e03af08f106e2422a319b34c3fb54bdf28
Reviewed-on: https://review.coreboot.org/c/30448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-04 01:15:00 +00:00
Arthur Heymans dff185a28d sb/intel/*: Use common files for PCIe ACPI
The result is that i82801{g,i,j}x now use the correct _PRT table for
their root port number.

Change-Id: I92bba3c669f3e6a44a42e19a88a33dfcfc2b9b42
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-03 22:33:29 +00:00
Arthur Heymans cd36634994 sb/intel/bd82x6x: Move pcie ACPI code to a common place
Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-03 22:32:50 +00:00
Frank Wu d0cc3bc5ce mb/google/poppy/variants/nami: Add sku_ids for Pantheon
Sync'ing the sku_ids list in the master sku sheet for Pantheon.

BUG=b:121207221
BRANCH=firmware-nami-10775.B
TEST=emerge-nami coreboot chromeos-bootimage

Change-Id: Ic03c3a6fe238f2692ce15c45016115087380c0ca
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-01-03 22:24:51 +00:00
Junzhi Zhao 66ee65f036 google/kukui: Initialize DRAM from romstage
Add DRAM support for google kukui.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I1ed01404343745c883b22a648966327bdcabc5c2
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-03 22:23:10 +00:00
Huayang Duan 4d15d2fc12 mediatek/mt8183: Add DDR driver of memory test part
Write a range of memory with special pattern, and read it back to check
whether the read value same as write.
The test pattern include 8bit offset read write, 16 bit offset read
write, 32bit offset read write, and cross testing.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
     patches.

Change-Id: I30d5fbd3db2acf36e3058ba4f34558b981fba78c
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28845
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03 22:22:58 +00:00
Huayang Duan 7b78a805da mediatek/mt8183: Add DDR driver of runtime config part
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
     patches.

Change-Id: Id1e8862ff6feb9628d37fe5300780ff56865a563
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-03 22:22:48 +00:00
Huayang Duan 6202d1b51a mediatek/mt8183: Add DDR driver of rx datlat calibration part
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
     patches.

Change-Id: Ia20de54633bf1077bd469df75ccb4390308e0b97
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28843
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03 22:22:36 +00:00
Elyes HAOUAS 0afc41e865 nb/amd/pi/00{630F01,730F01}: Use ARRAY_SIZE
Use already defined ARRAY_SIZE macro.

Change-Id: Ie22e3557e958b562816921a985411dd55c712142
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-03 21:55:59 +00:00
Elyes HAOUAS 66b462dd4f nb/intel/pineview/raminit.c: Remove unused variable
Change-Id: I1e0009677fda44faab2021e1c44827fdba803061
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-03 21:55:41 +00:00