Use the broadcast ID to deliver LINT1 as NMI to all CPUs,
instead of listing individual LAPIC IDs.
Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch provides helper functions to read or write a register via the
MDIO bus. They can be used from drivers to easily access registers on
the MDIO bus.
Change-Id: I293d93435d27269a071b4b9b94a1b55307c575a7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69611
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch extends the available device paths with a new device 'mdio'.
MDIO is the 'Management Data Input/Output' called interface which is
used to access an Ethernet PHY behind a MAC to change settings. The real
payload data path is not handled by this interface.
To address the PHY correctly on the MDIO bus, there is a 5 bit address
needed, which often can be configured via pins on the mainboard.
Therefore, the new introduced device has an 'addr' field to define its
address. If one wants to use a MDIO device in devicetree, the syntax is
straight forward (example):
device mdio 0x2 on end
As the MDIO interface is driven by the MAC, most likely this MDIO device
will be hooked in as a child device of the (PCI attached) MAC device.
With the new introduced ops_mdio a new interface is added to provide an
API for read and write access over MDIO.
Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69382
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves a lot of post code values, but unifies them between
platforms, so that the same value means the same thing as much as
possible.
The P4-netburst code was the most extensive and most different, so that
dictated the majority of the values. Three were two values there that
didn't match the other files, so those two values, 0x22 & 0x29 have
duplicate entries in the table.
The rest of the entries are similar between platforms, though the values
for many of them were moved to match the P4-netburst values.
POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become
global, while POST_SOC would be specific to the Intel platforms.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69866
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE is nowadays defined in
vboot/firmware/2lib/include/2constants.h, so update the comment.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7c9a5476ae06d4bac762da1729aff878b7d0965
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add pcie_find_dsn() to detect and match PCIe device serial
number. In addition, vendor ID is matched when provided.
Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add initial CEDT (CXL Early Discovery Table) support based on
CXL spec 2.0 section 9.14.1.
Add functions to create CEDT table (revision 1), and create CEDT
CXL Host Bridge Structure (CHBS) and CXL Fixed Memory Windows
Structure (CFMWS).
TESTED=Create CEDT table on Intel Archer City CRB, dumped the
CEDT table and examined the content.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Read FRU product info of PSU to get Type 39 required information.
Further development needed if multi-record info of PSU FRU is required.
For now, the read_fru_areas() only read product chassis and board info.
Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com>
Signed-off-by: ziang <ziang.wang@intel.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I18d056cba1a79b0775c8a42b3a879e819887adca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuming Chu (Shuming) <s1218944@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
The dimm_info structure (defined in src/include/memory_info.h)
currently does not hold information about the DIMM's
node/controller ID.
This patch extends the dimm_info structure by adding a new field for
the node ID, called node_num. Also, adapt the dimm_info_fill()
function accordingly to populate the newly-added field.
Background: These changes are necessary for the Atlas mainboard, where
we are currently experiencing issues with the DIMMs device/bank
locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a
distinct NODE ID. By looking at the smbios table we see
Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order
to distinguish them.
This patch was tested by building and booting for the Alderlake-P
RVP board, which has the same DIMM slot configuration as the
Prodrive Atlas mainboard.
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add definitions for Link Capability and Slot Capability and these
definitions may be used in smbios type 9.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Id66710d5569a7247d998cab20c2e41f2e67712cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This makes it easier to get the content of an msr into a full 64bit
variable.
Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68572
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add definition for smbios type 4 and type 9
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I559995b0204f8e5bdeef2c0f8b394f9011d72240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The deadlock prevention is also needed with CONFIG_X2APIC_RUNTIME when
the cpu is in x2apic mode.
TESTED: Fixes SMI generation on xeon_sp hardware with
CONFIG_X2APIC_RUNTIME.
Change-Id: I6a71204fcff35e11613fc8363ce061b348e73496
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit factors out `struct xhci_usb_info` from intel specific code
as it will be useful on other platforms.
BUG=b:186792595
TEST=Builds for volteer
Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit factors out some code for XHCI port status values.
BUG=b:186792595
TEST=Built coreboot for volteer device
Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These symbols and codepaths are unused now so drop them.
Change-Id: I7c46c36390f116f8f8920c06e539075e60c7118c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69361
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces support signing and verification of firmware
slots using CBFS metadata hash verification method for faster initial
verification. To have complete verification, CBFS_VERIFICATION should
also be enabled, as metadata hash covers only files metadata, not their
contents.
This patch also adapts mainboards and SoCs to new vboot reset
requirements.
TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=none
TEST=Able to build and boot Google, Rex SKU2 (Micron LPDDR5x
MT62F1G32D2DS-026).
Without this code change:
[INFO ] SPD: module type is UNKNOWN
With this code change:
[INFO ] SPD: module type is LPDDR5X
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If620cf51133ca295fd3f1cbecbb472beb337b9fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69226
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of having callbacks into serial console code to set up the
coreboot table have the coreboot table code call IP specific code to get
serial information. This makes it easier to reuse the information as the
return value can be used in a different context (e.g. when filling in a
FDT).
This also removes boilerplate code to set up lb_console entries by
setting entry based on the type in struct lb_uart.
Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* Add DPC related definitions which are defined in 7.9.14 of PCIe
6.0 spec.
* Add AER related definitions which are defined in 7.8.4 of PCIe
6.0 spec.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifb6722c326ef69ef1bf3b1c2c1d5bc0cb29d7c12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69106
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This pragma says to IWYU (Include What You Use) that the current file
is supposed to provide commented headers.
Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
It will be used in a follow-up change.
Change-Id: If89f9569c33949995d3b45a5f871ff2cb84a6610
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Acpigen inline helper functions are causing problems while compiling
coreboot with function instrumentation. Sometimes functions are not
inlined and are causing linking errors. Forcing inlining fixes problems
like that, as these functions would normally be inlined anyway.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ibf747573940fe5e76199f327f4e5bc32b4f8c470
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Add system agent ID for RPL QDF# Q271
TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is
gone
Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com>
Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add a post-code call that SoCs can hook to output or save in any way
that is specific to that SoC.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
To allow testing of code that uses msr calls, separate the actual
calls into a separate header file, This allows the tests to emulate
the msr access without replacing the rest of the msr.h definitions.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I102709fec346f18040baf9f2ce6e6d7eb094682d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit 672bd9bee5.
Reason for revert: Gmeet resolution dropped. When system starts
Gmeet video call, it uses the hardware accelerated encoder as per
the expectation. But, as soon as another system connects to the call,
the immediate fallback observed from hardware to software encoder.
Due to this, Gmeet resolution dropped from 720p to 180p.
Currently, this issue observed on AlderLake-N SoC based fanless
platforms. This issue is not seen on fan based systems.
BUG=b:246535768,b:235254828
BRANCH=None
TEST=Built and tested on Alderlake-N systems. With this revert
Gmeet resolution drop not observed.
Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Some platform run early stages like romstage and verstage from CAR
instead of XIP. This allows to link them like other arch inside the
_program region. This make in place LZ4 decompression possible as it
needs a bit of extra place to extract the code which is now provided by
the .bss.
Tested on up/squared (Intel APL).
Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
BRANCH=none
BUG=b:234776154
TEST=build and boot Nirwen UFS, copy ISH firmware to host
file system /lib/firmware/intel/adln_ish.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adlnrvp_ish.bin loaded
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I89782b0b7dde1fca0130472a38628e72dfd5c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Based on DMTF SMBIOS Specification 3.5.0
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Change-Id: I710124ca88dac9edb68aab98cf5950aa16c695d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67926
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
add functions to check whether a device is enabled pci
device or a pci device on a specific bus number.
TEST: compile and qemu run successfully
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: I3257c8404017372f6cdd9f6cf9453502447343a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68101
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel Core i5-10210U can have the following IGD Device IDs
0x9B21/0x9B41/0x9BAC/0x9BCA/0x9BCC according to Intel ARK. Some of
these IDs were not present in coreboot source nor hooked to the
common graphics driver. Add the missing IDs so that the graphics
driver will probe on the mentioned processor and detect the
framebuffer.
TEST=Boot Protectli VP4650 with i5-10210U and see framebuffer is
detected when using FSP GOP and libgfxinit.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iee720a272367aead31c8c8fa712bade1b6e53948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67975
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on DMTF SMBIOS Specification 3.1.0.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia2db29f8bc4cfbc6648bb2cabad074d9ea583ca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Add function defs and prototypes of functions checking whether
a device is {a cpu,an enabled cpu}
TEST: compile test and qemu executed successfully with
coreinfo payload
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: Iabc0e59d604ae4572921518a8dad47dc3d149f81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Kyösti Mälkki