Commit Graph

35911 Commits

Author SHA1 Message Date
Angel Pons e8393bd482 mb/asrock/b85m_pro4: Drop spurious LPC decode ranges
Only one generic decode range is needed for the HWM.

Change-Id: I964a073efbfaa1d79d3483d59ad04fe674bcb275
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42131
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:30:06 +00:00
Angel Pons 6c82012e5e mb/asus/p8z77-v_lx2: Correct Super I/O GPIO settings
Compared against superiotool dumps with vendor firmware. Still boots.

Change-Id: I49f36b2805e36695d7a53865e87dfafdb897594e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42482
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:29:26 +00:00
Angel Pons 279ace6669 mb/intel/baskingridge: Put GPIOs in a C file
This will allow dropping the pointer inside romstage_params.

Change-Id: I04b695cbe2a6485b42ab037f4f7359a2429c3440
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08 22:27:01 +00:00
Angel Pons 725657aa4c sb/intel/lynxpoint: Program PM registers directly
Perform the same operations as the RCBA reg script did, but directly
writing the corresponding registers. Some of these operations could be
simplified, but it is not done on this commit to ease verification.

Change-Id: I4c3177ab14ca9bfa2e8d11c27fb249850183eee5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08 22:26:15 +00:00
Angel Pons b4f9833028 sb/intel/lynxpoint: Factor out RCBA Function Disable
Comments stating that this was mainboard-specific were very wrong.

Change-Id: I7026ca9c7dabd01b4a0c0549b697e006d5f75eb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-08 22:18:56 +00:00
Angel Pons 55d148ca37 sb/intel/lynxpoint: Replace reg script with proper code
Why use a Rube Goldberg machine to write and then read one register?

Change-Id: I282c12f162b5ae69c40729903c09ae81a14c9761
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-08 22:18:20 +00:00
Angel Pons 2e25ac6afe haswell: relocate `romstage_common` to northbridge
Other platforms do this as well. It will ease refactoring on follow-ups.

Change-Id: I643982a58c6f5370c78acef93740f27df001a06d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08 22:16:58 +00:00
Angel Pons 284a54775b nb/intel/haswell: Drop unnecessary variable
The "normalized" boot mode is only used in a single place, so there's no
need to use a variable. Also, reword the associated comment, which seems
to be unnecessarily vague: the hardcoded assumptions are inside the MRC.

Change-Id: I260d10f231f5de765d2675416d7047717d391d8f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08 22:16:31 +00:00
Angel Pons e816829e7a haswell: drop unused function parameter
The `chipset_type` parameter is ignored.

Change-Id: Ia3d217178cc9caabf232b3a59f505229cc03135f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08 22:16:15 +00:00
Angel Pons 8d3bc49876 mb/google/slippy: Factor out common romstage settings
There's no need to repeat the same values over four variants.

Change-Id: Ifc4a9961fe9c87f15a6039e6e478682fab5b0bb7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08 22:15:54 +00:00
Angel Pons e12de372d7 sb/intel: Factor out irqlinks.asl
Files are identical for all southbridges, except bd82x6x. We will take
care of that in subsequent commits.

Change-Id: I38e5d440e188d26f8997bc22a956187b728487ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43157
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:12:44 +00:00
Angel Pons b6427b0b18 sb/intel: Factor out ICH ACPI for HDA
Files are identical between all three southbridges, and differ for PCH.

Change-Id: Ic6a926af675bda3db3a5795df9e8f490caf3ebf4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43156
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:12:16 +00:00
Angel Pons ba045653dc sb/intel/i82801{gx,ix,jx}/acpi: Align cosmetics
This reduces the differences between ACPI for these three southbridges.

Change-Id: If49bad776ebc98cab439f8ea6942471520c476a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43155
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:11:31 +00:00
Angel Pons 9511ce7d7f sb/intel/i82801gx: Remove nic.c driver
It does nothing special, so why have it in the first place?

Change-Id: I27aff0ed67e9c69ab78050d35b49f6e26924d31a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43174
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:10:33 +00:00
Angel Pons 5f201ef866 nb/intel/pineview/acpi: Remove unmatched comment start
This was silently commenting out the line after it.

Change-Id: I2714090b8f99193ace420ad02e2d42b324349c9e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-08 22:10:21 +00:00
Angel Pons bfc80098da nb/intel/pineview: Convert to ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: Ibc0988c4c86f7ffef8692ff3cf3ebd92235156b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43168
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:09:56 +00:00
Angel Pons 4d962b2ecf nb/intel/pineview: Tidy up comments and cosmetics
Remove some unneeded newlines, add some commas for consistency and
relocate comments to match the code.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I0ac18a692bf613c75083c4aa1860e0a9f07e68d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-08 22:09:34 +00:00
Angel Pons f67bf49ead nb/intel/i945: Use ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: Ibf6904246ee47dffdb5fa2e24cc7a230f439c7e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43178
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:08:37 +00:00
Angel Pons 837141fa56 nb/intel/i945/acpi: Tidy up comments and cosmetics
Use C-style comments, drop unneeded newlines, add missing commas for
consistency and relocate a comment to match the code.

Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: I37fffb60944c35dfb5e0491bb023babfcf2c6a73
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43177
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:08:27 +00:00
Angel Pons 29cd350c46 nb/intel/gm45: Use ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: Ibb9b627de85eb09bdc977af55880366e4e49f3ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-08 22:07:38 +00:00
Angel Pons d85d7e2329 nb/intel/gm45: Tidy up comments and cosmetics
Use C-style comments, drop an unneeded newline, add missing commas for
consistency and relocate a comment to match the code.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I3f91d1b57eb5530c8adcf5f682e73747435f0d47
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43172
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 22:07:27 +00:00
Angel Pons 7c71f7d15b nb/intel/x4x/acpi: Use ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: I089f14dce6e3fdebcfdee126a2023ef028a01805
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-08 22:07:10 +00:00
Angel Pons 0b5673dd33 nb/intel/x4x/acpi: Clean up comments
Use C-style comments. Also drop some unnecessary newlines.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: Icd33a326cc7d9ead765e2b32e7dea237bd76fd4f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-08 22:06:48 +00:00
Martin Roth 6e5f909830 soc/amd/picasso: Update APOB size & base generation
Make the APOB size & base generation the same as all the other command
line arguments to amdfwtool.

BUG=None
TEST=Build & boot trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id78383d87bc98dd2c859c75585266411c226f950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 21:07:00 +00:00
Martin Roth 00b37d3007 arch/x86: Add memmove.c to x86 bootblock
This was specifically needed for vboot with psp_verstage, but adding
it to always be built into bootblock if needed like memcpy & memset
makes sense.

TEST=Build & boot trembyle
BUG=None

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 21:06:47 +00:00
Martin Roth c35d4fa377 mb/google/zork: Enable psp_verstage
Finally enable psp_verstage for zork.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 21:06:34 +00:00
Martin Roth f38af663d2 src/amd/common: Exclude biosram from psp_verstage
This isn't needed for psp_verstage, and causes build failures if
included.

BUG=b:158124527
TEST=Build & boot Trembyle with psp_verstage

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I63942ad896d205c327d65bb8083da817b972962b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42808
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 21:02:31 +00:00
Martin Roth 95d05e43b1 soc/amd/picasso: Halt if workbuf is absent after psp_verstage
Check for the workbuf in bootblock if psp_verstage is being used.

BUG=b:158124527
TEST=Build & boot Trembyle with psp_verstage

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0ec8d2c953bce4c44cde5102d2765e0ab9b5875e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42810
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 20:46:05 +00:00
Martin Roth 137f86149e soc/amd/common: Don't init SMIs or SCIs in psp_verstage
We can't set the SMI or SCI flags in psp verstage, so skip them.

TEST=Build
BUG=b:154142138

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42765
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 20:42:07 +00:00
Martin Roth d09b9747e7 lib: Temporarily remove timestamps from psp_verstage
The timestamp functionality is not yet added for psp_verstage, so
temporarily remove it until that's completed.  That work is being
tracked by bug 154142138.

BUG=b:154142138
TEST=Build & Boot psp_verstage on trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I020619e3615ce92dedbe868104d2bfd83cb7caa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42381
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 19:37:50 +00:00
Martin Roth 9aa8d11885 soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regions
The AMD firmware package created by amdfwtool contains pointers to the
various binaries and settings.  When these are moved to the RW-A & RW-B
regions, the packages need to be recreated for the new addresses.

TEST=Build & boot trembyle. See that we're booting from the correct
region.
BUG=b:158124527

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 19:37:11 +00:00
Martin Roth 6303671189 security/vboot: Allow files to go into only RW-A or RW-B region
The AMD firmware package created by amdfwtool contains pointers to the
various binaries and settings.  This means that we need different copies
of the package in each region.
This change allows for the different files in each of the 3 vboot
regions.

BUG=b:158124527
TEST=Build trembyle; see the correct versions of the files getting
built into the RW-A & RW-B regions.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45ff69dbc2266a67e05597bbe721fbf95cf41777
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 19:36:24 +00:00
Martin Roth 362eaf3f4c soc/amd/picasso:Add psp_verstage components to amdfw binary
This adds the psp_verstage userspace application and the location of
the shared memory area to the amdfw binary tables.

BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45309b5998e6e442ff37cf1d2adb8ccfa1b6a619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
2020-07-08 19:35:27 +00:00
Martin Roth c7acf1666a soc/amd/picasso: add psp_verstage
This is the main code for building coreboot's verstage as a userspace
application to run on the PSP.  It does a minimal setup of hardware,
then runs verstage_main.  It uses hardware hashing to increase the speed
and will directly reboot into recovery mode if there are any failures.

BUG=b:158124527
TEST=Build & boot trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 19:34:59 +00:00
Martin Roth ac41f58235 soc/amd/picasso: Allow modification of i2c base addresses in PSP
BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45380e0c61e1bb7a94a96630e5867b7ffca0909c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42064
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 19:34:44 +00:00
Maulik V Vaghela ab70d0ff66 mb/google/waddledee: Enable Audio
1. Enable HDA Pci device in devicetree
2. Enable I2C4 in devicetree and fill ACPI information
3. Pass correct IRQ GPIO for headset jack

BUG=None
BRANCH=None
TEST=Audio playback and recording works on Waddledee.

Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41765
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 18:46:39 +00:00
Patrick Georgi b351875f1e build system: Rely on xcompile for HOSTCC and HOSTCXX
It already looks for them, so let's use the result instead
of blindly defaulting to gcc/g++, except when not building an image
(but run kconfig or tests) because we don't use xcompile in those cases.

Change-Id: I3e50c70a609f1903a925610928f8779c191040d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-08 08:53:46 +00:00
Patrick Georgi 793bf7e605 util/xcompile: Look for the host compiler in XGCCPATH, too (and first)
If there's a host compiler in XGCCPATH, it's likely the same
relatively-current version we use for coreboot, and it's a well-known
quantity, so let's prefer that over alternatives by default.

In addition, look for the C++ host compiler as well.

Change-Id: If50341df169a476899b5a5ffd4c4fb6d21c3f4ac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43144
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 08:53:41 +00:00
Kyösti Mälkki fca0cba6a1 sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine
The smm_setup_structures() calls placed GNVS address into
register %ebx. Old code on i82801dx used these low memory
addresses.

Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42426
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:33:00 +00:00
Kyösti Mälkki e769bcee9a ACPI: Add and fill gnvs_ptr for smm_runtime
Change-Id: I823d04a4851437b4267a60886e5ab205bb2e1b10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-08 07:32:51 +00:00
Bryant Ou da1fde2ffb mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC
BIC uses LPCflash utility to flash FW, it uses LPC to send the
bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used
to send BIC image for in-band update support.

TEST=Use LPCflash utility to flash BIC FW on YV3 successfully.

[root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin
Update Bridge IC Firmware from LPC

Deltalake linux utility ver:1.01
build time: Feb 11 2020 14:30:55
Processing image file: Y3BRDL_D06.bin
.. of size 206968 (0x00032878) bytes
.. file will be padded to a 64-byte size
.. with DEBUG Enabled
Generating CRC-32 for file.
Done (0x4e3905a3).

iBytesRead (0x00007c00).

Discovering LPC boot loader.
Discovered @ 0x3f8.

Configuring LPC boot loader.
Configured @ 0x00000600.

Sending header block.
Sent.

Loading firmware into target.
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 31744 bytes ...............................
 Sending 16512 bytes .................
Load complete.

Update done!

Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08 07:31:08 +00:00
Wisley Chen 742bccfb5c mb/google/dedede/var/drawcia: add elan touchscreen
BUG=b:155002684
TEST=build drawcia, and check touchscreen can work

Change-Id: Ib6a190d2f6fc5132af0e58c6df9919381e88f699
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-08 07:30:07 +00:00
Patrick Rudolph 03a79520d6 cpu/x86/smm: Add support for long mode
Enable long mode in SMM handler.
x86_32 isn't affected by this change.

As the rsm instruction used to leave SMM doesn't restore MSR registers,
drop back to protected mode after running the smi_handler and restore
IA32_EFER MSR (which enables long mode support) to previous value.

NOTE: This commit does NOT introduce a new security model. It uses the
      same page tables as the remaining firmware does.
      This can be a security risk if someone is able to manipulate the
      page tables stored in ROM at runtime. USE FOR TESTING ONLY!

Tested on Qemu Q35.

Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:28:32 +00:00
Patrick Rudolph d5321bf2fb Documentation: Add TODOs for secure SMM when using x86_64
Change-Id: I157238f18bc1c2eba0adc0b87caa9adaf3fc5d38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 07:27:52 +00:00
Angel Pons 9d69d881e6 nb/intel/haswell/acpi: Update to ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ibcc54c2332945fff28d6502edb7eefa06f764bdd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43152
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:26:25 +00:00
Angel Pons 05f996d433 nb/intel/haswell/acpi: Fix host bridge registers
The host bridge register definitions haven't changed from Sandy Bridge
to Haswell, according to the datasheets. However, coreboot's ACPI code
is not the same. Looks like Haswell values are wrong, so correct them.

Change-Id: Ib099575b5cc5e7d468db51f382a15b8aac3eedea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-08 07:26:07 +00:00
Michael Walle 32b13131c1 libpayload: arm64: silence libpayload main entry
No other architecture in libpayload outputs anything in the main entry
routine. Let alone an exception test which looks like a real exception
to the normal user and is most likely really misleading. Silence the
startup code.

Change-Id: I6e49f24ad46ce578a4bb111c2d623ca4470a1866
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43126
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:25:38 +00:00
Michael Walle 492d55fa46 libpayload: arm64: fix OUTPUT_ARCH()
There is no bfd "arm64". The correct bfdname is "aarch64". Fix it. With
this change libpayload will build with the AArch64 GCC.

Change-Id: If7a6b14691107c5d4fc67c3cd3990ecc849d4af1
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-08 07:25:03 +00:00
Johnny Lin 3d44c9925f mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variables in romstage
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting
the timer countdown value. By default it would start the timer and
trigger hard reset when it's expired. The timer is expected to be
stopped later by payload or OS.

Tested on OCP Delta Lake.

Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08 07:24:22 +00:00
Johnny Lin cef108cc90 mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configs
In romstage get the config from BMC IPMI and update the IIO accordingly.

Tested on OCP Delta Lake with FSP WW24 release, with lspci checking bifurcation
register values are expected.

Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-08 07:24:11 +00:00