Commit Graph

17860 Commits

Author SHA1 Message Date
Andrey Petrov 9c0e180655 Revert "intel/apollolake: Use custom reset calls"
Looks like we need to do real cold reset in some FSP flows, so
reverting this.

This reverts commit 6f762171de.

Change-Id: Ie948d264c4e2572dab26fdb9462905247a168177
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15331
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-24 20:27:08 +02:00
Simon Glass 7865932481 ec/google: Add support for the EC 'get time' function
Some platforms have an RTC provided by the Chrome OS EC. Allow the EC to
implement rtc_get() so that this can be plumbed in.

BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) with future commits, boot on gru and see output:
Date: 1970-01-17 (Saturday)  Time:  1:42:44

Then reboot ~10 seconds later and see output:
Date: 1970-01-17 (Saturday)  Time:  1:42:53

Change-Id: I3b38f23b259837cdd4bd99167961b7bd245683b3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4a4a26da37323c9ac33030c8f1510efae5ac2505
Original-Change-Id: Icaa381d32517dfed8d3b7927495b67a027d5ceea
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/351780
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15302
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24 20:22:52 +02:00
Simon Glass 2cf99e1655 lib: Add real-time-clock functions
Add functions to convert between seconds and a struct rtc_time. Also
add a function that can display the time on the console.

BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) with future commits and after setting RTC on the EC:
boot on gru into linux shell, check firmware log:

localhost ~ # grep Date: /sys/firmware/log
Date: 2016-06-20 (Monday)  Time: 18:01:44

Then reboot ~10 seconds and check again:

localhost ~ # grep Date: /sys/firmware/log
Date: 2016-06-20 (Monday)  Time: 18:01:54

Change-Id: Id148ccb7a18a05865b903307358666ff6c7b4a3d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 3b02dbcd7d9023ce0acabebcf904e70007428d27
Original-Change-Id: I344c385e2e4cb995d3a374025c205f01c38b660d
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/351782
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24 20:22:05 +02:00
Duncan Laurie 9482cf6c09 intel/kunimitsu: Move devices from mainboard.asl to devicetree
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices.  Then remove the static ACPI objects from the DSDT
in mainboard.asl.

This was tesed on a Chell mainboard since I lack a kunitmisu device.
I used different GPIOs across boots to verify that the different
audio codec devices would be "detected" and generated in the SSDT.

Change-Id: I9b3b2247a84aeb7c07780958377d5bea14417ce6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15317
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-24 20:14:23 +02:00
Duncan Laurie a2be7fbff5 google/lars: Move devices from mainboard.asl to devicetree
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices.  Then remove the static ACPI objects from the DSDT
in mainboard.asl.

This was tested on a Chell mainboard since I lack a lars device.

Change-Id: Ifba6fc6589ddd54f4c85e8858f17997fbb4b6176
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15316
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-24 20:11:20 +02:00
Duncan Laurie d6ae2f6edb google/glados: Move devices from mainboard.asl to devicetree
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices.  Then remove the static ACPI objects from the DSDT
in mainboard.asl.

This was verified on a glados board by verifying the SSDT contents
against what used to be in the DSDT.

Change-Id: I710cbb8462d0fe695297102a64bec8e4212acc65
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15315
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-24 20:10:28 +02:00
Duncan Laurie c8ea4c111c google/chell: Move devices from mainboard.asl to devicetree
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices.  Then remove the static ACPI objects from the DSDT
in mainboard.asl.

This was verified by comparing the generated ACPI code in the SSDT
to what was in mainboard.asl and ensuring the contents are
functionally equivalent.

Change-Id: I4725bbe2d47178568e3024fe3bb48cc80ff861c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15314
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24 20:09:31 +02:00
Hannah Williams 8ecd6f849c soc/intel/apollolake: Include _PTS, _WAK and _SWS
Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15138
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-24 19:11:21 +02:00
Benjamin Barenblat 82ef8ada82 src/commonlib/lz4_wrapper: Correct inline asm for unaligned 64-bit copy
Rewrite inline assembly for ARMv7+ to correctly annotate inputs and
outputs.  On ARM GCC 6.1.1, this causes assembly output to change from
the incorrect

	@ r0 is allocated to hold dst and x0
	@ r1 is allocated to hold src and x1
	ldr r0, [r1]		@ clobbers dst!
	ldr r1, [r1, #4]
	str r0, [r0]
	str r1, [r0, #4]

to the correct

	@ r0 is allocated to hold dst
	@ r1 is allocated to hold src and x1
	@ r3 is allocated to hold x0
	ldr r3, [r1]
	ldr r1, [r1, #4]
	str r3, [r0]
	str r1, [r0, #4]

Also modify checkpatch.pl to ignore spaces before opening brackets when
used in inline assembly.

Change-Id: I255995f5e0a7b1a95375258755a93972c51d79b8
Signed-off-by: Benjamin Barenblat <bbaren@google.com>
Reviewed-on: https://review.coreboot.org/15216
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24 19:10:05 +02:00
Elyes HAOUAS c86da67436 arch/x86/smbios: Correct manufacturer ID
Correct standard manufacturer's identification code.

Change-Id: I273711e121a61a91176c15cd4cab75420f1f5a39
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15271
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-24 18:46:56 +02:00
Elyes HAOUAS ed3ccc2cad SPD: Add DRAM devices types
Add SDRAM or module types to byte 2.

Change-Id: Id6e654a3a714c164bc9a7fbd9ab3e2f3c44ca5ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15265
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24 18:24:27 +02:00
Elyes HAOUAS aa8e7e7776 SPD: fix DDR3 SDRAM memory module types
Correct the definitions for 16b and 32b SO-DIMM modules.
Regarding JEDEC Standard No. 21-C
Annex K: Serial Presence Detect for DDR3 SDRAM Modules (2014),
the hex values used for 16b-SO-DIMM is 0x0c
and for 32b-SO-DIMM module type is 0x0d

Change-Id: I9210ac3409a4aaf55a0f6411d5960cfdca05068d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15262
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24 18:15:09 +02:00
Elyes HAOUAS c8d24dd150 SPD: fix and add DDR2 SDRAM memory module types
Correct the definitions and add 72b-SO-CDIMM and 72b-SO-RDIMM

Change-Id: I33532e30f45f6c8c0eb6d47b0bea87689d2d9a1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15204
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24 18:09:18 +02:00
Elyes HAOUAS 46bfce3353 spd: Add module voltage for 1.8V
Add SSTL 1.8 V Interface Level as specified in
JEDEC_DDR2_SPD_Specification_ Rev1.3, page 10.

Change-Id: I0112a85f557826b629109e212dbbc752aeda305d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15202
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24 18:08:04 +02:00
Furquan Shaikh a1850bafbf intel/apollolake: Enable prefetching and caching for BIOS reads
Change-Id: I6afcc17ec8511d3fd4c1ac3b15d523d9b6752120
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15321
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-23 23:11:35 +02:00
Kyösti Mälkki f359997f86 samsung/lumpy: Fix build with System Agent blob
Broken with commit:
  2585209 mb/samsung/lumpy/romstage: read SPD data of removable DIMM

The blob can pick SPDs from the addresses defined in pei_data
and we do only define read_spd() with USE_NATIVE_RAMINIT.

Change-Id: Ibd6d7a4a53fa808b476d3060872cb10d3dfce534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15329
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-23 21:53:04 +02:00
Kyösti Mälkki 0306e6a8bf intel/sandybridge: Fix builds with System Agent blob
Broken with commit:
  5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS

Available sandybridge/systemagent-r6.bin has MMCONF hard-coded
at some places and samsung/lumpy fails at boot here:

  CBFS: Locating 'mrc.bin'
  CBFS: Found @ offset 9fec0 size 2fc94
  System Agent: Starting up...
  System Agent: Initializing

These are the last lines as captured over USB debug.

Change-Id: I441847f0e71a5e1be9c8ef6a04a81eb7bdd8a6d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15328
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 21:52:46 +02:00
Furquan Shaikh c948746c21 google/reef: Update chromeos.fmd file
1. Mark 256KiB at end of BIOS region as unusable BIOS region is
memory-mapped just below 4GiB, however last 256KiB is unusable. Mark it
accordingly in fmd file.
2. Use up holes in RW region for RW_A and RW_B.
3. Fill up holes in RO with UNUSED regions.

BUG=chrome-os-partner:54672

Change-Id: I5facc566bb70d950522e12228b0631ddf00ac63d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15313
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 20:56:52 +02:00
Lin Huang 203fe7278a rockchip/rk3399: correct sdram inc file DENALI_CTL_217_DATA value
for per cs training, there should be more cycles to switch delay line.
so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5.

BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 1000" and pass

Change-Id: I11720b7c6f009789b88ca26fc5da88597ed1622e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9de93beae09174d50a31d2df655529f71628f77c
Original-Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/352953
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/15307
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23 17:26:00 +02:00
Lin Huang 321a6a94f9 rockchip/rk3399: fix sdram training issue
After write leveling for all ranks, check the
PHY_CLK_WRDQS_SLAVE_DELAY result, if the two ranks in one slice both
meet (0x200-PHY_CLK_WRDQS_SLAVE_DELAY < 0x20) or
(0x200-PHY_CLK_WRDQS_SLAVE > 0x1E0), enable PHY_WRLVL_EARLY_FORCE_ZERO
for this slice, and trigger write leveling again.

BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 1000" and pass

Change-Id: I1a0e4e888eb62b5fae5b5e5437a385e8660a246d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 717cbac97b2045f2934e99859ce405aa3637b1c4
Original-Change-Id: Ic0d7c59404e870a7108ed64bbf3215fcc2d0973e
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/351825
Reviewed-on: https://review.coreboot.org/15300
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23 17:22:44 +02:00
Vadim Bendebury 3fd57d8239 kconfig: add missing SPI TPM CS config definition
To fully define TPM attachment to a SPI interface both bus and CS
(chip select) settings are required. Add the missing CS configuration
option.

BRANCH=none
BUG=chrome-os-partner:50645
TEST=with the rest of the patches applied it is possible to compile in
     and run TPM2 SPI driver.

Change-Id: If297df8e5b9526f156ed1414eb9db317d6af5b33
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353913
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15299
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-23 17:22:06 +02:00
Vadim Bendebury e31d24366c tpm2: add SPI TPM driver
This introduces a SPI TPM driver compliant with the TCG issued "TPM
Profile (PTP) Specification Revision 00.43" which can be found by
googling its title.

The driver implements both the hardware flow control protocol and the
TPM state machine.

The hardware flow control allows to map SPI based TPM devices to the
LPC address space on x86 platforms, on all other platforms it needs to
be implemented in the driver software.

The tis layer is somewhat superficial, it might have to be expanded
later.

A lot more implementation details can be found in the code comments.

Also, it is worth mentioning that this is not a complete version of
the driver: its robustness needs to be improved, delay loops need to
be bound, error conditions need to propagate up the call stack.

BRANCH=none
BUG=chrome-os-partner:52132, chrome-os-partner:50645, chrome-os-partner:54141
TEST=with the rest of the patches applied coreboot is able complete
     Chrome OS factory initialization of the TPM2 device.

Change-Id: I967bc5c689f6e6f345755f08cb088ad37abd5d1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 5611c6f7d7fe6d37da668f337f0e70263913d63e
Original-Change-Id: I17d732e66bd231c2289ec289994dd819c6276855
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/350124
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15298
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Tested-by: build bot (Jenkins)
2016-06-23 17:14:16 +02:00
Lin Huang 50df52244e rockchip/rk3399: Clean up voltage rail settings
The CENTER LOGIC should always be 0.9V and can not be adjusted,
so use duty_ns = 2860 to correct CENTER LOGIC to 0.9V. And now
DDR seems to run stable at 800MHz on the gru board.

BRANCH=none
BUG=chrome-os-partner:54144, chrome-os-partner:53208
TEST=run "stressapptest -M 1024 -s 1000" and pass

Change-Id: Ia900e248c10ddd0ab630446a324cc0446c0fa49b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: f4fb1cefb59ac4099cef8b32a68ed9222e708478
Original-Change-Id: I2238da6c17908d09bc284b321d796901317ed9ef
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/352772
Reviewed-on: https://review.coreboot.org/15297
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23 17:13:40 +02:00
Vadim Bendebury 9e6b0ee2c4 gru: kevin: initialize cr50 SPI interface
Set up the pins and initialize the driver.

BRANCH=none
BUG=chrome-os-partner:50645, chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
     communicate with the cr50.

Change-Id: I9fc1cb84ccababa6f58b2d5beec4572dc1d79da1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 6100471db2a00fd411afc05d621429b8f8a2f81d
Original-Change-Id: I0ccd8777288e35870658268813c9202dd850c70d
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349852
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/15296
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23 17:12:56 +02:00
Vadim Bendebury 2c109a74cb rk3399: add definition for SP0 iomux
This register is described in the TRM in section called
GRF_GPIO3D_IOMUX. Added definitions allow to configure the SPI0
interface.

BRANCH=none
BUG=chrome-os-partner:50645, chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
     communicate over SPI0

Change-Id: Ieee3fcae6095020042b02673c7d863f398ed2eb4
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 8f155e3b47c9f44ad4e5a2513916572e7d5ec0ab
Original-Change-Id: Iea92971b0520dc4549cd0fd263dcb2098f80f6d6
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349851
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/15295
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23 17:12:19 +02:00
Vadim Bendebury 26588707c5 kconfig: allow various tpm type and interface permutations
Until now it was assumed that all TPM devices were of the same type
(TCG 1.2 spec compliant) and x86 based boards had LPC connected TPMs
and all other boards had I2C connected TPMs.

With the advent of TPM2 specification there is a need to be able to
configure different combinations of TPM types (TPM or TPM2) and
interfaces (LPC, I2C and SPI).

This patch allows to do it. Picking Chrome OS still assumes that the
board has a TPM device, but adding MAINBOARD_HAS_TPM2 to the board's
Kconfig will trigger including of TPM2 instead.

MAINBOARD_HAS_LPC_TPM forces the interface to be set to LPC, adding
SPI_TPM to the board config switches interface choice to SPI, and if
neither of the two is defined, the interface is assumed to be I2C.

BRANCH=none
BUG=chrome-os-partner:50645
TEST=verified that none of the generated board configurations change
     as a result of this patch. With the rest of the stack in place it
     is possible to configure different combinations of TPM types and
     interfaces for ARM and x86 boards.

Change-Id: I24f2e3ee63636566bf2a867c51ed80a622672f07
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 5a25c1070560cd2734519f87dfbf401c135088d1
Original-Change-Id: I659e9301a4a4fe065ca6537ef1fa824a08d36321
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349850
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15294
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-23 17:11:48 +02:00
Furquan Shaikh 0e820ce745 mainboard: Remove use of IFD_BIOS_START/IFD_BIOS_END
BUG=chrome-os-partner:54563

Change-Id: If07710333cbb84ce70d6d4fa40602a74c898c08a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15293
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-22 22:21:13 +02:00
Furquan Shaikh 8065bd4ce1 intel/apollolake: Add API for get_bios_size and use it
get_bios_size returns the value of bios_size. Use this function to
calculate bios_size for caching in bootblock.

BUG=chrome-os-partner:54563

Change-Id: I2e592b1c52138bd4623ad2acd05c744224a8e50b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15292
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-22 22:20:57 +02:00
Duncan Laurie 14b2a4d574 drivers/i2c/generic: Fix compile failure
This variable name was changed in chip.h but not the consumer
and it was submitted before it was caught.

Change-Id: I7c492b588b2fd854a9eeac36029a46da324a7b1b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15109
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-22 20:25:14 +02:00
Hannah Williams 4cff1d52a5 soc/intel/common/acpi: Add _PTS, _WAK methods
Change-Id: I72f894fd14bf0e333d9fda970397a3c82de598c3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15121
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 17:26:15 +02:00
Kyösti Mälkki cf0e60faf4 ACPI S3: Add common recovery code
There is nothing to backup with RELOCATABLE_RAMSTAGE.

Change-Id: I780a71e48d23e202fb0e9c70e34420066fa0e5b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15243
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 12:10:17 +02:00
Kyösti Mälkki 8e627a2e51 ACPI S3: Fix prohibited wakeup
No boards affected, resume is always allowed when enabled
in the build.

Change-Id: I1816557da8201af9e137c389b57852ec20390b6a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15275
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 12:07:53 +02:00
Kyösti Mälkki d132c996a6 ACPI S3: Split support for HAVE_ACPI_RESUME
Some of the support functions will be built for romstage
once HIGH_MEMORY_SAVE is removed.

Change-Id: I43ed9067cf6b2152a354088c1dcb02d374eb6efe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15242
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 12:04:25 +02:00
Kyösti Mälkki 34fcec1933 cpu/cpu.h: Change guard around function declarations
This file is pulled for x86 bootblock builds using ROMCC,
which would choke on struct bus.

Change-Id: Ie3566cd5cfc4b4e0e910b47785449de81a07b9ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15274
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-22 11:40:09 +02:00
Kyösti Mälkki a16cd9cdda ACPI S3: Move SMP trampoline recovery
No need to make low memory backup unless we are on
S3 resume path.
Hide those details from ACPI.

Change-Id: Ic08b6d70c7895b094afdb3c77e020ff37ad632a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15241
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 11:31:35 +02:00
Kyösti Mälkki 65cc526f6f Ignore RAMTOP for MTRRs
Without RELOCATABLE_RAMSTAGE have WB cache large enough
to cover the greatest ramstage needs, as there is no benefit
of trying to accurately match the actual need. Choose
this to be bottom 16MiB.

With RELOCATABLE_RAMSTAGE write-back cache of low ram is
only useful for bottom 1MiB of RAM as a small part of this gets used
during SMP initialisation before proper MTRR setup.

Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 11:03:42 +02:00
Kyösti Mälkki c5400efc11 intel: Drop old romstage main() without asmlinkage
Change-Id: I0d471766fdf46f6e61ac692fc98730a2429f981f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15234
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 10:53:17 +02:00
Kyösti Mälkki 75d139bdf2 intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP
Change-Id: Ib3250677ee926deaa957c83aca7479eb0159358c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15231
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 10:50:51 +02:00
Kyösti Mälkki 8431fcb8c8 intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I616143b55d7c5726dc2475434e3fcb08b8d69bda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15230
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 10:49:18 +02:00
Kyösti Mälkki b4f827d45a intel cache-as-ram: Fix comment about MTRRs
Change-Id: I5b9e10fe119c1a046494235e85f730bedfe8578d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15282
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 10:48:18 +02:00
Douglas Anderson e00b2de71c rockchip: kevin/gru: Slow memory down to 300 MHz
At the higher speeds stressapptest shows memory errors.  We don't want
to track down random problems due to simple memory corruption, so slow
memory back down to 300 MHz until someone figures out how to make it
faster without sacrificing reliability.

BRANCH=None
BUG=chrome-os-partner:54144
TEST=stressapptest -M 1024 -s 240

Change-Id: I2417f93f65b1491a028a63ce563ed7dd7831becc
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I02182b25e677e27e8541445938f9da9ae9553fa6
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/350480
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15120
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21 22:52:32 +02:00
Lin Huang 9a5c4fefec rockchip: gru: pass poweroff gpio parameter to BL31
To support gpio power off SOC, we need to pass the power off
gpio parameter to BL31. Gru reuse tsadc overtemp pin as power
off gpio, so need to iomux to gpio function when use gpio power
off function, either in bl31 or depthcharge.

BRANCH=None
BUG=chrome-os-partner:53448
TEST=Build gru

Change-Id: Ibfe64042f39f6df1b87536b50fe432859bf74426
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: Ie7a1bbea4a12753f0abac7a9142f2e032686ce31
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349703
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15119
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21 22:50:28 +02:00
Lin Huang 5a4be8a2c7 rockchip: gru: pass reset gpio parameter to BL31
To support gpio reset SOC, we need to pass the reset gpio
parameter to BL31. Note: request BL31 have supported this
function.

BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru

Change-Id: I182cff11ce6f5dc3354db0dc053c128b813acf9f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I8283596565d552b1f3db31c28621a1601c226999
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349702
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15118
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-06-21 22:37:02 +02:00
Lin Huang 8f1f982565 rockchip: gpio: add macro so we can get gpio number
sometimes we need gpio number, so add this macro so we
can get the gpio number if we need.

BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru

Change-Id: I0c8c6cc0643a66e9ae1f21b02c7364c641b9805d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I98e8cf15543179904295a86e9f720c2d7c8b443a
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/349701
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15117
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21 22:25:29 +02:00
Furquan Shaikh e0667f7b54 google/reef: Keep ISH enabled for now
Disabling ISH causes resets in FSP which leads to hang. This should be
fixed in a later stepping. Until then keep ISH enabled.

BUG=chrome-os-partner:54033

Change-Id: Id9cb276eed8d027ab6d2e81a5ec962bc730c1ff5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15142
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-21 22:01:55 +02:00
Furquan Shaikh 49f7dd9982 libpayload/pci: Correct MASK macro names
BUG=chrome-os-partner:54563

Change-Id: I8ef1c595205fe46dd64357051eeb232e2bbbebc1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15270
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21 20:41:06 +02:00
Furquan Shaikh 0be3da53c6 intel/apollolake: Calculate BIOS mmap at runtime
Instead of hard-coding the BIOS region start and end addresses, read
BIOS_BFPREG to determine the base and limit for the mapped BIOS
region.

BUG=chrome-os-partner:54563

Change-Id: Iddd3d4cc945f09e8f147e293bb9144471a6a220d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15269
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-21 20:39:32 +02:00
Furquan Shaikh bdcda710a7 intel/apollolake: Add helper routine for spi reg read
BUG=chrome-os-partner:54563

Change-Id: I56bc6b5292aec676103a436048abee8577edd961
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15268
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 20:38:15 +02:00
Furquan Shaikh d3f4c5be8b intel/apollolake: Rename _spi_reg_read/write to _spi_ctrlr_read/write
This makes it clearer that the read/write operations are being performed
on the host controllers registers.

Change-Id: Id63d778a4a03c461d97e535c34b85ada3ae469de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15281
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 20:25:28 +02:00
Furquan Shaikh 2b57691ce0 commonlib/region: Add helpers for dynamic initialization of region dev
This allows initialization of runtime region devices and xlate region
devices where all parameters cannot be statically determined.

BUG=chrome-os-partner:54563

Change-Id: Ia6e1b695fed3bbfa08598d1593e650fc1465d41f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15267
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 20:23:40 +02:00