This wasn't caught earlier because many boards select it manually.
Change-Id: I245ef8f44923b5384123bd549570db7c348e03b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18771
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Some renamings force us to update our code:
* Scan_Ports() moved into a new package Display_Probing.
* Ports Digital[123] are called HDMI[123] now (finally!).
* `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.
Other noteworthy changes in libgfxinit:
* libgfxinit now knows about ports that share pins (e.g. HDMI1 and
DP1) and refuses to enable any of them if both are connected
(which is physically possible on certain ThinkPad docks).
* Major refactoring of the high-level GMA code.
Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Updating headers corresponding to FSP 2.0.0
Below UPDs are added to FspmUpd.h
* PeciC10Reset
* PeciSxReset
rest of the changes are update to comments
CQ-DEPEND=CL:*340004,CL:*340005,CL:*340006
BUG=None
BRANCH=None
TEST=Build and test on Poppy
Change-Id: Id8ecea6fa5f4e7a72410f8da535ab9c4808b3482
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Reviewed-on: https://review.coreboot.org/19109
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable SS link trunk clock gating & D3hot when device enters
D3 state.
Similarly disable SS link trunk clock gating & D3hot when device enters
D0 state
TEST=Build & boot Poppy board. Check working for XHCI wake when DUT
is in S3.
Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18879
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch cleans up the code by:
o adding necessary default definitions to Kconfig
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
devicetree.cb and minnow3.fmd carried over a lot of code from google/reef
which is not correct for Minnow3 hardware. Minnow3 is not intended to
boot Chrome OS and does not need Chrome related flash regions. The
erroneous code is removed.
These changes are the same as those done for leafhill in commit:
6a48923 mainboard/intel/leafhill: Clean up
This was tested by building with the new configuration and
booting to UEFI Payload
Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18963
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This fixes the following issues, with no functional changes:
ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar"
ERROR:SPACING: space required after that ',' (ctx:VxV)
WARNING:LONG_LINE_COMMENT: line over 80 characters
WARNING:SPACE_BEFORE_TAB: please, no space before tabs
ERROR:FUNCTION_WITHOUT_ARGS: Bad function definition
ERROR:SPACING: space prohibited before that close parenthesis ')'
WARNING:RETURN_VOID: void function return statements are not generally
useful
2 unfixed issues:
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
Verified that the binary was the same before and after the changes.
Change-Id: Ie9afb50e268f4140872e39fe8bede231a43d5cc6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19078
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
All boards select INTEL_EDID, move it to nb folder.
Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19086
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This adds a gru libpayload config, that should fit all gru-based
devices such as kevin.
As gru-based devices are CrOS devices, select the associated config
to enable CrOS-specific features.
Change-Id: I6e79b763fc497c126612b8786a669a33b57ea29f
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/19137
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Move odt stretch into own function.
Apply workaround on SandyBridge C-stepping CPU only.
Apply odt stretch on all other CPU types.
Don't depend on empty DIMM detection, as in case one slot
is empty ref_card_offset is zero.
Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17616
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
quick_ram_check doesn't change contents of memory.
Run it in S3 resume, too.
Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17615
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Silency noisy raminit logging by:
* Removing verbose logging from loops.
* Printing detailed summary at end of loop instead.
* Using the same scheme already present in some functions.
Change-Id: I412d81592436ac0d2422caf396c64e0c34acc2d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17611
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Remove cross rank/cross channel dependency.
I guess this is a mistake that could lead to instabilities.
Tested on Lenovo T430 (Intel IvyBridge).
Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17610
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.
Change-Id: I88b5ef8e12ac606751952a493f626e1b146e98f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add package options to the CPU Kconfig that may be selected by the
mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4
packages and each requires a unique binaryPI image. Default to the
correct blob used by the northbridge by looking at the CPU's package.
Also modify Gardenia to select the right package.
See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for
additional details for the packages.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec)
Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18989
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The term 'callout' has a specific meaning in AGESA, meaning
invoking the said function from AGESA / PI proper.
OemPostParams() does not fall into that category.
Change-Id: I0ad1cbf244501207af96e0ac415a5b80ced91052
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19141
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The term 'callout' has a specific meaning in AGESA, meaning
invoking the said function from AGESA / PI proper.
OemPostParams() does not fall into that category.
Change-Id: I45913d93323b3813fc35b1dd1fdca3d782d4b01f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19140
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
BUG=b:35583511
TEST=check i2c bus 0 initializes from ap console log
Change-Id: Ibb6709159f5ed28ad0b62397d2ddb504dec55167
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/19105
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Memory training data that is saved as part of S3 feature in SPI
flash can be used to bypass training on normal boot path as well.
When RegisterSize is 3 in the register playback tables, no register is
saved or restored. Instead a function is called to do certain things in
the save and resume sequence. Previously, this was overlooked, and the
pointer containing the current OrMask was still incremented by 3 bytes.
Change-Id: I7221a03d5a4e442817911ba4862e3c0e8fa4a500
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Sky Lake PCH contains two GSPI controllers. Using the common GSPI
controller driver implementation for Intel PCH, add support for GSPI
controller buses on Sky Lake/Kaby Lake.
BUG=b:35583330
Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for GSPI controller in Intel PCH. This controller is
compliant with PXA2xx SPI controller with some additional registers to
provide more fine-grained control of the SPI bus. Currently, DMA is
not enabled as this driver might be used before memory is up (e.g. TPM
on SPI).
Also, provide common GSPI config structure that can be included by
SoCs in chip config to allow mainboards to configure GSPI
bus. Additionally, provide an option for SoCs to configure BAR for
GSPI controllers before memory is up.
BUG=b:35583330
Change-Id: I0eb91eba2c523be457fee8922c44fb500a9fa140
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19098
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since there are multiple controllers in the LPSS and all use the same
frequency, provide a single Kconfig option for LPSS_CLOCK_MHZ.
BUG=b:35583330
Change-Id: I3c0cb62d56916e6e5f671fb5f40210f4cb33316f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
In order to be able to use SPI TPM on x86, allow TPM_SPI to be used
with PC80_SYSTEM.
BUG=b:35583330
Change-Id: Ibe626a192d45cf2624368db42d369202a4003123
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19093
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Use proper CAR semantics for global/static variables.
2. Use spi_* functions directly instead of using a global structure to
store pointers to those functions.
BUG=b:36873582
Change-Id: I1fc52ab797ef0cbd3793a387d68198efc5dde58c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19114
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=b:35647967
TEST=boot from bob
Change-Id: Ib64107b17fb6e93dbe626ce92f3bc9da8b84784e
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452284
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19113
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=b:35775002
TEST=boot from bob
Change-Id: I6324f3c02da55a8527f085ba463cbb1f4fb5dc2e
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452283
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19112
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This is required to provide tsc freq required by timer library.
BUG=b:35583330
TEST=Verified that delay(5) in verstage adds a delay of 5 seconds.
Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19094
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Even though the i2c spec has no minimum data hold time in fast
mode the trackpad vendor indicates 300ns is their minimum. However,
the topology of the board uses FET isolation to cross voltage
domains. Therefore, the default 300ns which should work isn't reflected
on the device side of the voltage isolation circuit. Therefore,
increase the data hold time to show an observed data hold time of
more than 300ns on the device side.
BUG=b:36469182
Change-Id: I1b70f2f53c5a29cc7cfd5035a71ca5811b3bcba0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19065
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When using rise_time_ns and fall_time_ns there's currently not
a way to specify a target data hold time. The internal 300ns
value is used. However, that isn't always sufficient depending on
bus topology. Therefore, provide the ability to specify data
hold time in ns from devicetree, defaulting to default value if
none are specified.
BUG=b:36469182
Change-Id: I86de095186ee396099709cc8a97240bd2f9722c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19064
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
Change-Id: I986bb7a88f53f7f7a0b05d4edcd5020f5dbeb4b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18626
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Officialy we enter with BIST in %eax, but %ebp is old backup register.
Note that post_code() destroys %al.
Change-Id: I77b9a80aac11ae301fdda71c2a20803d7a5fb888
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18625
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As we now apply asmlinkage attributes to romstage_main()
entry, also x86_64 passes parameters on the stack.
Change-Id: If9938dbbe9a164c9c1029431499b51ffccb459c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18624
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Function enables PCI MMCONF and XIP cache, it needs
to be called before giving platform any chance of
calling any PCI access functions.
Change-Id: Ic044d4df7b93667fa987c29c810d0bd826af87ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18623
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
pci_lookup_name might return NULL from using format_name internally
which could cause a crash when trying to print that value. We
check for NULL and print a more appropriate value in that case.
Change-Id: I499f0b5e1681f3926df0d8a325aab2c666ebd632
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19089
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add 100 Mhz reflock default values for Ivybridge.
Some values are extracted from MRC, those marked as
guessed needs to be verified.
Tested on Lenovo T430 (Intel IvyBridge) and DDR3-1800.
Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17609
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add support for 100MHz reference clock on ivybridge.
Allows to use more frequencies than sandybridge.
Tested on Lenovo T430 (Intel IvyBridge) on DDR3-1800.
Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17607
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use Ivy Bridge specific magic values on Ivy Bridge instead
of Sandy Bridge values.
The values are extracted from MRC.bin.
Should increase raminit stability.
Tested on Lenovo T430 (Intel IvyBridge).
Change-Id: I49fdfe5ae3e65704d22e083e8446e3f1069869bc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17606
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Update ABUILD_VERSION for the timeless & checksum parameters.
Change-Id: I96b4c027ccf3e5563dbf4598a0d1fb5e83a5985a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19034
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Add --checksum command line parameter to specify a base path and
filename for the checksums to be saved into.
- Save checksums of each platform into the specified file appended
with "_platform"
- Save a sha256 checksum of the sorted config.h into the base file
appended with "_config"
Change-Id: Id24dc4b10afbd35cdb8750f75b934419e6e80290
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19033
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Remove document history. Since the document is now stored in git,
this is no longer needed.
- Fix spacing for the kconfig_lint help output
- Add license information to the bottom of the document.
Change-Id: I9854602a6ad9b4a99bf3988e1d7662b3b426e608
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19075
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This mainboard uses a LVDS connection for LCD panels. Apollo Lake SoC
provides a display controller with three independent pipes (1x eDP and
2x DP/HDMI). PTN3460 is an embedded DisplayPort to LVDS bridge device
that enables connectivity between an eDP source and LVDS display panel
(http://www.nxp.com/documents/data_sheet/PTN3460.pdf).
The bridge contains an On-chip Extended Display Identification Data
(EDIT) emulation for EDIT data structures.
This patch sets up PTN3460 to be used with the appropriate LCD panel.
Change-Id: Ib8fa79bb608f1842f26c1af3d7bf4bb0513fa94d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19043
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This was guarded because AGESA.h only defined it starting from fam15
header files. We can simply test if it has been defined.
The way coreboot currently handles this request, is to make the
allocation outside the heap, since heap may not be in CBMEM and thus
not available runtime. The acquired buffer from Allocate() would not
be found with Locate() or Deallocate(), so move the alloc_cbmem()
call for better code symmetry.
Change-Id: Ibf0066913a0b73e768488c3afbeb70139a3961eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19039
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Once we do CAR teardown between AmdInitResume() and
AmdS3LateRestore() we attempt to find our heap from the
temporary memory buffer instead of cache.
S3 resume is essentially broken anyways and this is not yet a
proper fix at all, but barely keeps system from halting on S3
resume.
Offset that seems arbitrary was taken from hudson/agesawrapper.c.
Change-Id: Idddf2ecde5a9d32d532071d6ba05032be730460c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19038
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Producer and consumer of these buffers now appear in same file.
Also add test for uninitialized NonVolatileStorage in SPI.
Change-Id: Ibbf6581a0bf1d4bffda870fc055721627b538b92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19037
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
- Add some variables to allow server customizations.
- Verify that coreboot images and containers exist before trying to
remove them.
- Add a couple of convenience targets: clean & cleanall to remove
coreboot containers and images or ALL containers and images.
- Add docker-what-jenkins-does target to run a test build locally inside
a docker image.
- Add docker-jenkins-server target to test the server configuration and
run the jenkins docker image.
- Add docker-jenkins-shell and docker-shell targets to run the
coreboot-sdk and coreboot-jenkins-server images.
- Update the help.
Change-Id: I1896f33e7eddfe3248f44ae780de65ce50d5dd99
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/18004
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Nico Huber