Brya’s chromeos.fmd contains a region for RECOVERY_MRC_CACHE,
but does not select HAS_RECOVERY_MRC_CACHE, so it’s unused.
BUG=b:174266035
TEST=Check MRC cache can allocate in recovery mode.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6b83eec3dcf27bafde610a701e55f1371a5d4571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51081
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fetch second source factory cache configuration (SSFC) as an optional
element to the firmware config interface. Introduce a Kconfig so that it
can be enabled and used on required mainboards.
BUG=b:177055126
TEST=Build and Boot to OS in Magolor.
Change-Id: I81137406d21e77b5d58a33f66778e13cf16c85c7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51094
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This just reformats these files. go fmt should probably be
run on the check-in of every .go file.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I70ced115bad42d123474b18bbff2e4c0a16f3d88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To supply memory information for Guybrush, the lpddr4x script for
generating SPDs needs to be updated for Cezanne.
BUG=b:178722935
TEST=Add the part used on Majolica to the global lpddr4x json file
and verify that the output is similar to the actual SPD used for
Majolica.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I1f522cb4a92b4fe4c26cad0689437c33ec44befe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51015
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the EC is reset on PLTRST this information will be lost, causing
system control interrupts to potentially stop functioning.
Change-Id: I137ef6c574a372601bc51f6e815158767acd0e1b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50489
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With this change NMI works in the kernel:
----------------
| NMI testsuite:
--------------------
remote IPI: ok |
local IPI: ok |
--------------------
Good, all 2 testcases passed! |
---------------------------------
See setup_lapic() for where this gets configured.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia391ec5a015d909462ff8aaf3cb047c6fd45fe0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
This function should be using the RK_CLRSETBITS() macros to access the
special Rockchip write-mask registers, like the rest of our code. Also,
there were already existing bit field definitions for these bits that
should be used (although it makes sense to adjust them a bit to allow
passing in the channel number).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If1f5c06aabb16045d890df3bbd271f08a2cdf390
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51080
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
From JSL FSP v2376 "FirmwareVersionInfo.h" header file is
added and "FirmwareVersionInfoHob.h" is deprecated. This patch
adds support to display firmware version information using
"FirmwareVersionInfo.h" header file.
Changes included in this patch:
- Add Kconfig to select FirmwareVersionInfo.h
- Add code change to display firmware version info using
FirmwareVersionInfo.h header
No change in version info print format.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This has been tested on the OCP Delta Lake platform.
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Add a weak variant routine to allow variants to perform any needed
initialization in ramstage.
BUG=b:178094376
TEST=none
Change-Id: I65dc1cdf15b68d9f2239e02fcb4b2c902d749378
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50827
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the missing PM initialization for Lynxpoint-H. There are some small
changes to Lynxpoint-LP, since some register writes are common among
both PCH variants. This is based on version 1.9.1 of reference code.
Remove the `pch_fixups()` function. The DMI configuration is specific to
Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI.
Tested on Asrock B85M Pro4, still boots. Registers have the new values.
Without this patch, nearly all registers don't have the expected values.
Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47208
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Three calls to memchr() had incorrect length values which could lead to
memory overrun.
Add non-null checks to ensure correct return values from memchr()
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ief7b7e2ecb9b5d2e05e6983d92d02fa00935b392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Create the blipper variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:179648964
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BLIPPER
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Change-Id: I8e67521bd9ab05c257cb3d5d5d4cf506f258bfa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
CB:50863 refactored the data_training() function to split out read gate
training into a separate function, but in the course of this forgot to
correctly initialize the local obs_err varible in the new function to 0.
This means that it will be used uninitialized, and when it happens to be
non-zero it makes the training process fail. Due to the convoluted
control flow in the function, it seems that GCC's static analyzer
couldn't pick up on this uninitialized use.
The whole variable is unnecessary anyway, all it's used for is to force
the function to return two lines below without doing anything with
side-effects in between. This patch removes the variable and simplifies
the code in all three training functions to avoid this uninitialized use
issue and make everything a bit more readable. (Also restore the
original pre-clang-format continuation line intendations for more
readability.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia475d64c06f2ec1bf9295742d173ce66717b821c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51079
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This causes the linux kernel to complain:
32/64X address mismatch in FADT/Pm1aEventBlock: 0x00000400/0x00000000FED80800
32/64X address mismatch in FADT/Pm1aControlBlock: 0x00000404/0x00000000FED80804
32/64X address mismatch in FADT/PmTimerBlock: 0x00000408/0x00000000FED80808
32/64X address mismatch in FADT/Gpe0Block: 0x00000420/0x00000000FED80814
The linux kernel also verifies that the PM Timer block only uses IO
ports.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I612b6bfb67d8559127ab2ee8a2fb828493820e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Stamp_boost 1640 parameter is too short to keep APU performance.
Restore parameter to 2500 then APU could have longer boost time (~3xxx sec)
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Change-Id: Ie08394d0b1a693f71336cb4cb6ce9528dfdce14b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Printing this in both bootblock and romstage is redundant, since the CPU
family and model aren't expected to change between bootblock and
romstage entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: Id7c6aea0d8a6dac39114593584e534661faea89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Because the entries were formatted differently to the baseboard, the
devicetree overrides didn't work as intended, and all 5 entries from
the baseboard were included, and then the overrides were applied, but
the baseboard's entries were kept, so there were duplicate ACPI
entries, which causes errors when parsing the table.
Fixes: 5f30ae3714 ("mb/google/volteer: update thermal table for Eldrid")
BUG=b:181034399
TEST=compile, verify static.c is correct now
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I32fe2eae591ed4d3c08378977c463327f7ee1100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51044
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the first version DPTF parameters. The TDP is down to 13w for acoustic concern.
BUG=b:177777472
BRANCH=firmware-volteer-13672.B
TEST=build test image and verified by thermal team.
Change-Id: I36f016530a61e3660938ce8d2948bb3b0f275d88
Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51030
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Broadwell has these devices, so add them to Lynx Point as well. This is
done in preparation to have Broadwell boards use Lynx Point ACPI code.
Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46959
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the first version DPTF parameters received from the thermal team.
BUG=b:177628854
TEST=cros build-ap --debug -b dedede --fw-name galtic
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ia8e76d303db0add95e77693f15cad108fa92303b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The codebase currently has only unix line endings, so add a lint tool
to check for windows line endings.
BUG=None
TEST=Verify that line endings are caught both inside and outside a git
repo.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I6faf99a3184e4843640fb8965f8124de0bc52ce7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Add a help target
- Add the -Wshadow and -Werror options
- Add a way to disable -Werror
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d9fe5beb3a2e103a0bf4603712c3a5ed15f93be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Add a help target
- Add the -Wshadow option
- Add a way to disable -Werror
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icd4e5cf51d60254d274c6e5093285cd49ff1607a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This fixes the following 2 complaints:
bucts.c: In function ‘main’:
error: unused parameter ‘envp’
error: ‘bucts_state’ may be used uninitialized in this function.
The bucts_state wasn't real, but the compiler couldn't tell, so use
one variable to check for modifications instead of two.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iff1aae3441ec366d272e88b6b6634980d61cb8ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rewrite early QPI initialisation to account for variables in the
register values. Trace replays did not capture these relationships.
Tested on out-of-tree HP 630, still boots.
Change-Id: I5d393e8222be286ab4d4dc074d85f721b07bbca4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49586
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The device function is missing in the PCI device table in the PPR, but
is present in the hardware. Verified on a Mandolin board with PCO APU.
The corresponding ticket for the PPR is DESPCSOC-6667.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie91438bc905691d443ca4e7841549d1e3bca39ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The PSP soft fuse bit 6 doesn't do what the comment above it says. See
NDA document #55758 for details.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic84cf6e1eee30af92cd700dc4bf78290143bf88b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
DPR size is in MiB, but the range boundaries are expressed in KiB. In
addition, DPR and TSEG use the same attributes, so unify both regions.
Also improve a comment about DPR, since `is special` is uninformative.
Change-Id: I4479483e17890b5a4c39165138fa1c5f8215bc84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46987
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The per-lane registers need to be modified in some cases. Also, MRC
does not have any delay after the loop, so remove it.
Tested on out-of-tree HP 630, still boots.
Change-Id: If02e171d2e999f4a5be5b43ecc5aafe8ca092951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49585
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Given that the PCI devices/registers being accessed are about QuickPath,
this code must be part of QuickPath init. Move it with the other code.
Tested on out-of-tree HP 630, still boots.
Change-Id: I0854e7f0ce3070eed1adc0603f68a9d1552204d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49584
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Eric Lai