Commit graph

6180 commits

Author SHA1 Message Date
Kyösti Mälkki
d15183144a cpu/x86/smm: Define APM_CNT_NOOP_SMI
Old (!PARALLEL_MP) cpu bringup uses this as the first
control to do SMM relocation.

Change-Id: I4241120b00fac77f0491d37f05ba17763db1254e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22 11:44:45 +00:00
Angel Pons
40b3943093 soc/intel/broadwell/systemagent.c: Fix typo
Broadwell does not have any `TESGMB`, but it has a `TSEGMB`.

Change-Id: Id25030aa86f2312e261eceb8b78c3878e9e0ee04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22 11:43:27 +00:00
Kyösti Mälkki
a9f881d039 ACPI: Drop some HAVE_ACPI_RESUME preprocessor use
Change-Id: Idfb89ceabac6b6906e31a3dbe9096d48ba680599
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-20 20:15:00 +00:00
Felix Held
fca4535acf soc/amd: move acpi_wake_source.asl to common directory
Files are both identical and common for both SoCs.

Change-Id: I54b78108d342a0fd03bf70ffe6a09695c5678eb4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42545
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19 23:47:24 +00:00
John Zhao
b8febf44d1 soc/intel/tigerlake: Update TCSS for SW CM support
This change adds support for SW CM. Add Operating System Capabilities
(_OSC) method to enable USB/DisplayPort/Inter-domain USB4 Internet
Protocol tunneling and enable PCIe tunneling as well. Remove Connect
Topology(CNTP) command because kernel driver directly works with SW CM
Thunderbolt firmware. Update _DSD method for USB4 support across XHCI
and PCIe root ports.

BUG=b:140645231
TEST=Check Type C device all ports connection/enumeration with SW CM.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I859c5075882e40d7be30d4ba88cc825886712b74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-19 21:55:32 +00:00
Sumeet R Pawnikar
51e0fd91d5 soc/intel/common/acpi: rename dptf.asl to dptf_common.asl file
Rename dptf.asl to dptf_common.asl under soc/intel/common/acpi path
to avoid any kind of confusion with another dptf.asl file under
soc/intel/common/acpi/dptf path. Sometime it's confusing to have
two dptf.asl files just one directory apart.

BUG=None
BRANCH=None
TEST=Build and boot on volteer system

Change-Id: I23d93719e23c0b7659ccb23e5d0868f879bc162c
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-19 18:43:44 +00:00
Sumeet R Pawnikar
a5ba5133ce tigerlake: add unique acpi device ids for dptf
Add unique new acpi device ids for dptf for Tiger Lake soc based platforms
and update volteer speficic dsdt.asl file accordingly. The Linux kernel
driver expects these new acpi device ids for dptf functionalities.

BUG=None
BRANCH=None
TEST=Build and boot on volteer system

Change-Id: I7dbb812c0fc0f5084c98cf2752ce7ddce8e4d50e
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-19 18:43:27 +00:00
Felix Held
9412b3e9bb soc/amd/picasso/uart: factor out console-related functions
Move uart_platform_base and uart_platform_refclk to their own
compilation unit to avoid preprocessor usage. The newly created
compilation unit is only added to the build when PICASSO_CONSOLE_UART
is selected.

Change-Id: I56911addc8c000a0772156e5166720867cdd26fe
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42517
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19 16:45:55 +00:00
Patrick Georgi
b8fba86b14 Kconfig: Escape variable to accommodate new Kconfig versions
Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.

While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.

Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-19 15:29:04 +00:00
Felix Held
f13b6ebc89 soc/amd/picasso/i2c: use config_of_soc()
Change-Id: I2ebe072a5c887b16d2a39f029069bc8674f8eaea
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18 20:15:56 +00:00
Felix Held
71800909f3 soc/amd/picasso/acp: use config_of_soc()
Change-Id: I815b013438d66eef6605dba7cfbd96b9a4aff9b2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-18 20:15:01 +00:00
Raul E Rangel
34fb9399de soc/amd/picasso: Add ability to enable/disable UART to device tree
If we are not using the UARTs or they don't have the correct GPIOs
configured we should let the mainboard disable them.

BUG=b:153001807
TEST=Dump SSDT and see UART device is disabled

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifc04e36e0ebe5cce4b6cc228c7174dc76f2ffa4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-18 16:43:09 +00:00
Felix Held
ef3395d990 soc/amd/picasso: remove AMDFW_OUTSIDE_CBFS option
The option to have amdfw outside of CBFS used dd to write amdfw at a
given location overwriting anything that was there before, which may
cause the build to fail due to the FMAP header being overwritten
resulting in a not too obvious error that the image is a legacy image
without FMAP header.

Mandolin was the only board using this functionality, but I fixed the
placement of components in the flash image there, so that amdfw can just
be placed in CBFS avoiding those problems.

Change-Id: I0f3abab9d3939da43e1681d5cfe2c8d494402acf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42438
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18 13:23:42 +00:00
Kyösti Mälkki
000d91af00 soc/intel,chromeos: Fix EC RO/RW status in GNVS
For baytrail and braswell, explicitly initialise
it to ACTIVE_ECFW_RO without ChromeEC.

For broadwell and skylake, fix it to report actual
google_ec_running_ro() status.

Change-Id: I30236c41c9261fd9f8565e1c5fdbfe6f46114e28
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42389
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18 12:51:09 +00:00
Karthikeyan Ramasubramanian
6abee84250 soc/intel/tigerlake: Enable FSP-S compression
Use LZ4 compression technique to compress FSP-S. This provides some
SPI ROM space savings (~36 KiB) in each CBFS. FSP-M is XIP and hence not
compressed. LZ4 is chosen over LZMA since the decompression saves
~25 ms for an extra overhead of ~1KiB.

LZ4 Compression:
fsps.bin	0xe6fc0	fsp	254262 LZ4  (290816 decompressed)
LZ4 Decompression:
 17:starting LZ4 decompress (ignore for x86)          712,361 (1,072)
 18:finished LZ4 decompress (ignore for x86)          750,695 (38,334)

LZMA Compression:
fsps.bin	0xe6fc0	fsp	253415 LZMA (290816 decompressed)
LZMA Decompression:
 15:starting LZMA decompress (ignore for x86)         707,696 (1,150)
 16:finished LZMA decompress (ignore for x86)         767,763 (60,067)

BUG=b:158034451
TEST=Build and boot volteer mainboard.

Change-Id: I91e33eb7b688b5383f3a0075a28ac21250314973
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42444
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18 08:33:09 +00:00
Karthikeyan Ramasubramanian
8021b474fb soc/intel/jasperlake: Enable FSP-S compression
Use LZ4 compression technique to compress FSP-S. This provides some
SPI ROM space savings(~60 KiB) in each CBFS. FSP-M is XIP and hence not
compressed. LZ4 is chosen over LZMA since the decompression saves
~50 ms for an extra overhead of ~1.5 KiB.

LZ4 Compression:
fsps.bin	0xa9fc0	fsp	203423 LZ4  (262144 decompressed)
LZ4 Decompression:
 17:starting LZ4 decompress (ignore for x86)          433,550 (1,154)
 18:finished LZ4 decompress (ignore for x86)          461,620 (28,069)

LZMA Compression:
fsps.bin	0xa9fc0	fsp	202132 LZMA (262144 decompressed)
LZMA Decompression:
 15:starting LZMA decompress (ignore for x86)         478,448 (1,174)
 16:finished LZMA decompress (ignore for x86)         557,725 (79,277)

BUG=b:158034451
TEST=Build and boot waddledoo mainboard.

Change-Id: I416b1d91d7f4836b1e9c641b0fe07b39876364ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18 08:33:03 +00:00
Karthikeyan Ramasubramanian
203af60464 soc/intel/cannonlake: Enable FSP-S compression
Use LZMA compression technique to compress FSP-S. This provides some
SPI ROM space savings(~27 KiB) in each CBFS. FSP-M is XIP and hence not
compressed. LZMA is chosen over LZ4 since it provides extra space
savings of ~1 KiB for the decompression overhead of ~7 ms.

LZMA Compression:
fsps.bin	0xd1fc0	fsp	190132 LZMA (217088 decompressed)
LZMA Decompression:
 15:starting LZMA decompress (ignore for x86)         343,289 (417)
 16:finished LZMA decompress (ignore for x86)         373,922 (30,632)

LZ4 Compression:
fsps.bin	0xd1fc0	fsp	191310 LZ4  (217088 decompressed)
LZ4 Decompression:
 17:starting LZ4 decompress (ignore for x86)          345,676 (581)
 18:finished LZ4 decompress (ignore for x86)          369,101 (23,424)

BUG=b:158034451
TEST=Build and boot helios mainboard.

Change-Id: Ic0d0d81c81eaa365f3dbfdd2e00ac76cea287387
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42446
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18 08:32:03 +00:00
Sumeet R Pawnikar
447472ec54 soc/intel: remove unused dptf.asl file and other defines
Remove unused cannonlake dptf.asl file and cleanup defines from apollolake
dptf.asl file as per soc/intel/common/acpi code changes for dptf.

BUG=None
BRANCH=None
TEST=Build and boot on the system

Change-Id: I4c8bf2bd5da9d5881e7690bff34816b19dd96072
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18 08:30:19 +00:00
Sumeet R Pawnikar
5e53bd5822 soc/intel/common: make dptf acpi device ids configurable
Make dptf acpi device ids configurable for thermal functionality
as per soc/intel/common/acpi code changes for dptf.

BUG=None
BRANCH=None
TEST=Build and boot on volteer system

Change-Id: I5161d19dc663cdb9a7b004bb681059c9af2aaf4f
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-18 08:29:49 +00:00
Alexey Buyanov
d182425af2 soc/intel/common: Introduce ASL2.0 syntax
Fix last legacy ASL syntax match in acpi/pcr.asl

BUG=none
TEST=Deltan coreboot binary remains the same after the changes are
applied

Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com>
Change-Id: Ia1021851b42b8fad52b3197d9003056d3dd2db04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42437
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18 02:50:14 +00:00
Furquan Shaikh
5edbb1c5d9 Revert "soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run"
This reverts commit d5f1e0f973.

Reason for revert: FSP-S is now fixed to not touch the SPI
configuration registers. Thus, coreboot does not need to reconfigure
SPI after FSP-S has run.

BUG=b:153506142
TEST=Verified that SPI configuration registers look the same before
and after FSP-S has run. em100 works fine without any additional
changes in coreboot to reconfigure SPI.

Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-17 20:54:32 +00:00
Felix Held
097e449013 soc/amd/picasso: rename PICASSO_UART Kconfig option
The PICASSO_UART Kconfig option is about using the internal MMIO UART
controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART

Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-17 18:52:07 +00:00
Furquan Shaikh
ca481ee87f soc/amd/picasso: fix build if PICASSO_UART is unset
This change includes uart.c in bootblock, romstage, ramstage and
verstage unconditionally because this file is handling more than just
the UART console configuration. This allows boards to take advantage
of picasso_uart_mmio_ops even if PICASSO_UART is not selected.
uart_platform_base and uart_platform_refclk mustn't be provided if
PICASSO_UART is unset, so add an #if around those functions.

BUG=b:158346697

TEST=Mandolin builds again.

Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 18:51:25 +00:00
Wonkyu Kim
c66c15334a soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD
This patch adds support for enabling/disabling PCIe hot-plug via
a chip config option PcieRpHotPlug, which is copied to the corresponding
FSP-S UPD.

BUG=b:156879564
BRANCH=none
TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:18:45 +00:00
Patrick Rudolph
c59d9e3917 soc/intel/cannonlake/vr_config: Add CFL defaults to TDC powerlimit
Add CFL defaults for VR TDC config and provide Iccmax for additional Xeon
CPUs tested on the Prodrive/Hermes board.

Based on the following Intel documents:
* Document Number 570805 (XEON E EDS Vol 1)
* Document Number 337344 (CFL Datasheet Vol 1)
* Document Number 571264 (CFL CNP PDG)

Change-Id: I681de076318fb647c44cc8b8c42eb297018cc540
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-17 09:17:47 +00:00
Patrick Rudolph
9de8c8013b soc/intel/cannonlake: Use table instead of switch-case
This makes future changes easier to review.

Change-Id: I5d67801a46a1613fbc7f813e94933fa30c1b92df
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-17 09:17:38 +00:00
Elyes HAOUAS
da7749c5d6 soc/amd/picasso/include/soc/memmap.c: Add missing <stdint.h>
include <stdint.h> for 'uint32_t'.

Change-Id: I8768b7f0692ed703a060dc0406b517dc001cc25d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-16 08:06:35 +00:00
Kyösti Mälkki
eadd251bf7 cpu/x86: Define MTRR_CAP_PRMRR
Followups will remove remaining cases of PRMRR_SUPPORTED and
SMRR_SUPPORTED in the tree.

Change-Id: I7f8c7d98f5e83a45cc0787c245cdcaf8fab176d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:05:16 +00:00
Kyösti Mälkki
87e6796a90 soc/amd: Replace enable_smi_generation()
Change-Id: I9846df34fd2b6b15549fa33d3eda137544fa4219
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:04:48 +00:00
Kyösti Mälkki
0778c86b3b sb,soc/intel: Replace smm_southbridge_enable_smi()
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:04:09 +00:00
Kyösti Mälkki
040c531158 soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)
Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:03:44 +00:00
Kyösti Mälkki
ad882c3b17 sb/intel: Remove spurious HAVE_SMI_HANDLER test
There are no side-effects in calling acpi_is_wakeup_s3()
and apm_control() is a no-op with HAVE_SMI_HANDLER=n.

Change-Id: Ia9195781955cc5fa96d0690aa7735fc590e527e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41986
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16 08:02:54 +00:00
Kyösti Mälkki
b6585481e8 arch/x86: Create helper for APM_CNT SMI triggers
Attempts to write to APM_CNT IO port should always be guarded
with a test to verify SMI handler has been installed.

Immediate followup removes redundant HAVE_SMI_HANDLER tests.

Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16 08:02:18 +00:00
Martin Roth
4883252912 soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage
Because the PSP maps the MMIO addresses that are used to non-
deterministic addresses, the accesses need to be able to find
the address at runtime.

BUG=b:158124527
TEST=Build & boot with Trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I68305e0f31956c57bfdee42025bdfe938703e82d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42061
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 22:10:16 +00:00
Kyösti Mälkki
44ef38f703 arch/x86: Remove NO_FIXED_XIP_ROM_SIZE
The variable SETUP_XIP_CACHE provides us a working
alternative.

Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-15 18:35:52 +00:00
Martin Roth
86ba0d73f3 soc/amd/picasso/graphics: implement map_oprom_vendev_rev
Picasso, Dali, and Pollock iGPU share the same PCI device ID, but need
different video BIOSes. This checks the vendor & device IDs along with
the revision and selects the correct video BIOS to use.

Also add the second VGA BIOS for Raven2-based SoCs and change all VGA
BIOS IDs to the format including the revision number.

Since SeaBIOS still expects the CBFS file name without the revision ID,
it won't find the VBIOS any more. As a temporary workaround add the
VBIOS for the silicon it will run on as VGA_BIOS_DGPU_*.

Change-Id: I8f48ecc3fbffddd21d1f830fbee26a09ac351e1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/2040455
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14 19:08:08 +00:00
Raul E Rangel
5591b91b1a soc/amd/picasso/aoac: Add wait_for_aoac_enabled
This way drivers can wait for their devices to be enabled.

I also rewrote enable_aoac_devices to take advantage of
wait_for_aoac_enabled.

BUG=b:153001807
TEST=Trembyle builds

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8e653c857e164f90439e0028e08aa9608d4eca94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14 16:53:44 +00:00
Raul E Rangel
c64755bcd7 soc/amd/picasso/aoac: Set the Target Device State when powering on
If the OS sets the target device state to D3, we need to clear it so we
can reestablish register access.

BUG=b:153001807
TEST=Boot trembyle with I2C powered off and see it power back on.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9bd1b7cfa7b8d074226c4dcdefc1a44cad8b940
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14 16:53:31 +00:00
Raul E Rangel
d53c281d0b soc/amd/picasso: Move aoac functions to new file
This functionality is needed in the PSP and I can't include all of
southbridge.c.

BUG=b:153001807
TEST=Made sure trembyle still compiles

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3a38c655588d7836e1bd033e958a505774de871e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:53:20 +00:00
Raul E Rangel
4f5936b456 soc/amd/picasso: Explicitly disable legacy UART
The legacy UARTs are supposed to default to off according to the
documentation (PPR for AMD Family 17h Model 18h). But legacy UART Range_0
is enabled after reset. The PSP might be enabling it or the documentation
might be wrong.

Having it enabled causes problems though. We have ACPI nodes defining
MMIO UARTs, and the kernel also probes for legacy UARTs. This results in
two drivers accessing the same device, one via MMIO and one via IO. I
suspect this was the cause of the garbage serial output.

Before the change you would see the following in the console:
[    0.741108] serial8250: ttyS3 at I/O 0x2e8 (irq = 3, base_baud = 115200) is a 16550A

After this change, we no longer see it.

BUG=b:152079780, b:157858890
TEST=Boot trembyle and make sure serial is still working.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9d837e449b961dbb55d1301d2107838e26b3f892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-14 16:52:58 +00:00
Jonathan Zhang
7454005a4f soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS
FSP_NV_STORAGE HOB is supported in CPX-SP FSP ww22 release.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ida06fa7f7c7937f4e66a83fdecbca8bc208d626f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42024
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:51:10 +00:00
Aaron Durbin
4a3a73c042 soc/amd/picasso: correct MCFG ACPI table
The start and end bus number in the MCFG ACPI table is inclusive.
Therefore, the number of buses decoded needs to be subtracted by
1.

BUG=b:158874061

Change-Id: Ic773bc1e0ccaa99af45d1a53919f6480887fa37e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42329
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:51:01 +00:00
Alex Levin
f3668fc1de soc/intel/tigerlake: enable CPU_INTEL_COMMON
Since we plan to use VMX, enable CPU_INTEL_COMMON.

BUG=b:157388365
TEST=tested on Volteer

Signed-off-by: Alex Levin <levinale@chromium.org>
Change-Id: I5e7bdb4310947dd8a94ee554834a67ce94377ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-14 16:48:25 +00:00
Marshall Dawson
3e2fabfa5e soc/amd/picasso: Increase SMM_RESERVED_SIZE
Correct a message of "Error: Can't add stage_cache 57a9e101 to imd".
ramstage is 0xffc90 and adding FSP-S (0x50000) failed.  Increase the
reserved region of SMRAM to accommodate both images.

BUG=b:158704095
TEST=Boot Mandolin and check console log

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I51595d80d4779e995ec2a26e395cf95d666a309e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42314
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:48:12 +00:00
Paul Menzel
bc0fc39022 soc/intel/cannonlake/acpi: Capitalize hex number to unify with Skylake
diff -ur src/soc/intel/skylake/acpi/pch_hda.asl src/soc/intel/cannonlake/acpi/pch_hda.asl
    --- src/soc/intel/skylake/acpi/pch_hda.asl      2020-05-12 11:17:42.780293920 +0200
    +++ src/soc/intel/cannonlake/acpi/pch_hda.asl   2020-05-12 11:17:42.756294169 +0200
    @@ -4,7 +4,7 @@

     Device (HDAS)
     {
    -       Name (_ADR, 0x001F0003)
    +       Name (_ADR, 0x001f0003)
            Name (_DDN, "Audio Controller")
            Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))

Change-Id: Ic8b874163ddede72a75e0dc94021683bca3e7859
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-14 16:47:11 +00:00
Jonathan Zhang
3a6d8fd889 soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
Configure FSP-M UPD parameters.

TESTED=Boot CPX-SP based server.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14 16:46:15 +00:00
Jonathan Zhang
c110595503 soc/intel/xeon_sp/cpx: add cpu entries in ssdt
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I4d057a7c385ca563bfcc7ad44f651ad1f8ca003c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14 16:45:55 +00:00
Jonathan Zhang
890cf2299d soc/intel/xeon_sp/cpx: fix MADT ACPI table
Fix MADT table generation to keep IIO stack design in consideration.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14 16:45:24 +00:00
Jonathan Zhang
110d1a98e1 soc/intel/xeon_sp/cpx: add IIO stack resources to DSDT
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Iec89551a8b88a683db5857e3a6ab4af5e446cb5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14 16:45:10 +00:00
Jonathan Zhang
3172f987fa soc/intel/xeon_sp/cpx: add NUMA ACPI tables
Add NUMA ACPI tables: SRAT, SLIT.

TESTED=Boot CPX-SP based server, check /sys/firmware/acpi/tables
for SRAT/SLIT tables.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I3374b802afd2d001e841afd85e7ae07bc27c01ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14 16:44:58 +00:00