When turning up the CPU frequency set it to turbo if that is
a possibility. Also only set the frequency on the boot CPU
since that is all we need it on, this will allow the 1-core
turbo ratio.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: I573eb7a507305814ec48cc2f624b8e6ddad43f84
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: d408c1b462983c682d61c6c447692391c2b52183
Original-Change-Id: Ib5ad746767ee0a56bc7e59de679a9342f053c0e5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234401
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9281
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The romstage_main routine takes three parameters: bist, tsc_low and
tsc_hi. However in cache_as_ram.inc only the bist value is being
passed. This patch adds the two halves of the TSC value.
BRANCH=none
BUG=None
TEST=Build and run on Samus
Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: de565f28dce8a549d74defbcf5eaf8116bb1b831
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e
Original-Reviewed-on: https://chromium-review.googlesource.com/231173
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9280
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Extend lib/reg_script.c to use a platform table to declare
additional platform specific register access routine functions.
REG_SCRIPT_TYPE_PLATFORM_BASE is the starting value for platform
specific register types. Additional register access types may be
defined above this value. The type and access routines are placed
into reg_script_type_table.
The Baytrail type value for IOSF was left the enumeration since it
was already defined and is being used for Braswell.
BRANCH=none
BUG=None
TEST=Use the following steps to test:
1. Build for a Baytrail platform
2. Build for the Samus platform
3. Add a platform_bus_table routine to a platform which returns the
address of an array of reg_script_bus_entry structures and the
number of entries in the array.
Change-Id: Ic99d345c4b067c52b4e9c47e59ed4472a05bc1a5
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 2d9fecf4287dff6311a81d818603212248f1a248
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/215645
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Change-Id: I7cd37abc5a08cadb3166d4048f65b919b86ab5db
Original-Reviewed-on: https://chromium-review.googlesource.com/229612
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9279
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add a new memory type for the next build, and rename the existing
ones to drop the Gb suffix.
BUG=chrome-os-partner:33924
BRANCH=samus
TEST=build and boot on samus
Change-Id: Iedcd3823aa80c93fc2aadbc486d74b40c9bd4279
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: bcc9827965182a7d0d5325189d55eb76f5c2f0e7
Original-Change-Id: I47d2b7e58f51f3ee00cd7797da3f8353f509f8b5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230769
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9278
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently the rt5677 codec outputs 6MHz PDM clock which is
out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS
pin is pulled down to PGND with a 47k resistor, so the
expected PDM clock is 64*FS (~3MHz) according to its datasheet.
The corresponding kernel patch that adds the PDM clock config
option is https://chromium-review.googlesource.com/#/c/230303/
BUG=chrome-os-partner:33303
BRANCH=samus
TEST=flash coreboot with this patch and see PDM CLK went
from 6MHz to 3MHz on samus with a scope.
Change-Id: Icf2c61930175bede1ee8ebc2b0fb17c2938b806c
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: b9ba4597515b2fbcc72fa22e296357c454175648
Original-Change-Id: I09acdf47bab4f641981491a84197de234918435e
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230344
Original-Reviewed-by: Dylan Reid <dgreid@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9277
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This was copied and pasted more than it should have been...
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: I5008f2992d8ab3b952042415af6d7844788e14fc
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: bff4570dffa413c4fc4dfd8c49920f6b951e944a
Original-Change-Id: I2af9a30f3df733af147e8759f78a9802d2296c0f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230753
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9276
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These are board specific adjustments that can be made for each
USB3 port.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: Iaa3ce09419dfd64e3e8187f6dc073a8c68565337
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 21000496bb4560c9d1452a128335bbf24ca1b0aa
Original-Change-Id: Iab92ff7b0218d4abd9eba8a94d34ddd9a30ddb87
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230231
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9275
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This value apparently changed to 0x27 in the hardware but was
never adjusted in firmware.
BUG=chrome-os-partner:33790
BRANCH=samus
TEST=build and boot on samus
Change-Id: Ib610fc6522715e3c841c337d420ec63563bec798
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: e01d3b47bf49861e9d53fc8db41890fe4c91ff9b
Original-Change-Id: I10ca7b77068491e143f8bf2463b481eada910618
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230232
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9274
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This will be connected to the coded for firmware upload.
BUG=chrome-os-partner:33495
BRANCH=samus
TEST=build and boot on samus, check that GSPI driver is loaded
Change-Id: Ife41394e31af9dab03495b34609cb119525f9b19
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: bbf26154da675845251c54f71d1df9df8d2a4fd5
Original-Change-Id: I25c91145aef8ca2aef229ffb27e8a45df659982e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228835
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9273
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With EVT2 systems GPIO9 is now used for touchpad wake.
BUG=chrome-os-partner:32232
BRANCH=samus
TEST=suspend/resume by touchpad on samus, with kernel workaround
to disable setting of T19 in atmel driver mxt_suspend()
51 | 2014-11-03 12:41:34 | ACPI Enter | S3
52 | 2014-11-03 12:41:37 | ACPI Wake | S3
53 | 2014-11-03 12:41:37 | Wake Source | GPIO | 9
Change-Id: I67c1a6591dc287fc780889950e78c731a5a65d44
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 8512a6e5266edaf77d300f47bd26c501f00361d7
Original-Change-Id: I8120747986e694b64d464826f87c9afa68af157a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227157
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9271
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The codec interrupt needs to be active high because multiple
interrupt sources share this line:
1) Headphone plug detect
2) Mic present
3) Hotword detect
These interrupt sources are OR-ed together.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=Jack detection works on samus
Change-Id: If35fe8493ab30d878d9fac2251acee62c776b0eb
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 348608fe61f7848db2bfd22502a0c259d24f8980
Original-Change-Id: Ief0a291d9455f2d03789198153781ff8133aa1ce
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220588
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9268
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GPIO IRQ support has been added in upstream rt5677 driver,
with new jack detect platform config options.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=headphone and mic detect works on Samus
Change-Id: I68a675ccd1fec3e5329d57aadad3229053092026
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4b90fa2f557f603661e25c9e1b4712eea15c8502
Original-Change-Id: I379087b8acdb13e65776a18c9ee3a58d4cb4e73c
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224513
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9266
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This matches the label exported by the GPIO controller in the
kernel and allows more speicific matches if there are other
devices that also export GPIOs.
BUG=chrome-os-partner:33098
BRANCH=samus
TEST=crossystem wpsw_cur returns 1
Change-Id: I96f8d0f7f9fd584be4a6f14d13e04db0a88951a8
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 736679136a0a72874304eaeae1ac58633cd2ce14
Original-Change-Id: I655549d0f0eca341581bfbf845162d8b9f5e993d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224136
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since the PD software sync is slow enable support for displaying
a screen telling the user that something is happening.
BUG=chrome-os-partner:32379
BRANCH=samus
TEST=manual testing:
1) in normal mode, with EC/PD in RW, ensure that they are rebooted
to RO and the VGA Option ROM is loaded and the wait screen is
displayed, and then the system is rebooted at the end and the
VGA Option ROM is not loaded.
2) same as #1 with EC/PD in RO already, same result
3) same as #1 with system in developer mode, same result except
there is no reboot at the end of software sync
4) same as #1 with system in developer mode and EC/PD in RO,
ensure that there is no extra reboot at the beginning or end of
software sync.
Change-Id: Ib6c4cc03952768ece76832efc84f665c52191ffb
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 6971d74ff50ced0ef94d5fec26c0e6a071d207b2
Original-Change-Id: I125744f58c6b84df1af3943d9be98fe55c7117d5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223850
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9264
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of having this in mosys just have coreboot report the
board version in SMBIOS tables.
BUG=chrome-os-partner:32359
BRANCH=samus
TEST=build and boot on samus, check /sys/class/dmi/id/product_version
Change-Id: I09d235752f4c870f99fb8c6a280e2bf9aba7e137
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 08413589ba84b07ff64c9116ca5fcc991cee3b89
Original-Change-Id: Ib851d2e79ed721dcbc1c2f2eda6da50cac064cf3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223096
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9263
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This function needs to be available in different LOGLEVELs.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=USE=quiet-cb emerge-samus coreboot
Change-Id: Ib56995db64a7417a637eb8a93350fc40e6f83340
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 716d26c82a7df1dccf8956f301ab0e103fcedcff
Original-Change-Id: Ia8f0d05af24c9070c8c9241a3a7e137f845d1cab
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/221540
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9262
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is the specific codec setup platform data for samus.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=emerge-samus coreboot
Change-Id: I00d4a2f73810f5f7bad49922321fb1c340289770
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 813c45bc3fdd7a2fb84df0e24bd470003bf4eafa
Original-Change-Id: I5e2a8fad58bb8a3d02ccece0b1f6fe52f56c94ea
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/221539
Original-Reviewed-by: Ben Zhang <benzh@chromium.org>
Reviewed-on: http://review.coreboot.org/9261
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Snow was renamed to daisy a long time ago. The only reason, it seems,
the directory was still there, was a stray board_info.txt file that
probably went in shortly after the rename.
Change-Id: Iba08665e8486fcfeb214fcd05206a5f5683aea82
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9302
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Secmon needs a special build rule because of the objcopy -B
operation required to include it in ramstage. Utilize the
manual template so builds continue to work with upcoming
build chnages.
Note: secmon is actually missing symbols still so those
still need to be addressed. That looks to be as if
--gc-sections isn't be honored, but I'm actually thinking
the symbols are just erroneously carried over as the
references for these symbols don't show up in the
symbol table:
U coreboot_build
U coreboot_extra_version
U coreboot_version
U default_baudrate
U lb_add_console
U lb_add_serial
U uart_baudrate_divisor
Change-Id: I41c75e93536b73c4304ef3a87dc39d448d1f00d4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9300
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A higher drive setting is used for fast link training, once the
link training succeeds, a known-good drive setting will be used
for the main stream transactions.
For full link training sequence, the sink devices may ask for a
preferred drive setting, thus this drive setting should be used
for the main stream transactions too.
BUG=chrome-os-partner:32129
TEST=all panels on blaze/big devices work fine.
Original-Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219544
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 13d6accfdbe678e785851057f0800a3bbef11bea)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: If2fe7d5621f15aa3134d2a3920220e149bb64be6
Reviewed-on: http://review.coreboot.org/9248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The original dp driver supports only fast link training and a
special drive setting is used for the link training sequence.
This might not be accepted by all panels. The better way is to
go through full link training sequence to negotiate for a best
drive setting.
With the change, dp driver will try fast link training first,
this is same as before. If it fails in fast link training, will
try full link training.
BUG=chrome-os-partner:32129
TEST=all panels on blaze/big devices work fine.
Original-Change-Id: I6f3402c4c5993a156c965c7f52b011d336a2946f
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219543
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 24966517d41252384af3c2784def36aebad42434)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I3e7e7e749e5c8a9f07ac6132859fcad6fc96c39c
Reviewed-on: http://review.coreboot.org/9247
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
rockchip_spi_slave has a fifo_size member which doesn't change.
This just replaces the struct member with a #define.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I9ea5cdad49ee10c5f32304d0909c4a7e74a261f9
Original-Reviewed-on: https://chromium-review.googlesource.com/220471
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit f76cce3b38ac37f4df8abf6eebb8f7c7b29da095)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I3ab4eecfcce98aff3f6c9bd8f6c4e589784c60be
Reviewed-on: http://review.coreboot.org/9246
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This re-factors rockchip_spi to remove speed_hz which will instead be
passed in via rockchip_spi_init(), thus making it easier to support
other boards which may have different slave devices attached.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10
Original-Reviewed-on: https://chromium-review.googlesource.com/220411
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c
Reviewed-on: http://review.coreboot.org/9245
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
It's used for files with custom build rules, eg.
the objcopy stuff surrounding smm and sipi_vector.
Change-Id: Ie9ab4c9c6008ca42f82f768c5f33f90c7f5f4db5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9287
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide a mechanism to define rules that apply for a given filetype
(.c, .asl, ...) across all classes (ramstage, ...)
Change-Id: If45c526d294e0374c32efef01f0213c6b78b1e43
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9286
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tell gcc what to use as target part of the generated rule.
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.
Change-Id: Ie4814143337abb3cf1e9e8db7e96201a517a17b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9285
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The ldscript_ prefix is redundant.
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.
Change-Id: I0f005c0c2abe2fdd6911a2c579cb7ec49ae5c0b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9284
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
The tegra132 SoC is currently booting up on the AVP cpu which
bootstraps the rest of the SoC. Upon exiting romstage it
runs ramstage from its faster armv8 core. Instead of hard
coding the stage loading operations use run_ramstage().
Change-Id: Ib9b3eecf376ae022f910295920a085bde6e17f9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8848
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The tegra124 SoC is currently booting up on the AVP cpu which
bootstraps the rest of the SoC. Upon exiting bootblock it
runs romstage from its faster armv7 core. Instead of hard
coding the stage loading operations use run_romstage().
Change-Id: Idddcfd5443f08d4dd41e1d9b71650ff6d4b14bc4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8847
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The rmod_stage_load structure contained the same fields
as struct prog. In order to more closely integrate with the
rest of program loading use struct prog.
Change-Id: Ib7f45d0b3573e6d518864deacc4002802b11aa9c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9143
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Instead of having different structures for loading
ramstage and payload align to using struct prog.
This also removes arch_payload_run() in favor of
the prog_run() interface.
Change-Id: I31483096094eacc713a7433811cd69cc5621c43e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8849
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The prog_run() function abstracts away what is required
for running a given program. Within it, there are 2
calls: 1. platform_prog_run() and 2. arch_prog_run().
The platform_prog_run() allows for a chipset to intercept
a program that will be run. This allows for CPU switching
as currently needed in t124 and t132.
Change-Id: I22a5dd5bfb1018e7e46475e47ac993a0941e2a8c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8846
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The struct prog serves as way to consolidate program
loading. This abstraction can be used to perform more
complicated execution paths such as running a program
on a separate CPU after it has been loaded. Currently
t124 and t132 need to do that in the boot path. Follow
on patches will allow the platform to decide how to
execute a particular program.
Note: the vboot path is largely untouched because it's
already broken in the coreboot.org tree. After getting
all the necessary patches pushed then vboot will be
fixed.
Change-Id: Ic6e6fe28c5660fb41edee5fd8661eaf58222f883
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8839
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This patch moves init for I2C, SPI, ChromeOS GPIOs to the
board-specific bootblock init function on Pinky, the idea being
to isolate SoC code so that it's more readily adaptable for
different boards.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I75516bbd332915c1f61249844e18415b4e23c520
Original-Reviewed-on: https://chromium-review.googlesource.com/220410
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 0a7dec2fe70679c3457b0bfc7138b4a90b6217c8)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib2c2e00b11c294a8d5bdd07a2cd59503179f0a84
Reviewed-on: http://review.coreboot.org/9243
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Since the UART which is used for the serial console may change from
board-to-board, this moves CONSOLE_SERIAL_UART_ADDRESS from rk3288's
Kconfig into Pinky's Kconfig.
BUG=none
BRANCH=none
TEST=built and booted on pinky
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I29837a72d8cf205a144494a6c8ce350465118b34
Original-Reviewed-on: https://chromium-review.googlesource.com/221438
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 53bff629f2e9865656beabd81e6ce1eab7c728a9)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I65835c07a49dc3a3518c6bb24a29bc6ae7dd46c9
Reviewed-on: http://review.coreboot.org/9242
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I'm not sure how the build didn't fail before. In either
case remove the duplication.
Change-Id: I764774f2b8a5839512af3f054b844a1a86efdb45
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9244
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
This is necessary to support generic gpio interface in src/lib. This
file will be later populated with more GPIO definitions.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=none
Change-Id: I3fa93f1b3b1ce99d921bbfb378b3f7ae4eb652c2
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 26f564ee10a770d57cb4af0a8ab5a264aaf1a7cd
Original-Change-Id: I68c9c3a28fcc747575436b502cb25b31afed8700
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226181
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9184
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It's an unfortunate side effect of our different-archs-per-stage
mechanism that all src/arch/*/Kconfig files are always parsed with no
if blocks to exclude them if they're not relevant. This makes it very
easy to accidentally rely on a Kconfig default set by a totally
different and not applying architecture.
This patch moves a few Kconfigs from ARM and X86 that leaked out like
this into a common Kconfig file for clarity. It also gives ARM64 its
own BOOTBLOCK_CUSTOM mechanism so that it doesn't leech off the ARM one
(currently not used by any board).
In the future, we should maybe prefix all options in the arch/*/Kconfig
files with the architecture name (such as X86_BOOTBLOCK_NORMAL and
ARM_LPAE are already doing), to make it more apparent when they are used
in the wrong place.
BUG=None
TEST=None (tested together with dependent changes)
Change-Id: I3e8bb3dfbb2c4edada621ce16d130bd7387d4eb8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5528aa9252cdf711af3c160da387c6a7bebe9e76
Original-Change-Id: Ieb2d79bae6c6800be0f93ca3489b658008b1dfae
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219171
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9235
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It also creates file names in the build directory and with
the stage sliced in, but keeps the extension for anything
not .c or .S.
Also some handling for non-.c/.S files was adapted to match.
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.
Change-Id: If8f89a7daffcf51f430b64c3293d2a817ae5120f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9175
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Urara CBFS header configuration is broken. CBFS header needs to be
right above the bootblock, and the CBFS data - 0x100 bytes above, to
allow room for proper CBFS wrapper structures.
Ideally only the header offset should be specified (and even that
could be derived from the bootblock size). But this is a more generic
problem to be addressed with different architectures' image layout
requirements in mind.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=coreboot image passes the integrity check now (it was failing
before because CBGS header was overlaying the bootblock)
$ FEATURES=noclean emerge-urara coreboot
$ /build/urara/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/build/util/bimgtool/bimgtool \
/build/urara/firmware/coreboot.rom.serial
$ cbfstool /build/urara/firmware/coreboot.rom.serial print
coreboot.rom.serial: 1024 kB, bootblocksize 9956, romsize 1048576, offset 0x4100
alignment: 64 bytes, architecture: mips
Name Offset Type Size
fallback/romstage 0x4100 stage 7100
fallback/ramstage 0x5d00 stage 18995
config 0xa780 raw 2452
(empty) 0xb140 null 1003096
Change-Id: Id615bdcc6261dea9f36a409bd90f1e4764353bb9
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 8a0115963aa7460e4c7255ab8508d7d52d67fb67
Original-Change-Id: Id200ab5421661ef39b7c7713e931c39153fdc8be
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227523
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/9187
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
A branch instruction in a branch delay slot confuses the execution
pipeline and causes an exception.
bootblock.S was written 'by hand', has a branch instruction in branch
delay slot and includes '.set noreorder' directive, which causes it to
crash when trying to branch to main().
Adding a nop instruction fixes the problem. Also adding a nop after
the last branch in the file just in case main() returns and the object
linked next starts with a branch.
BUG=chrome-os-partner:31438
TEST=Running on the simulator can reach main() now
Change-Id: I0882b2eb5ce426f5a311018ffbb6f37a2ca64d98
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221421
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9183
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Duncan Laurie