Commit graph

1443 commits

Author SHA1 Message Date
Abhay Kumar
cc37c85ab4 mainboard/google/reef: Configure DDI0, DDI1 HPD GPIO lines
Configure GPIO_199 and GPIO_200 as NF2 to work as HPD.

Change-Id: If3aa6b75ed22c221cfbedaecf16035cdd9939387
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/15447
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-01 03:52:57 +02:00
Saurabh Satija
af9f35a2ce mainboard/google/reef: Use common NHLT
Add ACPI NHLT table generation that the current hardware
supports.

Reef supports two audio codecs, Dialog 7219 for headsets
and Maxim 98357 for speakers.

Change-Id: Ie39947960c86b8f65140834e31f9ed9f1b578485
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/15440
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01 03:22:04 +02:00
Freddy Paul
7b3512dde3 google/reef: set 20K PULLUP on SDCARD DATA/CLK/CMD
SD card need 20K PULLUP on D0-D3/CLOCK/COMMAND lines.
Without this SDCARD will throw data read/write errors.

BUG=chrome-os-partner:54676
TEST=Build and boot to OS.
     Verify SD card is detected and data read/write works well.

Change-Id: I90da5b84dc2e488eb38f805322bd7b4dee394e5b
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/15345
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-29 05:34:29 +02:00
Jagadish Krishnamoorthy
6dfe25dc8b google/reef: disable unused devices
BRANCH=none
BUG=chrome-os-partner:54325, chrome-os-partner:54581
TEST=device off in devicetree should disable the device.

Change-Id: I5dada06cba0eea8a30f297e3a6940a36b2ff40ee
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15339
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-28 16:46:49 +02:00
Lin Huang
627c27bb92 rockchip/rk3399: provide multiple SDRAM configurations
We want to be able to easily change SDRAM clock rate for debugging
purposes. This patch adds configurations for 4 different clock rates.

Same configs are used for all rk3399 boards at 200, 666 and 800 MHz.
Kevin board does not run reliably at 666 MHz, an option for it is
added to run at 300 MHz, this option is available to Kevin only.

There is not much room left in the coreboot romstage section, this is
why the config file for 928 MHz is being added with this patch but is
not included in the code, one of the lower frequency options will have
to be dropped for the higher frequency option to be added.

BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 3600" and pass on both kevin and
     gru. Verified that on Kevin the firmware reports starting up
     SDRAM at 300 MHz and on Gru at 800 MHz.

Change-Id: Ie24c1813d5a0e9f0f9bfc781cade9e28fb6eb2f1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: ef5e4551b79c3f0531f9af35491f2c593f8482f1
Original-Change-Id: I08bccd40147ad89d851b995a8aab4d2b6da8258a
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/353493
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/15309
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24 20:54:01 +02:00
Simon Glass
bc679bc23c gru: Add elog support
Add code to start up elog. This uses the EC RTC to obtain the timestamp.

BUG=chrome-os-partner:52220
BRANCH=none
TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages

Change-Id: I4971d661b267ae8b7e3befeff482ca703b741743
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e4e9823d8cecbf9873e78b048e389c7a737ff512
Original-Change-Id: I0fcf55b3feccf9a0ad915deb6d323b65bf2e9811
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/353822
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15306
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24 20:52:41 +02:00
Simon Glass
fe0dd6fc93 gru: Add get_developer_mode_switch()
Add this function and make it return 0, as there is no physical dev switch
(at least I think this is what we are supposed to do).

This is needed for elog to work, which is needed so we can test RTC
properly.

BUG=chrome-os-partner:52220
BRANCH=none
TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages:
elog_init()
SF: Detected W25Q64 with sector size 0x1000, total 0x800000
elog_find_flash()
FMAP: area RW_ELOG found @ 5d8000 (32768 bytes)
elog_scan_flash()
elog_is_buffer_clear(base=0x000000000031d668 size=4096)
ELOG: flash area invalid
elog_flash_erase(address=0x000000000031d668 offset=0x005d8000 size=4096)
SF: Successfully erased 4096 bytes @ 0x5d8000
elog_prepare_empty()
elog_flash_write(address=0x000000000031d668 offset=0x005d8000 size=8)
elog_scan_flash()
elog_is_buffer_clear(base=0x000000000031d668 size=4096)
elog_is_header_valid()
elog_update_event_buffer_state()
elog_is_buffer_clear(base=0x000000000031d670 size=4088)
elog_is_area_valid()
ELOG: FLASH @0x000000000031d668 [SPI 0x005d8000]
ELOG: area is 4096 bytes, full threshold 3834, shrink size 1024
elog_add_event_raw(type=16)
out: cmd=0x44: 03 b9 44 00 00 00 00 00
in-header: 03 3f 00 00 04 00 00 00
in-data: 6e 4c 00 00
elog_flash_write(address=0x000000000031d670 offset=0x005d8008 size=11)
ELOG: Event(16) added with size 11
elog_add_event_raw(type=17)
out: cmd=0x44: 03 b9 44 00 00 00 00 00
in-header: 03 3f 00 00 04 00 00 00
in-data: 6e 4c 00 00
elog_flash_write(address=0x000000000031d67b offset=0x005d8013 size=13)
ELOG: Event(17) added with size 13
elog_add_event_raw(type=A0)
out: cmd=0x44: 03 b9 44 00 00 00 00 00
in-header: 03 3f 00 00 04 00 00 00
in-data: 6e 4c 00 00
elog_flash_write(address=0x000000000031d688 offset=0x005d8020 size=9)
ELOG: Event(A0) added with size 9
elog_add_boot_reason: Logged dev mode boot

I can't actually see the timestamp, but the EC traffic is visible.

Change-Id: I82bcf296dce4f4d146edf90b23bfae955fbe9e3a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: ffc7a7e0e7b136144d2a0b2ed21a543eafee49fa
Original-Change-Id: I1489c6b874cc49495635aec0bf303f7098455716
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/353821
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15305
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24 20:52:03 +02:00
Simon Glass
850e45f19f gru: Show the current time on start-up
Display the current time from the EC.

BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) boot on gru and see output:
Date: 1970-01-17 (Saturday)  Time:  1:42:44

Then reboot ~10 seconds later and see output:
Date: 1970-01-17 (Saturday)  Time:  1:42:53

Change-Id: I4288efc56f00e47f7575d0379a44871351da6200
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: d0361193e0ec135e21f0611d7fa6e5c02f2b2bfc
Original-Change-Id: I04a072c788ba3fc915e6d73703f966955bbd3e7e
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/351783
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15304
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24 20:51:23 +02:00
Simon Glass
2622b54936 gru: Enable EC-based RTC
Obtain the real-time clock value from the EC on start-up and show the
current time.

BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) with future commits and EC clock set, boot on gru into
      Linux shell and check the firmware log:

      localhost ~ # grep Date: /sys/firmware/log
      Date: 2016-06-20 (Monday)  Time: 18:09:16

Change-Id: Id3ef791f546419c4881a891251cbb62d7596884b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 348e9373b0e95a17f5c39ec28a480712e6e45caf
Original-Change-Id: Iff43b16a86d9fee483420ee2eff5ff3d276716a3
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/351781
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15303
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24 20:49:57 +02:00
Duncan Laurie
a2be7fbff5 google/lars: Move devices from mainboard.asl to devicetree
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices.  Then remove the static ACPI objects from the DSDT
in mainboard.asl.

This was tested on a Chell mainboard since I lack a lars device.

Change-Id: Ifba6fc6589ddd54f4c85e8858f17997fbb4b6176
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15316
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-24 20:11:20 +02:00
Duncan Laurie
d6ae2f6edb google/glados: Move devices from mainboard.asl to devicetree
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices.  Then remove the static ACPI objects from the DSDT
in mainboard.asl.

This was verified on a glados board by verifying the SSDT contents
against what used to be in the DSDT.

Change-Id: I710cbb8462d0fe695297102a64bec8e4212acc65
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15315
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-24 20:10:28 +02:00
Duncan Laurie
c8ea4c111c google/chell: Move devices from mainboard.asl to devicetree
Declare the mainboard attached devices in the devicetree and enable
the provided device drivers by default to generate the ACPI objects
for these devices.  Then remove the static ACPI objects from the DSDT
in mainboard.asl.

This was verified by comparing the generated ACPI code in the SSDT
to what was in mainboard.asl and ensuring the contents are
functionally equivalent.

Change-Id: I4725bbe2d47178568e3024fe3bb48cc80ff861c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15314
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24 20:09:31 +02:00
Kyösti Mälkki
0306e6a8bf intel/sandybridge: Fix builds with System Agent blob
Broken with commit:
  5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS

Available sandybridge/systemagent-r6.bin has MMCONF hard-coded
at some places and samsung/lumpy fails at boot here:

  CBFS: Locating 'mrc.bin'
  CBFS: Found @ offset 9fec0 size 2fc94
  System Agent: Starting up...
  System Agent: Initializing

These are the last lines as captured over USB debug.

Change-Id: I441847f0e71a5e1be9c8ef6a04a81eb7bdd8a6d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15328
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 21:52:46 +02:00
Furquan Shaikh
c948746c21 google/reef: Update chromeos.fmd file
1. Mark 256KiB at end of BIOS region as unusable BIOS region is
memory-mapped just below 4GiB, however last 256KiB is unusable. Mark it
accordingly in fmd file.
2. Use up holes in RW region for RW_A and RW_B.
3. Fill up holes in RO with UNUSED regions.

BUG=chrome-os-partner:54672

Change-Id: I5facc566bb70d950522e12228b0631ddf00ac63d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15313
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23 20:56:52 +02:00
Lin Huang
203fe7278a rockchip/rk3399: correct sdram inc file DENALI_CTL_217_DATA value
for per cs training, there should be more cycles to switch delay line.
so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5.

BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 1000" and pass

Change-Id: I11720b7c6f009789b88ca26fc5da88597ed1622e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9de93beae09174d50a31d2df655529f71628f77c
Original-Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/352953
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/15307
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23 17:26:00 +02:00
Vadim Bendebury
9e6b0ee2c4 gru: kevin: initialize cr50 SPI interface
Set up the pins and initialize the driver.

BRANCH=none
BUG=chrome-os-partner:50645, chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
     communicate with the cr50.

Change-Id: I9fc1cb84ccababa6f58b2d5beec4572dc1d79da1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 6100471db2a00fd411afc05d621429b8f8a2f81d
Original-Change-Id: I0ccd8777288e35870658268813c9202dd850c70d
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349852
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/15296
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23 17:12:56 +02:00
Furquan Shaikh
0e820ce745 mainboard: Remove use of IFD_BIOS_START/IFD_BIOS_END
BUG=chrome-os-partner:54563

Change-Id: If07710333cbb84ce70d6d4fa40602a74c898c08a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15293
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-22 22:21:13 +02:00
Douglas Anderson
e00b2de71c rockchip: kevin/gru: Slow memory down to 300 MHz
At the higher speeds stressapptest shows memory errors.  We don't want
to track down random problems due to simple memory corruption, so slow
memory back down to 300 MHz until someone figures out how to make it
faster without sacrificing reliability.

BRANCH=None
BUG=chrome-os-partner:54144
TEST=stressapptest -M 1024 -s 240

Change-Id: I2417f93f65b1491a028a63ce563ed7dd7831becc
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I02182b25e677e27e8541445938f9da9ae9553fa6
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/350480
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15120
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21 22:52:32 +02:00
Lin Huang
9a5c4fefec rockchip: gru: pass poweroff gpio parameter to BL31
To support gpio power off SOC, we need to pass the power off
gpio parameter to BL31. Gru reuse tsadc overtemp pin as power
off gpio, so need to iomux to gpio function when use gpio power
off function, either in bl31 or depthcharge.

BRANCH=None
BUG=chrome-os-partner:53448
TEST=Build gru

Change-Id: Ibfe64042f39f6df1b87536b50fe432859bf74426
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: Ie7a1bbea4a12753f0abac7a9142f2e032686ce31
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349703
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15119
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21 22:50:28 +02:00
Lin Huang
5a4be8a2c7 rockchip: gru: pass reset gpio parameter to BL31
To support gpio reset SOC, we need to pass the reset gpio
parameter to BL31. Note: request BL31 have supported this
function.

BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru

Change-Id: I182cff11ce6f5dc3354db0dc053c128b813acf9f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I8283596565d552b1f3db31c28621a1601c226999
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349702
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15118
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-06-21 22:37:02 +02:00
Furquan Shaikh
e0667f7b54 google/reef: Keep ISH enabled for now
Disabling ISH causes resets in FSP which leads to hang. This should be
fixed in a later stepping. Until then keep ISH enabled.

BUG=chrome-os-partner:54033

Change-Id: Id9cb276eed8d027ab6d2e81a5ec962bc730c1ff5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15142
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-21 22:01:55 +02:00
Freddy Paul
8200761912 google/reef: Add ACPI code for trackpad
This patch enlists ELAN trackpad on I2C4 for reef board.

BUG=None
TEST=Build and boot to OS.
     Ensure ELAN trackpad is working with ELAN trackpad driver enabled
     in kernel.

Change-Id: I788600f16dea9fac0e089cb82ccfc38a960157f9
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/15213
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 17:10:12 +02:00
Matt DeVillier
41bcf8adbf mb/google: remove superfluous header includes in bdw chromeboxes
Change-Id: I71443c7547a113bf9b64d48fe5a85c6e2302c8aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/15208
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-21 00:44:58 +02:00
Zhao, Lijian
e813c15443 google/reef: Update EMMC DLL setting in all mode
Update tuned DLL setting on all other mode, including SDR12
SDR25 and DDR50.

Change-Id: I1eb85ac6080fd78f63816d3fa9ef482484bd9f94
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/15210
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-17 21:30:45 +02:00
Furquan Shaikh
4b373ca8a0 google/reef: Add NVRAM and LEGACY sections to chromeos.fmd
Now that the flash size is increased to 16MiB, add RW_NVRAM and
RW_LEGACY sections to chromeos.fmd file.

BUG=chrome-os-partner:54390

Change-Id: I6c79d35295c4bc774f05f8045ac920474d7a791f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15192
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16 08:15:06 +02:00
Furquan Shaikh
2c4a60da35 google/reef: Update flash size to 16MiB
Use entire 16MiB flash size on reef. Adjust SIGN_CSE region
accordingly.

BUG=chrome-os-partner:54390

Change-Id: I94de509bdb2aa94625814123bf4d9758bfa37fc9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15191
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16 08:14:39 +02:00
Prabal Saha
5a3833d2d3 mb/google: Remove whitespace from devicetree on bdw boxes.
Change-Id: I189836282b4ad084fbbb74199b24505f5e141b60
Signed-off-by: Prabal Saha <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/15207
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins)
2016-06-16 06:46:13 +02:00
Matt DeVillier
f09d39db4e google/rikku: Upstream Acer Chromebox CXI2
Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to
upstream, using google/guado as a baseline.

original source:
branch firmware-rikku-6301.110.B
commit 2e71207 [CHERRY-PICK: broadwell: Update to microcode 0x1F]

TEST=built and booted Linux on rikku with full functionality

blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.bin)
external reference code (refcode.elf)

Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12802
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-16 01:43:42 +02:00
Furquan Shaikh
579fdb4910 google/reef: Correct use of globalnvs.asl
Use the correct globalnvs.asl from apollolake.

BUG=chrome-os-partner:54342

Change-Id: I1a5b8f61c540bdb2668b532f032350d8e4d48010
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-14 18:26:12 +02:00
Zhao, Lijian
e9cf848dad google/reef: Update EMMC DLL settings
Update EMMC DLL setting for reef board, after that system can
boot up into EMMC successfully.

BUG=chrome-os-partner:54228
TEST=Boot up into EMMC and check with Rootdev

Change-Id: I614cd624dce9069c5565599a955f87906bcea53b
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/15156
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-14 18:05:47 +02:00
Patrick Rudolph
266a1f794d nb/intel/raminit (native): Read PCI mmio size from devicetree
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.

Tested on Sandybridge Lenovo T520.

Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12 12:48:44 +02:00
PH Hsu
cf6526c211 mt8173: dram: Add more sample points to improve dram timing margin
BRANCH=none
BUG=chrome-os-partner:52959
TEST=verified on elm-EVT SKU1/SKU2, Oak-rev5 2GB/4GB models.

Change-Id: I228c629d9a3d6cd8fc5c4e8ba24cc52d5283b4e6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 3c19e7d
Original-Change-Id: I22356aa8d196c4c126742cfc7e85cc693acd9b39
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/347716
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15115
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:13:10 +02:00
Julius Werner
99f065fb6e oak: Select VBOOT_EC_SLOW_UPDATE Kconfig option
All current Oak boards have PD chips with update speeds that range from
slow (Oak) to "OMG it's so awfully slow I could make a cup of coffee and
it would still not be done" (Elm). Set the flag that enables the "Your
system is applying a critical update. Please don't turn it off." message
on EC software sync so that our users don't accidentally carry it back
to the store and demand a refund while it's still not done booting.

BRANCH=None
BUG=chrome-os-partner:51145
TEST=Booted Oak in normal mode with a new EC-RW image. Confirmed that I
saw the magic screen.

Change-Id: I000eab36d26b61b25d1f0da505f02ced15457255
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 274644b
Original-Change-Id: I64ba698985d5fbcf2b94115df72b70a5319106ac
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/348787
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15114
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:12:31 +02:00
Julius Werner
0a0f9c5d68 Kconfig: Set VBOOT_OPROM_MATTERS for relevant non-x86 devices
The VBOOT_OPROM_MATTERS configuration option signals to vboot that the
board can skip display initialization in the normal boot path. It's name
is a left-over from a time when this could only happen by avoiding
loading the VGA option ROM on x86 devices. Now we have other
boards that can skip their native display initialization paths too, and
the effect to vboot is the same. (Really, we should rename oprom_matters
and oprom_loaded to display_skippable and display_initialized or
something, but I don't think that's worth the amount of repositories
this would need to touch.)

The only effect this still has in today's vboot is to reboot and
explicitly request display initialization for EC software sync on
VBOOT_EC_SLOW_UPDATE devices (which we haven't had yet on ARM). Still,
the vboot flag just declares the capability (for skipping display init),
and it should be set correctly regardless of whether that actually makes
a difference on a given platform (right now). This patch updates all
boards/SoCs that have a conditional path based on
display_init_required() accordingly.

BRANCH=None
BUG=chrome-os-partner:51145
TEST=Booted Oak, confirmed that there's no notable boot time impact.

Change-Id: Ic7c77dbd8356d67af7aee54e7869f9ac35241b99
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9c242f7
Original-Change-Id: I75e5cdda2ba2d111ea50ed2c7cdf94322679f1cd
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/348786
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15113
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:11:08 +02:00
Liangfeng Wu
76655cb82c rockchip: gru: Add USB DRD DWC3 controller support
This patch adds code to initialize the two DWC3 USB
host controllers, and uses them to initialize USB3.0
on the gru rk3399 board.

BRANCH=none
BUG=chrome-os-partner:52684
TEST=boot from USB3.0 on gru/kevin rk3399 platform

Change-Id: If6a6e56f3a7c7ce8e8b098634cfc2f250a91810d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0306a9e
Original-Change-Id: I796fa1133510876f75873d134ea752e1b52e40a8
Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347524
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15112
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:10:22 +02:00
Duncan Laurie
c8d45ac88e skylake: Move I2C bus configuration to separate structure
Move the existing I2C voltage configuration variable into a new
structure that is equivalent, similar to how USB ports are configured.

This is to make room for additional I2C configuration options like
bus speed and whether to enable the bus in early boot which are coming
in a subsequent commit.

The affected mainboards are updated in this commit so it will build.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e
Reviewed-on: https://review.coreboot.org/15104
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09 17:08:33 +02:00
Duncan Laurie
7f3156dad6 skylake: gpio: Add support for setting 1.8V tolerant
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses
that are at 1.8V.  This is currently done by passing in a value to FSP
but it is needed earlier than FSP if the I2C bus is used in verstage.

This does not remove the need for the FSP input parameter, that is
still required so FSP doesn't disable what has been set in coreboot.
The mainboards that are affected are updated in this commit.

This was tested by exercising I2C transactions to the 1.8V codec while
in verstage on the google/chell mainboard.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c
Reviewed-on: https://review.coreboot.org/15103
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-09 17:07:26 +02:00
Xing Zheng
96fbc31027 rockchip: rk3399: Add support i2s
This patch enable and configure the clocks and IOMUX for i2s audio path,
and the i2s0 clock is from CPLL.

Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155
for the i2s clock div and gate setting.

BRANCH=none
BUG=chrome-os-partner:52172
TEST=boot kevin rev1, press ctrl+u and hear the beep voice.

Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9c58fa7
Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68
Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/347526
Original-Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15034
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:27:01 +02:00
Vadim Bendebury
8f8cf4d336 gru: kevin: enable EC SPI interface
This configures and enables SPI interface #5 used for EC
communications on Gru/Kevin.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the appropriate depthcharge change it is possible to trigger
     booting Chrome OS from the SD card by pressing '^U' on Gru
     keyboard at the right time.

Change-Id: I5304bf47e030c0b9b7794752f30ffdca6c03a4f4
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: b5cc177
Original-Change-Id: I99883daa60562ccddfaeb858c1957d497f05a501
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346632
Reviewed-on: https://review.coreboot.org/15032
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:22:54 +02:00
Vadim Bendebury
9ed93cb5d5 gru: kevin: configure board GPIOs
Set board GPIOs as required and add their description into the
appropriate section of the coreboot table, to make them available to
depthcharge.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to use
     keyboard on Gru, which indicates that the EC interrupt GPIO is
     properly configured. The rest of the pins will be verified later.

Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e02a05f
Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346631
Reviewed-on: https://review.coreboot.org/15031
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:21:55 +02:00
Julius Werner
221fdd8cce veyron: Add exception_init() to romstage
I'm not even sure how this slipped through... looks like it had never
been there in the first place. Anyway, on ARM exceptions should always
be reinitialized in all stages to make sure the handlers are still
around (especially in an OVERLAP_VERSTAGE_ROMSTAGE board like this one).

Change-Id: Ic74ea1448d63b363f2ed59d9e2529971b3d32d9a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-08 23:21:18 +02:00
Vadim Bendebury
993dbe1fc8 gru: kevin: define GPIOs used on both platforms
The same GPIOs are used on both platforms, definitions are added an a
new .h to make it easier to re-use them across the code.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=panel backlight still enabled on Gru as before. The rest of the
     GPIOs are used in the upcoming patches.

Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: c587880
Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346219
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/15029
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:19:32 +02:00
Jagadish Krishnamoorthy
00f21c7724 mainboard/google/reef: Configure sd card pins
Since the sd card cmd, data, cd lines are configured
as native mode, allow the native controller to control
the termination.
Configure SDCARD_CLK_FB which is used for calibrating the
timing of the actual clock buffer.

BUG==chrome-os-partner:53747
TEST=verify sd card detection

Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/348377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15096
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-06-08 16:11:54 +02:00
Shaunak Saha
f6118c62a4 google/reef: Add asl code to enable google ChromeEC
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.

BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
       connected is charging properly.

Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15069
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07 18:31:20 +02:00
jongpil19.jung
d841da8512 Kevin/Gru : Update Board ID table.
Add board id table as kevin/gru configuration.

BUG=chrome-os-partner:53519
BRANCH=chromeos-2016.02
TEST=check boot on Kevin board.

Change-Id: I30c16916f3cda0ac88d2ce5a922e936a405fcc89
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 16c7b5486befd73c3e31624970ba1c97e526676f
Original-Change-Id: Ib69ed9dad8e1a9e08717545c6be19a90e0298c43
Original-Signed-off-by: jongpil19.jung <jongpil19.jung@samsung.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/345736
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15028
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-07 16:59:07 +02:00
Shunqian Zheng
0d9839b333 rockchip: gru: update the hynix lpddr3 config to run at 928MHz
Update the DDR config and DRAM driver to allow running at up to
928MHz. Kevin config/clock rate are not being changed, but Gru now
runs at 928 MHz.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru,

Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9
Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/343984
Original-Reviewed-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://review.coreboot.org/15027
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-07 16:14:05 +02:00
Lin Huang
b497b48027 rockchip: gru: enable eDP display
This patch enables eDP display by:
o. setting HPD pinmux, backlight, vdd for eDP
o. setting vop mode
o. enabling VGA configs for edid

BRANCH=none
BUG=chrome-os-partner:51537
TEST=The dev screen is shown on kevin board

Change-Id: If8b07307454daa88727d317cc208d6c97de07ad7
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: b1ad9337510f5437f691153dc68883edf273e4c7
Original-Change-Id: Id7006619b5be638b286a5402d892a5361ac1e430
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/340026
Original-Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/14858
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-03 18:08:27 +02:00
Furquan Shaikh
ab90f96ba5 google/reef: Select UART_FOR_CONSOLE for reef
Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15044
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 17:21:17 +02:00
Kan Yan
1bfcc843ff Gale board: Move TPM setup function to verstage.c
TPM should be only be reset once in verstage.

BUG=chrome-os-partner:51096
TEST=Depthcharge no longer shows TPM error.
BRANCH=None

Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Commit-Id: 911bdaa83a05fa5c8ea82656be0ddc74e19064c3
Original-Change-Id: I52ee6f2c2953e95d617d16f75c8831ecf4f014f9
Original-Reviewed-on: https://chromium-review.googlesource.com/343537
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I8047b7ba44c604d97a662dbf400efc9eea2c7719
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14845
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-06-02 00:19:11 +02:00
Furquan Shaikh
989842c972 mainboard/google/reef: Add IFWI region to chromeos.fmd
IFWI region holds different components required for booting including
CSE firmware, PMC firmware, CPU microcode as well as the bootblock. Add
section for IFWI in chromeos.fmd

Change-Id: Ic97980ff222ad7cbd7a2970417b79150256a7a16
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15000
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-01 17:17:15 +02:00