Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.
It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.
Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The current code didn't reserve static resource the right way.
Also reduce TOLM to 0xd0000000, because those boards have so many PCI
devices that 0xe0000000 isn't sufficient.
Change-Id: Ia75a81905eea1a096aed464b63ac154e044bc99c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1220
Tested-by: build bot (Jenkins)
Don't stop if RAM init fails at first try. It's better to restart
and try again instead of failing on the first try if the second
try would have worked.
Change-Id: Ib5660265d5b10a01588f2e4022dac2ee34f2c6d0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1191
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
This is mostly necessary for reboot, but it doesn't hurt the boot process.
On reboot explicitely reset the integrated graphics, otherwise the VGABIOS
might not be able to reinitialize it properly, and you either have a still
of the last pre-reboot image, garbage or an empty screen, but no text-mode.
Change-Id: Ic3d6932fbaf720d88daaac7e4b09c3c0b9f0b0e2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1178
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
As Mathias Krause pointed out, using movw/outw on %al is clearly invalid.
Let's do another typo fix...
Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1119
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Peter and Ron pointed out two typos. They have no side effects, but
it's still worth to fix them.
Change-Id: I9aecccdbc72beb2623fbe558a06e4f1b050f6e74
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1117
Tested-by: build bot (Jenkins)
Not doing a hard reset leaves the BOFL0 register cleared, which
prevents the BSP selection from working. To make sure we start
with known values, use the SPAD0 register for soft reset detection.
If there's a value other than 0, do a hard reset.
Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1103
Tested-by: build bot (Jenkins)
Originally, ChromeBooks would get the offset of the MRC cache
from an entry in the u-boot device tree. Not everyone wants to
use u-boot on Sandybridge systems, however.
Since the new code (based on Kconfig) is now fully working, we
can drop the u-boot device tree remnants.
Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1051
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The MRC region is described by Kconfig variables, no further math
or parsing is required at this point.
Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1046
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Requirements:
- must be in ramstage (locking flash while executing code from there
might not work)
- must be after cbmem is reinitialized (so the mrc cache copy of the
current run can be found)
Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Separate Sandybridge from ChromeOS a bit
The Sandybridge code depends on chromeos features a whole lot.
As a first step, provide a code path to look up the MRC cache
without depending on u-boot.
- Move mrc cache handling to separate file
This enables us to handle the MRC cache from ramstage,
where we can write the flash safely (eg. to update the
cache).
Also teach it to lookup the current MRC cache from CBMEM,
as the original data block isn't available anymore.
After all the preparations, finally write to the SPI
as necessary. It's a simple round robin wear levelling
that erases the entire MRC cache region when it's full
and starts from the beginning.
Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1001
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This fixes my build when specifying an absolute path to the binary.
Change-Id: I95fb3960be70f78146c6afeb9cc777dccdca6b5b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/987
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
It is important to have the system configuration reported as early as
possible to have a better idea what exact chipset the platform is
running with.
This change adds code to have an early coreboot module report the CPU
and PCH information. CPU info includes the 32 bit feature information
word, the symbolic processor brand string, and information about some
features support, as obtained through CPUID instructions.
The PCH information includes the symbolic device name and PCI device
version.
Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/975
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
- New table for GT1
- Updates to GT2 17W table
- New table for GT2 35W SKU
- New table for GT2 Other
This also includes a workaround to poll on a different register
when deasserting force wake. On some SKUs the kernel is hanging
when bringing up graphics unless this register is also polled.
Change-Id: I2badf62b464e901cfb0eaf4fc196f59111c71564
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/974
Tested-by: build bot (Jenkins)
- Add config options to set backlight registers
- Update powermeter weight tables for IvyBridge GT1 and
add a new table for GT2 SKU
- Fix a few registers used during GPU PM init sequence
Change-Id: I1500bc07e3ba1bc10c77e7856089e716489dc07a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/973
Tested-by: build bot (Jenkins)
This is done inside the SystemAgent binary on Ivybridge.
Change-Id: I8fb0f593a65a4803e160b284c21b9d5021e2e4a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/970
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ASPM setting for the Direct Media Interface should no longer be done on
Ivybridge/PantherPoint based systems.
Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: http://review.coreboot.org/969
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This fixes a few cosmetics with the following three boards:
- Intel Emerald Lake 2
- Samsung ChromeBook
- Samsung ChromeBox
The following issues were fixed:
- rely on include path in ASL code instead of specifying relative
paths
- use updated ALIGN_CURRENT in acpi_tables.c
- use preprocessor defines instead of hard coded values where possible
Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/963
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
This code is still using libfdt which was denied for inclusion
in coreboot, so it won't compile as is.
Without MRC cache, waking from suspend won't work, and cold boots are
significantly slower (adds around 300-400ms per channel IIRC).
A rework of this code is currently in the works, but will take a little bit
more time (and should not hold back the mainboards being merged)
Change-Id: Ifb9e7d7b86c1f52378803a748810da0d51b58384
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/948
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- When calling map_oprom_vendev() the vendor ID and device ID
are joined into a 32 bit value. They were reversed from the
order that I would have expected - Device ID as the high 16 bits
and the Vendor ID as the low 16. This patch reverses them so
so that the the dword comparison in map_oprom_vendev() matches
what's entered into Kconfig for vendor,device.
- Change files calling map_oprom_vendev()
Change-Id: I5b84db3cb1a359a7533409fde7d05fbc6ba3fcc4
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/938
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Cougar Point southbridge does udelay in SMM, hence add it on Sandybridge
systems.
Change-Id: I6e5520ca27e7c6eaae632992fb68612067bc1e30
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/937
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
No longer include northbridge files directly in the source for
mainboard romstage.c and fix includes.
Also make required adjustments to function declarations.
Change-Id: Iafdcc0766ed44c64cc628e5935eef2c6372f5f22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/906
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
It takes about 3 seconds to scrub 8GiB DDR266 RAM.
After ECC scrub XIP cache is disabled for system stability. There is
very little to do in romstage after ECC scrub, especially when RAM
debug messages are turned off. So the delay caused by this is hardly
noticeable.
Cache for complete ROM is re-enabled before ramstage is decompressed,
and it has no unstability issues. So the code required to re-enable
cache for ROM currently already exists in cache-as-ram_ht.inc.
A Kconfig option HW_SCRUBBER enables the scrub to be run on hard
reboots and power-ons.
Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/905
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Drop comments (from e7501 era) which no longer seem to apply with
e7505. Write the semi-constant D0:F0 table as code. Some register
settings seem to be in different order compared with vendor BIOS,
and will be handled by follow-up patches.
Split RCOMP register copy function in two parts.
Drop some uses of inline and local_mdelay().
Change-Id: I8739d3b2bbad5861118e8b16ccea1dd86991204f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/896
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Makes the code a bit more readable, IMO. There is no clean way
to implement this as the affected registers are undocumented.
Seems ROMCC cannot handle the enum. Also any of my future changes
would not be even abuild tested as there is no longer a board with
ROMCC and this chipset. E7505 chipset is CAR only from now on.
Change-Id: I0e2d8ba0c7ed7cce46d9eafb8d8badf04cf75f7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/895
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Some places still hardcoded the address instead of using IO_APIC_ADDR.
Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix delay loop comments. Time waited and the comments did not match
in the origin (e7501), so delays currently "just work".
Move reset detection to main raminit and don't use generic
sdram_initialize for now, as there are local debug
functions I need to use. Fix AOpen respectively.
Disable ecc scrub, until I have it fixed for cache-as-ram use.
Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/883
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Drop maybe-prefix in registers and tables.
Have a name in place of PCI_DEV(x,y,z) to avoid confusion.
Change-Id: I88f51b50d7fd83294aa14455a83418630e1bab85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/882
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build.
Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time
which model of I945 the driver is built for.
Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/684
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Also mark the corresponding lint test stable.
Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The current directory is always part of the search path of cpp when
using #include "..."
Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In the spirit of the earlier renames.
Change-Id: I458a42c79a164483120169d1822ffa6861cc3aff
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/647
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If both FSBs on i5000 are equipped with CPU packages, one CPU
from each package is elected as BSP. To prevent races between
both BSPs, hlt the second BSP.
Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/615
Tested-by: build bot (Jenkins)
Originally brought up by Sven Schnelle in March 2011
http://patchwork.coreboot.org/patch/2801/http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html
On some mainboards it may be neccessary to reset early during resume
from S3 if the SLFRCS register indicates that a memory channel is not
guaranteed to be in self-refresh.
On other mainboards, such as Lenovo X60 and T60, the check always
creates false positives, effectively making it impossible to resume.
The SLFRCS register is documented on page 197 of
Mobile Intel® 945 Express Chipset Family Datasheet
Document Number: 309219-006
which is publically available, and the register indicates if a memory
channel is guaranteed to be in self-refresh mode (if bit = 1), or that
a memory channel *may or may not be* in self-refresh mode (if bit = 0).
The register can thus only be used to positively learn that memory is
in self-refresh. It is not known for sure that memory is *not* in
self-refresh. The register is reset by the PWROK signal, which *should*
go low during S3, and go high again when resuming, so it is unsurprising
that SLFRCS has already been cleared when we read the register.
Sven's measurements of the CKE signal on a ThinkPad shows that memory
remains in self-refresh indefinitely, until coreboot re-initializes the
memory controller, even when SLFRCS bits were = 0.
Boards which require a warm reset when SLFRCS bits are cleared must now
explicitly enable the check in the mainboard Kconfig file.
This commit selects the new option in all existing i945 mainboards.
A follow-up commit will remove the option for ThinkPads.
Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/590
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
The comparision is the wrong way round: as long as tsc
is below tsc1, the timeout is not reached
Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/530
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Adapted from northbridge/intel/e7501 with only minor changes.
This commit provides minimal patch from e7501 and I prefer any
cosmetic clean-up to be done after initial merge.
Due the incomplete register specifications, it is safer to have
e7505 as a separate directory in case I improve it to support
wider range of memory configurations. I have no e7501 to test with.
Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/295
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Choice between printk/print_ is related to CAR, but really
depends whether we compiled with GCC or ROMCC.
Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/347
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
config.h defines also unset config options (as "0") so #ifdef
matches both settings, which isn't what we want.
Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/293
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
