Commit Graph

37897 Commits

Author SHA1 Message Date
Elyes HAOUAS 0141f0d6b8 sb/amd/*/*/smbus.h: Make 'smbus.h' uniform
Reformat 'smbus.h' files and add missing <stdint.h>.

Change-Id: If78f483ca8ad2e3cffe60e22948dc8150cce3664
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-26 06:53:18 +00:00
Johnny Lin e61391738f mb/ocp/deltalake: Override coreboot log level via VPD
Tested=On OCP Delta Lake, log level can be changed via VPD.

Change-Id: I36d4b01b6fb6acc726749641df089cb3f9a4dc3e
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-10-26 06:53:06 +00:00
Michael Niewöhner e874b1c179 cpu/intel/common: implement the two missing CPPC v2 autonomous registers
This implements the two missing registers for the CPPC Hardware
Autonomous mode (HWP) to the CPPC v2 package.

The right values can be determined via Intel SDM and the ACPI 6.3 spec.

Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled
version

Change-Id: I7e2f4e4ae6a0fdb57204538bd62ead97cb540e91
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt Delco <delco@chromium.org>
2020-10-26 06:52:08 +00:00
Michael Niewöhner 6f1754d090 soc/intel/icl: enable common CPU code
Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which
gets used in CB:45535 and CB:45536 for CPPC entries generation.

Note: This also retrieves the VMX Kconfig and enables it by default,
like done for SKL and CNL already.

Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets
selected statically by the SoC to reflect this in menuconfig.

Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:51:53 +00:00
Michael Niewöhner a64b4f4548 mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
The dt option `speed_shift_enable` is obsolete now. Drop it.

Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-26 06:51:42 +00:00
Michael Niewöhner d5a45470c8 soc/intel/skl: replace conditional on dt option reading CPUID for CPPC
Check ISST (Intel SpeedShift) availability via CPUID.06H:EAX[7], instead
of relying on the devicetree option `speed_shift_enable`, that is going
to be dropped.

Test: GCPC and _CPC entries still get generated on Supermicro X11SSM-F

Change-Id: I5f9bf09385627fb6a1d8e566a80370f7ddd8605e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46461
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:49:40 +00:00
Michael Niewöhner 6267cc523b soc/intel: drop unneeded ISST configuration code
The code configuring ISST (Intel SpeedShift Technology) sets the ISST
capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware
P-States), which shall be done by the OS only.

Since the capability is enabled by default (opt-out), there is nothing
to do for us in the enabled-case. Practically speaking, there is no
value at all in disabling the capability, since one can configure the
OS to not enable HWP if that is desired.

The two other bits for EPP and HWP interrupt that were set by the code
are not set anymore, too. It was tested, on three platforms so far
(CML-U, KBL-H, SKL-U), that these are set as well by default in the
MSRs reset value (0x1cc0).

To reduce complexity and duplicated code without actual benefit, this
code gets dropped. The remaining dt option will be dropped in CB:46462.

Test: Linux on Supermicro X11SSM-F detects and enables HWP:
[    0.415017] intel_pstate: HWP enabled

Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:49:22 +00:00
Benjamin Doron 0310279411 util/intelp2m: Fix typos
Change-Id: I7210fb44ed54d365181ca23c6b92d2269dc8a697
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:49:03 +00:00
Nico Huber 308c1b7976 console/init: Drop CONSOLE_LEVEL_CONST
We limited the configurability of the debug level to stages that have
a `.data` section. This is not really a requirement, because a `.bss`
section should suffice and we always have that now.

We want to make the debug level configurable early but also want to
avoid calling get_option() early, as an error therein could result
in no console output at all. Hence, we compromise and start using
get_option() from the second console init on.

TEST=Booted QEMU once with `debug_level=Debug` and once with
     `debug_level=Notice`. On the second boot, most messages
     vanished for all stages but the bootblock.

Change-Id: I11484fc32dcbba8d31772bd0b82785f17b2fba11
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:48:45 +00:00
Sheng-Liang Pan e836d11214 mb/google/volteer/var/voxel: enable GPP_D17 for FCAM_PWR
Enable front camera power in ramstage.

BUG=b:169170677
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I8b5a9a8333ed518883aa3664a115a4ba2e8a0218
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2020-10-26 06:48:12 +00:00
Frans Hendriks 4622a2fe82 security/tpm/tspi/crtm: Add line break to debug messages
Add line break at debug messages.

Tested on Facebook FBG1701

Change-Id: Idbfcd6ce7139efcb79e2980b366937e9fdcb3a4e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46659
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:47:20 +00:00
Eric Lai 6c02ca6962 mb/google/octopus/var/fleex: Add goodix touch pad support
Add goodix touch pad as below:
HWID : GXTP7288
CID : PNP0C50
I2C address : 0x2C
I2C speed : 400Khz
HID Descriptor Address : 0x20

BUG=b:171351666
BRANCH=octopus
TEST=build image and verify goodix touch pad working.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idb4f8d3aff09712dcc98c8ae0c9ae30dc4049e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46614
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:47:10 +00:00
Patrick Rudolph 90f01ece00 soc/intel/common/block/smbus: Add define for I2C_EN
Change-Id: Iecccc363f492985555019f2390bd53472a000ba9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:46:59 +00:00
Patrick Rudolph 2c70708a78 soc/intel/common/block/smbus: Add Cannonpoint PCH-H PCI ID
This is required to make sure the defined SMBUS_BASE address is valid
even after PCI enumeration.

Tested on Prodrive Hermes.

Change-Id: Ibd40e556fd890000836d23682d4e9e3aa5200c54
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46562
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:46:39 +00:00
Tim Chu 5ec02680eb mb/ocp/deltalake: Use BMC version to represent ec version
In deltalake, there's no embedded controller and BMC version is
used to represent ec version.

TEST=Build with CB:45138 and CB:46070
Execute "dmidecode -t 0" to check if the firmware version is correct

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I388efd749170f0ebbb4dd4d32199675d92cc018e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:46:29 +00:00
Tim Chu 278ad21fa9 src/drivers/ipmi: Add function to get BMC revision
Provide a way to get BMC revision.

Tested=On OCP Delta Lake, function can get BMC revision well.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Iaaa4e8bf181a38452b53c83a762c7b648e95e643
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-26 06:46:17 +00:00
Amanda Huang cbcd8a02fc mb/google/octopus/var/fleex: Add new SKU for LTE touch
New SKU ID 5 is used for LTE touch SKU. This patch does LTE power off
for LTE sku and only use Wifi SAR table for non-LTE sku.

BUG=b:168001586
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4 and 5.

Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46643
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:45:13 +00:00
Frank Wu fc66ab6959 mb/google/zork/vilboz: Enable SAR proximity sensor STH9324
BUG=b:161759253
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage
firmware log:
\_SB.I2C2.SEMTECH SX9324: SAR Proximity Sensor at I2C: 02:28
kernel log:
INFO kernel: [   11.238644] sx932x i2c-STH9324:00: initial compensation success

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I6294ce291365443dd1c4550ba75cb7f33481b889
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45565
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:44:58 +00:00
Elyes HAOUAS 92f46aaac7 src: Include <arch/io.h> when appropriate
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:44:40 +00:00
Eric Lai f209b18df3 mb/google/zork: Update style of check on cbi return values
Since google_chromeec_cbi_get_board_version and google_chromeec_cbi_get_fw_config both call cbi_get_unit32 and return 0 as success, non-zero as failure. Let's add more readability for the false condition.

BUG=None
TEST=check with empty CBI value

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46566
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:44:02 +00:00
David Wu 7d1a137b84 mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF
Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports

BUG=none
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:43:45 +00:00
David Wu e738a7e337 mb/google/volteer/var/terrador: Disable SRCCLKREQ1#
According to the schematic, SRCCLKREQ1# is not connected, so disable it
for terrador and todor.

BUG=b:171278849
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5f7734d64390bfadbdb8d152261103adb8e75f40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-26 06:43:38 +00:00
Sheng-Liang Pan d3108d6c89 mb/google/volteer/var/voxel: Disable SRCCLKREQ1#
According to the schematic,SRCCLKREQ1# is not connected,so disable it
on voxel.

BUG=b:171279034
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46612
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:43:20 +00:00
Patrick Rudolph 9572dd8953 include/device/azalia_device: Fix typo
Change-Id: Iee2ffb3b5170cd4c630f2b26d1eb418b239a8e23
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46629
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 06:36:44 +00:00
Xi Chen 71e86d66a6 soc/mediatek/mt8192: update descriptions for dram config
MEMORY_TEST,  MT8192_DRAM_DVFS

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2e714c0ce588e48bbe6bd8e59c03bdb69dea01e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46616
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 03:04:37 +00:00
Hung-Te Lin 6871d51125 mb/google/asurada: fix EC commands timeout
The Asurada EC is using the large packet (256B) mode, and we were
seeing lots of timeout errors on various commands.

The AcceptTimeoutUs in EC SPI driver is hard-coded at 5000,
and that is too small for large packet running in 1M so we
should change EC SPI to the same value that kernel is using (3M).

BUG=b:161509047
TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot

Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46394
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 03:04:08 +00:00
Marc Jones d3d50e027f soc/intel/xeon_sp/acpi: Add pch.asl
Add ASL for the PCH. Initially, this only contains
soc/intel/common/block/acpi/acpi/lpc.asl. Additional PCH ASL
may be added in the future.

Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45836
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26 00:15:36 +00:00
Angel Pons e866a2fde4 soc/intel/broadwell: Merge `chip.c` into `systemagent.c`
Prepare to break down Broadwell into CPU, northbridge and southbridge.

Change-Id: Ic844cc3bbff760fa0eed9d81208bbeef39577e9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46698
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25 16:11:53 +00:00
Angel Pons cb2080f551 soc/intel/broadwell: Drop `broadwell_pci_ops`
This is essentially a duplicate of `pci_dev_ops_pci`.

Change-Id: I06a21ebd759c35910cd753d3079ea7902868e89d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46697
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25 16:10:29 +00:00
Angel Pons 08e5b65f46 nb/intel/haswell/gma.c: Drop unused ChromeOS include
Change-Id: I598fe743354ea429d6821b95be7d209a9fcf9f0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46693
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25 16:10:13 +00:00
Paul Menzel 6a8990110e mb/lippert/frontrunner-af: Add blank line in code
Adding the blank line reduces the differences with the variant
toucan-af.

Change-Id: I58bfc99109a2df2eab54a562dc13e7bd946890d9
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46716
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25 13:36:07 +00:00
Paul Menzel 79b4df2d08 mb/lippert/frontrunner-af: Remove unused header include
Change-Id: If1d4128055a0fd50d109b4aa04c7d0c8ebb2f6c5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-25 13:35:27 +00:00
Paul Menzel 9a264d7ac9 mb/lippert/frontrunner-af: Add board URL
Change-Id: If58d87296ed6fb176d4bc42ba6f6f39ca069adfd
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-25 13:35:16 +00:00
Angel Pons fe152de697 nb/intel/haswell/gma.c: Drop unused `set_translation_table` function
Change-Id: I6c65a5a74a83b8da299245fd6f4a7ae7c1ed30c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46692
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25 12:45:24 +00:00
Subrata Banik 28371e2826 soc/intel/alderlake/romstage: Skip GPIO configuration from FSP
Set GpioOverride UPD to 1 to skip GPIO configuration in FSP phases

TEST=Able to build and boot ADLRVP to OS.

Change-Id: Ie965a85d9da9b6a23b385536313b852e66909cf4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-25 06:18:03 +00:00
Subrata Banik a8ddc89d27 vc/intel/fsp/fsp2_0/adl: Update FSP header file version to 1432
List of changes:
1. FSP-M Header:
- Add new UPD GpioOverride
- Change help text for PlatformDebugConsent UPD
- Adjust Reservedxx UPD Offset
2. FSP-S Header:
- Adjust Reservedxx UPD Offset
- PcieRpLtrMaxSnoopLatency and PcieRpLtrMaxNoSnoopLatency array grew
  by 4 elements

Change-Id: I54aabd759b99df792b224f91ce94927275dd9b80
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46695
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25 06:17:54 +00:00
Angel Pons da59ca94cf nb/intel/haswell/gma.c: Drop space after unary `!`
Change-Id: I72f75f3df50af362874818f2c1883a6a1c741087
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46691
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 21:44:18 +00:00
Angel Pons db3047c57b nb/intel/haswell/gma.c: Move log message to the right place
The message was being printed too early, possibly because it was
relocated around alongside the rest of the code.

Change-Id: I4257f6f0baa1c398aa1df9bd3274458abfaf28a6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46690
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 21:44:05 +00:00
Angel Pons e153a35029 nb/intel/haswell/gma.c: Use `config_of` in `gma_setup_panel`
This is to reduce differences between Haswell and Broadwell.

Change-Id: I8d6a8ee02e24bee22f0a7b69098ea8430095ba90
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-10-24 21:43:47 +00:00
Angel Pons 14cd17a5fb soc/intel/broadwell/gma.c: Align `igd_setup_panel` with Haswell
Rename it, add a print and factor out refclock value into a variable.

Change-Id: I7248e0b54cd6310cf74eadc5d976a8868cf822f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46688
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 21:43:31 +00:00
Angel Pons ebf800c538 nb/intel/haswell/early_init.c: Remove invalid register writes
MRC does not use the value of SSKPD, and will overwrite it with constant
values at the end of memory initialisation. Since coreboot does not rely
on this particular bit's value, it is safe to drop the writes to set it.

MCHBAR register 0x6120 is undocumented. It is nowhere to be found in any
documentation or code I have access to; not even for Sandy/Ivy Bridge,
the platform where this mysterious register write originally came from.

These workarounds were copied from Sandy Bridge, but do not apply to
Haswell. They were dropped on Broadwell, so drop them for Haswell too.

Tested on Asrock B85M Pro4, still boots.

Change-Id: I21d9656a7595d47ac8648c08d223b7cbafd213c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46683
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 21:43:10 +00:00
Angel Pons f27662f5ba nb/intel/haswell/finalize.c: Align with Broadwell
Reorder register writes to match the locking order in Broadwell.

Tested on Asrock B85M Pro4, still boots and registers are still locked.

Change-Id: Ibe15c2598fabda752c9a54eba6362621e144ad77
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46682
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:47:59 +00:00
Angel Pons 6fe3c06614 nb/intel/haswell/finalize.c: Align MC locking with Broadwell
Broadwell uses a 32-bit or, so also use it on Haswell for consistency.
This has no effect because MRC already locks the memory controller down.

Tested on Asrock B85M Pro4, still boots and register is still locked.

Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46681
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:47:27 +00:00
Angel Pons 8cc39a5fae nb/intel/haswell/finalize.c: Lock down MC ARB register
The Haswell System Agent BIOS Spec revision 0.6.0 indicates this
register needs to be locked, and Broadwell already locks it.

Tested on Asrock B85M Pro4, still boots and register is locked.

Change-Id: Icdeb39e2fdde1403b6ab83faed214addca863f4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46680
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:47:17 +00:00
Angel Pons 97f0d81503 nb/intel/haswell/finalize.c: Lock PCU DDR PTM
This register has a lock bit. The Haswell System Agent BIOS Spec
revision 0.6.0 indicates it needs to be set, thus set it. Note that
Broadwell already locks this register.

Tested on Asrock B85M Pro4, still boots and register is locked.

Change-Id: Ie23b825e708edbfc04ec0d7783f868e8632eb608
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46679
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:46:57 +00:00
Angel Pons 63837b0af0 nb/intel/haswell/finalize.c: Drop obsolete SA PM lock
This register had a lock bit on Sandy Bridge, but does not on Haswell.
Moreover, the bit remains cleared on Asrock B85M Pro4 with coreboot.
Therefore, remove the write to this bit, because it has no effect.

Tested on Asrock B85M Pro4, still boots.

Change-Id: I382a6d69233ced5af069767eb61b56741ed665be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46678
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:46:42 +00:00
Angel Pons 385ce9f4f8 nb/intel/haswell/finalize.c: Use PCI register names
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I46331225f36a58615c9cb67d6387fd020d30a04d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46677
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:46:28 +00:00
Angel Pons f92f27370d soc/intel/broadwell: Use get_{pmbase,gpiobase}
This is to align Broadwell and Lynx Point.

Change-Id: I9facaec2967616b07b537a8e79b915d6f04948a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45717
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:46:11 +00:00
Angel Pons cbcbb6767e sb/intel/lynxpoint: Ensure that `dev->chip_info` is not null
Use either a regular null check or `config_of` to avoid bugs.

Change-Id: I36a01b898c3e62423f27c2940b5f875b73e36950
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46665
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:45:49 +00:00
Angel Pons 84fa224b53 sb/intel/lynxpoint: Use spaces around `|`
Coding style says so.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I72386bbe4b38602a641bf8dc9448d6a3e95d297a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46718
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:43:15 +00:00