Some usb devices exhibit signal loss which causes xHCI entering
compliance mode. The resolution is to disable xHCI compliance mode.
BUG=b:122671995
TEST=check "Disable Link Compliance Mode" bit of "SuperSpeed Port Link
control" register and usb operation successfully.
Change-Id: Ia2ae7e52391fadc8ed23b8b76c45d410757d22ec
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/30948
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With commit aaced4a (cpu/intel/common: Use a common acpi/cpu.asl file),
some model_206ax code was moved to a common place. However, autoport
was not updated accordingly.
Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30967
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add available thermal sensors information for CPU throttling action.
BRANCH=None
BUG=b:120058043
TEST=Built and tested on Arcada system
Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Required for ACPI S3 suspend support at some motherboards.
Synchronizing with flashchips.c/h flashrom source code.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I4d15d5acf0e2044e5128ce809c282fbcb35f24f0
Reviewed-on: https://review.coreboot.org/c/30746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a
clone of X220, with additional USB3 controller on pci-e (as i7 variant
of x220), and a powered ESATA port wired to ata4 (Linux' annotation).
Documentation added.
Tested:
- CPU i5-2520M
- Slotted DIMM 8GiB
- Camera
- Mini pci-e on wlan slot
- Msata on wwan slot
- On board SDHCI connected to pci-e
- USB3 controller connected to pci-e
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
SeaBIOS, or Linux payload (Heads)
Not tested:
- Fingerprint reader on USB2
- Onboard USB2 interfaces (wlan slot, wwan slot)
Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With the i82801gx code automatically disabling devices ethernet
NICs attached to the southbridge PCIe ports can now be disabled
during the ramstage.
Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30245
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The implementation is a simplified version of the haswell/broadwell
code. This also adds a chip option to enable coalescing from the
devicetree.
Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The IO mask shouldn't contain zeros inside the block of ones.
Change-Id: Icfebbf1d1d88ceef58800339bf899931fdc61ab7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/30954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Sometimes, it’s not clear, what log level is configured (in Kconfig and
CMOS), so print the log level in the banner.
coreboot-4.9-354-gff6e99cebe Tue Jan 15 15:23:20 UTC 2019 bootblock starting (log level: 7)...
Change-Id: I82c87ae90cd53fd47458fc6df3ef2c7f238f0f3d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/30935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
```
if (!(a & (0xffff << 16))) {
^~
src/lib/libgcc.c:40:18: error: result of '255 << 24' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]
if (!(a & (0xff << 24))) {
^~
src/lib/libgcc.c:45:17: error: result of '15 << 28' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]
if (!(a & (0xf << 28))) {
^~
```
Change-Id: I7bdd75c20a76b303743d7e7e0d3a6503760284fd
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/23361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
set SaGv = SaGv_Enabled , To Enable System Agent dynamic frequency support
set HeciEnabled = 1, To Enable heci communication
set speed_shift_enable = 1 To Enable Speed Shift Technology support
Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
CNL,WHL and CFL all are not using midfixed option in SaGv so keeping it for
CNL only and removing it for others.
Change-Id: I754515c2f8e249479c603872c61ac9a006e962ff
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30917
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On the Sarien/Arcada platforms, the EC is not trusted to provide
the state of the ESC+REFRESH+PWR recovery combination. On these
platforms the Cr50 latches the state of REFRESH+PWR for use as the
recovery mode key combination.
BUG=b:122715254
BRANCH=none
TEST=Verify recovery mode screen shown after pressing REFRESH+PWR
Change-Id: If336e9d7016987be151ab30d5c037ead3a998fe0
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
On the Sarien/Arcada platforms, the EC is not trusted to provide
the state of the ESC+REFRESH+PWR recovery combination. On these
platforms the Cr50 latches the state of REFRESH+PWR for use as the
recovery mode key combination.
BUG=b:122715254
BRANCH=none
TEST=Verify recovery mode screen shown after pressing REFRESH+PWR
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Ie3ce519956f916023c8c52f1d11fa93331f52f3c
Reviewed-on: https://review.coreboot.org/c/30929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The address bits 19:0 of TSEG_LIMIT read as zero, but are ignored on
comparison. The result is that the limit is effectively FFFFFh.
Add one MiB to the register value to make TSEG 8MiB instead of 7MiB.
Fixes a crash related to SMRR not matching the TSEG region.
Change-Id: I1a625f7bb53a3e90d3cbc0ce16021892861367d8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
RISCV parts can be created with any one of four CPU modes enabled,
with or without PMP, and with either 32 or 64 bit XLEN.
In anticipation of parts to come, create the Kconfig variables for these
architecture attributes.
Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30348
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change tcc offset from 15 to 3 for sarien.
BUG=b:122636962
TEST=Match the result from TAT UI
Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30808
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to EDS #565870 chapter 5.3.1, AG3E bit in PMC located in PMC
memory mapped register but not pci config spaces. Change the programming
to affect that difference.
BUG=b:122425492
TEST=Change System Power State after failure to "s5 off", and boot up
onto sarien platform, check the register with iotools mmio_read32
0xfe001020 and bit 0 is set.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I0934894558fd9cbc056dea8e7ac30426c2529e4e
Reviewed-on: https://review.coreboot.org/c/30945
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The general rule is to configure GPIOs used by coreboot in bootblock
(using the reset table), and GPIOs used by OS in RAM stage.
However, GPIO_9 will be used as both, and we need to reconfigure it to
properly set up debounce, however, it is no longer possible to change
bootblock, so we also configure it in RAM stage to make the new
debounce configuration take affect.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=Reboot stress test grunt (>100 times); no messages in dmesg like:
tpm tpm0: Timeout waiting for TPM ready
Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03
Reviewed-on: https://review.coreboot.org/c/30922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
FT4 has a strange property where whenever the debounce registers for any
one gpio are changed, the FT4 disables interrupt propagation for ALL
gpio irqs for ~4ms.
In other words, if an edge interrupt of one gpio happens exactly during
this debounce-irq-off window immediately following the configuration of
another gpio, the interrupt will be lost.
It is quite difficult to deal with this in the kernel, since during kernel
boot time, drivers & devices are probed asynchronously, meaning it may
happen that an already loaded driver may miss an interrupt when some
later driver is being probed and configuring its gpio interrupt.
To eliminate this possibility, we pre-configure the debounce registers in
ram stage for all gpios that will be used as irqs later by the kernel
using the same configuration as used by the kernel, as per this table:
IRQ Debounce
Edge Remove Glitch
Level High Preserve Low Glitch
Level Low Preserve High Glitch
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=Reboot stress test grunt (>100 times); no messages in dmesg like:
tpm tpm0: Timeout waiting for TPM ready
Change-Id: I94c7ecfb14e5bb209b3598e10287c80eb19da25b
Reviewed-on: https://review.coreboot.org/c/30921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
define wakeup-delay-ms to 20ms. This avoids the pop
noise heard at the start of capture.
BUG=b:119926436
TEST=with kernel patch
https://lore.kernel.org/patchwork/patch/1029806/
no pop sound heard at start of capture
Change-Id: I299a584ef2ba66d1e752515100cbe3919b2108f6
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/c/30726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
define wakeup-delay-ms to 20ms. This avoids the pop
noise heard at the start of capture.
BUG=b:119926436
TEST=with kernel patch
https://lore.kernel.org/patchwork/patch/1029806/
no pop sound heard at start of capture
Change-Id: I2593afa69cfb955f6a2b695406855e0f31f28468
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/c/30725
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Passes out wakeup-delay to driver. This delay is applied at
the start of capture to make sure dmics are ready before we
start recording. This avoids pop noise at begining of capture.
BUG=b:119926436
TEST=
With kernel patch
https://lore.kernel.org/patchwork/patch/1029806/
No pop sound heard at start of capture
Change-Id: I32b18bf80fad5899ab4093a127dfd52d589bc365
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/c/30724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Declaring a Kconfig symbol ahead to override its default also always
sets implicit dependencies. If the original symbol doesn't have any,
Kconfig gets confused.
Change-Id: Ie6d9ca96e4b6037eefd432dd386cb5e540deb0ed
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.
This way libgfxinit also gets build-tested by Jenkins.
Change-Id: Ic6678d3455f1116e7e67a67b465a79df020b2399
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
After a96e66a (soc/intel: Clean mess around UART_DEBUG) got merged,
all mainboard using intel cannonlake,coffeelake, kabylake, skylake,
icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.
TEST=Intel client and IoT team has verified that LPSS uart
is working fine on CNL, WHL and ICL RVPs.
Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Whiskeylake processor have an internal device called Camarillo
dedicated for thermal management support, turn it on so processor
thermal driver can be loaded.
BUG=N/A
TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0
can be seen.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7
Reviewed-on: https://review.coreboot.org/c/30858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
PC Engines apu1 has a 20 pin LPC header that allows connection of
external TPM module.
Add necessary Kconfig option and devicetree entry for TPM.
Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30354
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove double nesting of chip northbridge/amd.
There is requirement to keep SPD address map in
the same chip block with device 0:18.2.
Change-Id: Id3a161c54341d0c5c569ea6118ee6f890b7f62e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30735
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove double nesting of chip northbridge/amd.
There is requirement to keep SPD address map in
the same chip block with device 0:18.2.
Change-Id: Ib212f24c3d697a009d2ca8e2c77220de4bfb7573
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30733
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
conf pointer could be null, access it only if its not null.
Foundby=klocwork
BUG=N/A
TEST=N/A
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I0611e15d52edd8e69e4234b8ac602f35efba4015
Reviewed-on: https://review.coreboot.org/c/30862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
conf pointer could be null, access it only if its not null.
Foundby=klocwork
BUG=N/A
TEST=N/A
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I1b3d6f53d2bfd9845ad7def91c4e6ca92651d216
Reviewed-on: https://review.coreboot.org/c/30860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Add processor power limits control support to configure values.
BRANCH=None
BUG=b:122343940
TEST=Built and tested on Arcada system
Change-Id: I5990dc05b51481a0074855914cef20cf07378cde
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Wisley Chen