It would not be possible to set MTRR for range 1MiB to 4MiB.
Our RAMTOP is power of 2 and enabling cache for bottom
1MiB should cause no problems.
Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15238
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Required EHCI state is maintained as a CAR_GLOBAL to have it
properly migrated.
Change-Id: I8df413bec6faae4952670710c8ac804e0331c966
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15236
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reference to CACHE_AS_RAM was from the days we had
romcc boards using socket_mPGA605.
Change-Id: If397db83a01adeda4dd18d8b4c6e89bf0984264a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15224
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Implement function that automatically converts a SELF payload,
extracted from the CBFS, into an ELF file.
The code has been tested on the following payloads:
Working: GRUB, FILO, SeaBIOS, nvramcui, coreinfo and tint
Currently not working: none
Change-Id: I51599e65419bfa4ada8fe24b119acb20c9936227
Signed-off-by: Antonello Dettori <dettori.an@gmail.com>
Reviewed-on: https://review.coreboot.org/15139
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Allow to write multiple phdrs, one for each non-consecutive section
of the ELF.
Previously it only worked for ELFs contaning a single
program header.
Change-Id: If6f95e999373a0cab4414b811e8ced4c93c67c30
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15215
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This is more of ACPI S3 resume and x86 definition than CBMEM.
Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15190
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This Kconfig is deprecated, new platforms need to locate
ramstage stack in CBMEM instead.
Change-Id: I20ece297302321337cc2ce17fdef0c55242a4fc3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15189
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Checksum is calculated by using 2s complement method. 8-bit sum of the
entire subpart directory from first byte of header to last byte of last
partition directory entry.
BUG=chrome-os-partner:53508
Change-Id: I991d79dfdb5331ab732bf0d71cf8223d63426fa8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15200
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that the flash size is increased to 16MiB, add RW_NVRAM and
RW_LEGACY sections to chromeos.fmd file.
BUG=chrome-os-partner:54390
Change-Id: I6c79d35295c4bc774f05f8045ac920474d7a791f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15192
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to
upstream, using google/guado as a baseline.
original source:
branch firmware-rikku-6301.110.B
commit 2e71207 [CHERRY-PICK: broadwell: Update to microcode 0x1F]
TEST=built and booted Linux on rikku with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.bin)
external reference code (refcode.elf)
Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12802
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
CBMEM console stores all the console logs in CBMEM. Address of this
location in CBMEM where console logs are stored needs to be passed up to
OS using GNVS.
1. Add CBMC to GNVS fields in globalnvs.asl
2. Add cbmc member to global_nvs_t structure in nvs.h
3. Initialize gnvs->cbmc to address of cbmem console
BUG=chrome-os-partner:54342
Change-Id: Idcd4573e626fa433c1623bdcbe29921de64539b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
FSP methods may require reset under certain conditions. That is indicated
by returning specific return code. Add the missing return status codes.
BUG=chrome-os-partner:54149
BRANCH=none
TEST=none
Change-Id: I460353c5f835548a98255bd3e11dbfd08260ea52
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Update EMMC DLL setting for reef board, after that system can
boot up into EMMC successfully.
BUG=chrome-os-partner:54228
TEST=Boot up into EMMC and check with Rootdev
Change-Id: I614cd624dce9069c5565599a955f87906bcea53b
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/15156
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected.
This is the first piece in supporting FSP 2.0. Move esraminit from
romstage into the bootblock. Replace cache_as_ram with
car_stage_entry.S and code in romstage.c
TEST=Build and run on Galileo Gen2
Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15132
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable uses of a common bootblock_pre_c_entry routine. Pass in TSC
value as a uint64_t value.
TEST=Build for amenia and Galileo Gen2
Change-Id: I8be2e079ababb2cf1f9b7e6293f93e7c778761a1
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15124
Tested-by: build bot (Jenkins)
Reviewed-by: Lee Leahy <lpleahyjr@gmail.com>
If a bridge has the primary bus equal to the secondary bus the
busmaster_disable_on_bus() will infinitely call itself. Avoid the
inifinite recursion by checking current bus number against the
secondary bus number.
BUG=chrome-os-partner:54262
TEST=Ran on reef. Able to actually get the chipset to assert SLP_Sx
signals which means no more infinite recursion.
Change-Id: I52b21fbba24e6a652ea8f9f87f5f49f60109c8f2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15157
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Like other boards there will likely be information needed from
GNVS in the SMM handler. Therefore, it's important that the point
is stashed accordingly.
BUG=chrome-os-partner:54275
TEST=Noted GNVS messages from SMM console on reef.
Change-Id: If12b69731330a1e0af7f8fe880635e5ffd02d715
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15152
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The UART support is needed in SMM in order for DEBUG_SMI to
function.
BUG=chrome-os-partner:54262
TEST=Ran on reef with DEBUG_SMI enabled. Can observed SMI messages.
Change-Id: Ibd6b12e27d5776046b400adf72f24133b9e54af8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15151
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
It appears that PM1 is not wired up to the SMI status register, but
it does definitely cause SMIs to trigger. Therefore, provide a fake
PM1 status bit by checking the power button status when SMI status
is indicating no status as well as the PM1 control indicating that
SCI mode is not enabled.
BUG=chrome-os-partner:54262
TEST=Smashed power button on reef to cause SMI in firmware. No longer
loops infinitely with constant SMIs firing.
Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15155
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Provide the bit definitions for the SMI status register. Also,
utilize them which means deleting some of the handlers that can't
exist because there are no status bits.
BUG=chrome-os-partner:54262
Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15154
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.
Tested on Sandybridge Lenovo T520.
Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. The checksum method that was documented is not correct. So, no use
filling in a value based on wrong calculations. This can be added back
once updated information is available.
2. Checksum does not seem to affect the booting up of SoC. So, fill in 0
for now.
Change-Id: I0e49ac8e0e04abb6d7c9be70323612bdef309975
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15145
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Update pack and header order and mark the entries as mandatory and
recommended w.r.t. ordering (mandatory = essential for booting,
recommended = okay to change, but this config is tested and known to work).
Change-Id: Ia089bdaa0703de830bb9553130caf91a3665d2c4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15144
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since the HTIF is a non-standard interface, and coreboot already has a
8250 driver, I started implementing an 8250 core for spike[1].
[1]: https://github.com/riscv/riscv-isa-sim/pull/53
Change-Id: I84adc1169474baa8cc5837358a8ad3d184cfa51b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15150
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In the default (medlow) code model, pointers are loaded with a lui, addi
instruction sequence:
lui a0, 0xNNNNN
addi a0, a0, 0xNNN
Since lui sign-extends bits 32-63 from bit 31 on RV64, lui/addi can't
load pointers just above 0x80000000, where RISC-V's RAM now lives.
The medany code model gets around this restriction by loading pointers
trough auipc and addi:
auipc a0, 0xNNNNN
addi a0, a0, 0xNNN
This way, any pointer within the current pc ±2G can be loaded, which is
by far sufficient for coreboot.
Change-Id: I77350d9218a687284c1337d987765553cf915a22
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15148
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The uart8250mem driver needs it.
Change-Id: I09e6a17cedf8a4045f008f5a0d225055d745e8db
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15147
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Due to USB LDO issue in current steppings, cold reboot needs to be
temporarily disabled. Thus, hard_reset call should be the same as
soft_reset.
Once future steppings are available INTEL_COMMON_RESET can be enabled again.
Change-Id: If0ec56db3864d500acc93d2b363a78a6cd7632da
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15143
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update the Galileo board implementation checklist.
TEST=Build and run on Galileo Gen2
Change-Id: I1c88e9500d304273a3176d8b034a805920aab9bb
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15137
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Remove code duplication and use the common function
store_current_mrc_cache instead.
No functionality is changed.
Tested on Sandybridge Lenovo T520.
Change-Id: I4aa5463f1b1d5e1afbe44b4bfc659524d86204db
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15074
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Sometimes we need to pass board specific messages to BL31,
so that BL31 can do board specific operation based on
common code.
BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru
Change-Id: I096878699c6e6933debdf2fb3423734f538691ae
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: af83e1b
Original-Change-Id: Ib7585ce7d3bf01d3ce53b388bf9bd60f3b65f5f1
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349700
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15116
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Kyösti Mälkki