This wasn't done previously because not all files in the
src directory had the correct headers. Doing this earlier
would have broken the build.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ia6d7a7a17116e4c8e55354783085355fd45ff87a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66505
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
- Set pre-wake randomization time (DPA) to 100
BUG=b:241349500
TEST=build FW and checked fsp log.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Id4a1540de8c3ee74695631acc8181dcc446fe137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66783
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add FW_CONFIG probe based on pujjoteen boxster of below devices:
LTE, SD card, stylus, WFC camera, AUDIO
BUG=b:236158122
TEST=Boot to OS and verify that above devices are set based on
fw_cofnig.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I49fc5461e7affba68a6b89bf166c84598fbfa088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66741
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ghost has two amps and address are 0x3c and 0x3d.
BUG=b:231581723
BRANCH=firmware-brya-14505.B
TEST=max98396 driver can get the DSD property correctly.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3b6a331ca42e97f984f3a585726c02452bb067f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Starting vboot earlier in bootblock instead of romstage is usually
preferred (smaller root of trust, among other things). Therefore
unselect VBOOT_STARTS_IN_ROMSTAGE for broadwell. Also remove the unused
BROADWELL_VBOOT_IN_BOOTBLOCK option.
Change-Id: If8feea403ee4cd3a16ed8cb0faf9f4ccb34feaaf
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The I2C config was unnecessarily placed in the overridetree. As we
prepare for fanout, this is going to cause unnecessary noisy changes.
Move the I2C config to the devicetree to avoid this.
BUG=None
TEST=Build
Change-Id: I09ad5c911a0fd00274761cb71e9b659b47cd6da1
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66802
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCIe spec explicitly states that the bottom-two bits of the next
offset are reserved for future use and should be masked. We can also
change the loop condition to avoid wrong offsets below 0x100 (exten-
ded capabilities always reside in the extended config space).
The whole patch series was tested on Google Samus and keeps the L1ss
configuration of the WiFi device in tact.
Change-Id: I0b622a0ce0a4a1127d266226ade0ec1e66e9fb79
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66459
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add some inline functions for the bit-wise operations, change the loop
body to an if-bail-out style and remove stateful variables.
Change-Id: Ia8db915f375737064e3486d313383d9b6c3eb2b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66458
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Keeping these checks in generic code seems rather dangerous.
In theory, it could lead to endless loops even for compliant
devices, if we accidentally detect arbitrary register contents
as capability and use them as a pointer to another one. Not
to forget that the register reads can have side effects.
All users of this `cafe` have been converted to use
pciexp_find_ext_vendor_cap().
Change-Id: I70d21534e04282a4156572a290b83c46be085e0c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66456
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We have this quirk in our tree since the introduction of L1-substate
support[1]. The way we searched for this capability was rather crude:
We simply assumed that it would show up in the first data word of
another capability.
As it turned out that it is actually a proper vendor-specific capa-
bility that we are looking for, we can drop some of the mystic code.
This was confirmed to work on the device that was originally used
during development, Google/Samus.
[1] commit 31c6e632cf (PCIe: Add L1 Sub-State support.)
Change-Id: I886fb96e9a92387bc0e2a7feb746f7842cee5476
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Vendors can choose to add non-standard capabilities inside a
Vendor-Specific Extended Capability. These are identified by
the Extended Capability ID 0x0b.
Change-Id: Idd6dd0e98bd53b19077afdd4c402114578bec966
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move the `offset` parameter into pciexp_find_extended_cap(). If it's
called with `0`, we start a new search. If it's an existing offset,
we continue the search.
This makes it easier to search for multiple occurences of a capa-
bility in a single loop.
Change-Id: I80115372a82523b90460d97f0fd0fa565c3f56cb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Now that we have functionality to get the minimal and nominal
frequencies, the corresponding fields in the CPPC config can now be
populated. If the HOB isn't present and/or the frequency values
could not be obtained, CPPC_UNSUPPORTED is still used; otherwise the
HOB-provided frequency in MHz is used for those two fields.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Id3257690a3388d44ceceb7ac4f1db3d49e195caa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66551
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add common AMD FSP functionality to get the nominal and minimal CPU core
CPPC frequencies. Those functions will be used in the _CPC ACPI object
generation in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: I68ebdf610795d2673e0118a732f54f5f719b73c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66550
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
xhci.asl places the SS ports at 11-14, following HS ports 1-10. However,
for Nissa, the kernel detects 12 HS ports 1-12 and 4 SS ports at 13-16,
resulting in the PLD intended for SS ports 1 and 2 being associated with
HS ports 11 and 12.
Changing the asl for SS to 13-16 makes locations associate correctly and
peering work.
BUG=b:234544025
BRANCH=firmware-brya-14505.B
TEST=manually verified on Nissa and Brya devices
Change-Id: I57aef771a7ff086b71a9e90b81e1a3635f832b2f
Signed-off-by: Adam Mills <adamjmills@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66590
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMI sleep entry handler will access the SMN space via the index/data
register at PCI config space offsets 0xb8 and 0xbc of the device at bus
0, device 0, function 0. This register pair is also used by other
software components running on the x86 cores after boot, so it should be
saved and restored at the beginning/end of the SMI handler if it
accesses SMN. The sleep entry SMI handler is a special case, since the
OS is already done at the moment we enter the sleep SMI handler which is
the last code that gets run on the x86 cores before entering S3/4/5.
BUG=b:237004699
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0980562ef8a61489082a81c71d6d00d0786d68cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
EN_PP3300_EMMC will change to GPP_A21 to meet DP++ function and it based on Moli GPIO Table_20220803.xlsx. But it will let current eMMC skus can't boot into OS, so use the board_ver to decide which gpio table return and set override_gpio_table_id2 and early_gpio_table_id2 based on Moli GPIO Table_20220803.xlsx
1. set GPP_A21 to EN_PP3300_EMMC
2. set GPP_A22 to NC
3. set GPP_E20 to DDIC_DP_CTRCLK
4. set GPP_E21 to DDIC_DP_CTRLDATA
BUG=b:241370405
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I0a2c8684d140738f43658cd6075ed083eee44e65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8534305e4e973c975ad271b181a2ea767c840ae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66686
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the winterhold variant of the skyrim reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:240970782
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_WINTERHOLD
Signed-off-by: Isaac Lee <isaaclee@google.com>
Change-Id: I0e16f0a674aa3f4687cd82d5840a3c2087148a51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66620
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit I73b7ddec50936f7836f915f459ca0bdc0777cb22.
Revert change to disable post codes. Post codes were initially disabled
because of an issue with initialization within the SMU.
BUG=b:227201571
TEST=Build and boot to OS in Skyrim.
Change-Id: I2a2bd2252a103c682b5d4ad5ecd1da42b3744083
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66092
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is no longer in the tree.
Change-Id: Ie4a626ce85fe0dc2b2d826dd8830a8e80ec331aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
By moving the large wait for FBVDD discharge from PGOF
to PGON, the whole time may be avoided if enough time has
elapsed between the successive calls.
BUG=b:239719056
TEST=With Nvidia test software, verify ACPI prints
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I891aa14f120d58c45b8965038a9d2f2a417b3f3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Now that the virtual wire situation is figured out, the GC6 sequence
is updated to match the latest HW design guide from Nvidia. This
allows Nvidia test software to (mostly) successfully execute the GC6
test, but with some PCIe AER errors.
BUG=b:214581763
TEST=tested with Nvidia test software
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia094c4fa9b4db094a59b9b6f02be1a649ee8569b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Since the VW GPIOs are not in the baseboard GPIO table, they do
not actually override anything, and hence do not actually get
programmed. This patch moves the programming from the ramstage
table to the bootblock table so they get programmed.
BUG=b:214581763
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I42db44d38df20dd2695921e2f252be163f6b17f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725
on mainboards with a chipset not yet released on 2011-07-25. Since this
comment is most likely to have been copy-pasted from other boards, drop
it from boards which use a chipset newer than Sandy/Ivy Bridge.
Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This patch drops explicit usage of the address-of operator ('&') while
passing the function pointer (argument 0) to the
`mp_run_on_all_cpus` API.
Note: It's just cosmetic change without any real difference in the operation.
TEST=Able to build and boot Google/Kano where CPU feature programming
is successful on all logical processors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2c77959a76d2240ad1bfb7a9d7b9db7e8aee42f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66685
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
If we already encountered the last extended capability in the
list, we'd call pciexp_get_ext_cap_offset() with `offset == 0`.
So it also needs to check if the passed offset is valid.
As there were no callers of pciexp_find_next_extended_cap()
yet, pciexp_get_ext_cap_offset() was only ever called with
`PCIE_EXT_CAP_OFFSET`.
Change-Id: I155c4691a34ff16661919913a3446fa915ac535e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Checking if the return value of the fsp_find_extension_hob_by_guid call
is NULL should make the code a bit easier to read.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6bdb07eab6da80f46c57f5d7b3c894b41ac23b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Different guybrush boards have different TPM IRQs. This change passes in
the correct GPIO to the TPM.
BUG=b:241824257
TEST=Boot guybrush and verify GPIO 3 was passed and that OEM Crypto test
passes
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I61954fa4493fd56e528b616ca65166a31917f557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The PSP currently uses a hard coded GPIO for the TPM IRQ. Not all board
versions use the same GPIO. This method allows the mainboard to pass
in the correct GPIO.
BUG=b:241824257
TEST=Boot guybrush and verify PSP message prints
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie05d095d7f141d6a526d08fbf25eb2652e96aa49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Since bootblock_soc_early_init gets called before
bootblock_mainboard_early_init which does the early GPIO setup, external
I2C level shifters that are controlled by GPIOs might not be enabled yet.
Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure
that the early GPIO setup is already done when reset_i2c_peripherals is
called.
Haven't probed any SCL signal on the non-SoC side of the I2C level
shifters yet, but the waveform on the SCL pin of I2C3 on the SoC of a
barla/careena Chromebook doesn't have the longer than expected SCL
pulses any more.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Logo.bmp is overwritten with a custom one from coreboot. This needs to
be restored before the branch is updated otherwise git will report that
the repository is dirty.
Move this to the update recipe so that will always be done for any
recipe that needs to update the branch.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I85bf753a47d9e70d6555dec9a539e8ed7395bead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66355
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Steelix uses ps8640 for board revision < 2, and uses anx7625 for newer
revisions. So we use board_id to distinguish anx7625 and ps8640.
BUG=b:242018373
TEST=firmware bootsplash is shown on eDP panel of steelix.
Change-Id: Ia6907d2e6e290375946afb13176ab9a26dedd671
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Add support for SocInfo in coreboot. The API socinfo_modem_supported is
added to help to differentiate between LTE and WiFi SKUs.
BUG=b:232302324
TEST=Validate boards are detected correctly on LTE and Wifi SKUs
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: I61047ad49772c3796ba403cafde311ad184a4093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Add a new driver for NXP UWB SR1xx (e.g., SR150) device.
The driver was originally written by Tim Wawrzynczak as a WIP in
CL:3503703, and was based on drivers/spi/acpi.
BUG=b:240607130
BRANCH=firmware-brya-14505.B
TEST=On ghost (with follow-up CL), patch linux with NXP's pending
drivers
-> UWB device is probed and can respond to a simple hello
packet
Co-authored-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I5b1b0a5c1b48d0b09e7ab5f2ea6b6bc2fba2a7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66466
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add OV 5675 MIPI camera to ghost, sensor eeprom, and IPU device to
device tree. Enable config for MIPI camera.
BUG=b:241343306
BRANCH=firmware-brya-14505.B
TEST=with ghost overlay changes, camera in camera app works
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: Ie079e43ae0f34efba396331922ea4a89eda72128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This reverts commit 8b1c6c6cb3. With
updated APCB, eSPI configuration carries over to bootblock. Hence eSPI
does not need to be re-initialized in bootblock.
BUG=b:241426419
TEST=Build and boot to OS in Skyrim with PSP verstage.
Cq-Depend: chrome-internal:4929421
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I426b07329d4a0154d915381c99dcc9746b7a3d7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Introduce the `BROADWELL_LPDDR3` Kconfig option along with some wrapper
code to allow mainboards using LPDDR3 DRAM to supply the DQ/DQS maps to
chipset code without having to use `pei_data`. The only mainboard using
LPDDR3 is Google Samus.
Change-Id: I0aaf0ace243c03600430c2a7ab6389a7b20cb432
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55812
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboards do not need to know about `pei_data` to tell northbridge code
where to find the SPD data. As done on Haswell, add the `mb_get_spd_map`
function and the `struct spd_info` type to retrieve SPD information from
mainboard code without having to use `pei_data` in said mainboard code.
Unlike Haswell MRC, Broadwell MRC uses all positions of the `spd_data`
array, not just the first. The placeholder SPD address for memory-down
seems to be different as well. Adapt the existing code to handle these
variations. Once complete, the abstraction layer for both MRC binaries
will have the same API.
Change-Id: I92a05003a319c354675368cae8e34980bd2f9e10
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The `ddr_refresh_2x` setting is already set in chipset code.
Change-Id: I76478689b3aa27c369a0413d9fbde03674d5e528
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55810
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no generic way to tell whether a mainboard has an EC or not.
Making Kconfig symbols for these options seems overkill, too. So, just
put them on the devicetree. Also, drop unnecessary assignments when the
board's current value is zero, as the struct defaults to zero already.
Change-Id: I8d3b352333bea7ea6f7b0f96d73e6c2d7d1a2cfb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55809
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The SPD file handling code is generic and can be used on any other
mainboard. Move it to chipset scope to enable code reuse.
Change-Id: I85b1460ccb82f0c1bf409db4a6b4c9355c25e76d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55808
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Introduce the `SPD_MEMORY_DOWN` macro to indicate that a slot is used
with memory-down. This enables computing the channel disable masks as
the bits for slots where the SPD address is zero. To preserve current
behavior, zero the SPD addresses for memory-down slots afterwards.
Change-Id: I75b7be7c72062d1a26cfc7b09b79de62de0a9cea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55807
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is the version of genrelnotes that was used to help with the
4.16 release.
- Fix shellcheck issues.
- Send messages for the user to STDERR.
- Add recent platforms
- Handle symbolic links to the git repo.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2204793a5d1cc5792d0720d2bbfb172bb6020dd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
To generate a complete _CPC ACPI object, coreboot needs the minimal and
nominal core speed values which are specific to the CPU and not only the
CPU family. Since this is done by an undocumented mechanism, FSP has to
do this and puts the information we need into a HOB. This adds the HOB
GUID and the structure of the HOB data.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: Ibf338c32de367a3fd57695873da1625338fa196d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66549
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Martin Roth