Commit Graph

5925 Commits

Author SHA1 Message Date
Noe Rubinstein 03169d3e1c Replace while with do; while to avoid repetition
Cosmetic only; replaces some 'while' loops with 'do; while' loops to
avoid repetition.

Replacement performed by the Ruby expression:
t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
	"\\1do \\2\n\\1\\3;")

Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd
Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/183
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09 11:40:48 +02:00
Patrick Georgi ac624a638d Crank up CPU speed on Intel Core and Core2 CPUs
The CPUs start on their slowest speed, and were left that way by
coreboot. This change will speed up coreboot a bit, as well as
systems that don't change the clock for whatever reason.

Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/176
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09 11:40:30 +02:00
Stefan Reinauer 7981b940a6 Report GSE chipset and warn if the code has been compiled for the wrong chipset.
It would be nicer to unify the code so that it does all detection at runtime
instead of compile time (but that would also significantly increase code size)
so if someone else wants to give it a shot...

Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/184
Tested-by: build bot (Jenkins)
2011-09-09 11:40:04 +02:00
Rudolf Marek 8679e52b96 Add support utils for tracing
Following patch adds a userspace util genprof
which is able to convert the console printed
traces to gmon.out file used by gprof & friends.
The log2dress will replace the adresses in logfile
with a line numbers.

Change-Id: I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/179
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:27:57 +02:00
Rudolf Marek 7f0e93060e Add support for the tracing infastructure in coreboot.
The compiler is forced to emmit special functions on every
entry/exit of the function. Add a compile time option
to support it. Function entries will be printed in
the console. The CONFIG_TRACE has more documentation.

Patch for userspace tools will follow.

Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/178
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:26:47 +02:00
Kerry She f73535c089 AMD F14 Rev C0 update
Add AMD Family14 Rev C0 cpu id

Change-Id: Iacd1c7b20e889da61a2085188766285f27e5c018
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/160
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:10:29 +02:00
Kerry She 6209c8299a AMD SB800 southbridge update
This patch enables access to the registers of the hardware monitor
logical device in the superio via isa ports 0x295/0x296.
Previously this was not enabled in the SB8xx LPC device.
This is required for initialisation in init_hwm() in
src/superio/winbond/w83627hf/superio.c and also by OS-level
sensor monitoring such as lm-sensors to access temperature,
fan monitoring and control and voltage registers.
asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.

Change-Id: I2176885549277b335c0c41b48457d09b9b76b703
Signed-off-by: Per Hansen <perh52@runbox.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/159
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:10:05 +02:00
Kerry She feed329a0c AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.

Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:08:57 +02:00
Wang Qing Pei 16d3ec6a58 Adjust some code/comment of sb700 sata init
The inline comment of sata_init function seems not placed correctly.
Rearrange it.

Change-Id: I63480da60e51cdc68e64c302ad2d8a6197e288f6
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/186
Tested-by: build bot (Jenkins)
2011-09-04 12:22:09 +02:00
Wang Qing Pei f6e37316d0 Disable dev3 on ma78gm-us2h
Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot.

Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/187
Tested-by: build bot (Jenkins)
2011-09-04 12:22:00 +02:00
Peter Stuge 0e8ee81edb buildgcc: Do not download GDB source code if run with --skip-gdb
Change-Id: Ida3680418fdd3136752d51cc19f3e14111c12131
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/175
Tested-by: build bot (Jenkins)
2011-08-29 22:42:24 +02:00
Sven Schnelle ebc28095ad Add a few more patterns to .gitignore
Change-Id: If7c1c6d9a96dd788bacee72b6e18a435069cad6e
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/172
Tested-by: build bot (Jenkins)
2011-08-27 09:44:50 +02:00
Sven Schnelle 054849dc6b Add dirty flag to git describe
git describe knows --dirty, which adds -dirty to the verion number
if the tree contains uncommited changes. We should add this flag
to make it obvious that the COREBOOT_VERSION might be misleading.
This is especially important as this version number is now used
in the SMBIOS data structures.

Change-Id: If4c608c7455e1bbf0cc530c6299fa00eb0fe4d58
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/173
Tested-by: build bot (Jenkins)
2011-08-27 09:44:34 +02:00
Sven Schnelle ff31692e08 X60/T60: remove obsolete dmi.h
Change-Id: Id0e8bcc1b93a629f0620b84a060d7ff99a82de78
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/174
Tested-by: build bot (Jenkins)
2011-08-26 22:35:43 +02:00
Sven Schnelle 164bcfdd1b Add automatic SMBIOS table generation
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/152
Tested-by: build bot (Jenkins)
2011-08-26 20:08:52 +02:00
Alec Ari bc081cdf6d Minor ma785gmt clean-up
Change-Id: I9e889a6c475fb3283fa11f8b3de5baaf54235589
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/167
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-25 15:43:10 +02:00
Alec Ari e1562bdccb Fix up various dsdt.asl files
Change-Id: I46eb27847deb3a903ac9af347992a9954e50ff6e
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/166
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-25 15:42:14 +02:00
Alec Ari 0e615007ec Remove dead code
Remove dead code, copy and pasted from
tilapia's mainboard.c file into various
asus mainboard.c files

Change-Id: Ic715ccaad8ac0210401d4a99ecb11e943f6afe58
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/168
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-24 19:04:54 +02:00
Peter Stuge 09377b7d3f buildgcc: Remove all bashisms, making the script run also on BSD
Use sed instead of ${variable:start:length} and ${#variable}
Use single = in string comparisons
Use `eval echo '$'$variable` instead of ${!variable}
Use > file 2>&1 instead of &> file
Use readlink -f to expand the path of GCC configure

Change-Id: Idc7dfcea3922f55630a6855acdb19e36582708bd
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/165
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2011-08-21 08:47:00 +02:00
Peter Stuge 875b9b197f Use git describe to set KERNELVERSION
Change-Id: Id579b19fc38c7ca2b98ad1e87aaec71c070a9178
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/163
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-21 07:40:39 +02:00
Peter Stuge b98dbfb97e buildgcc: Fix typo in check for failed iasl build
Change-Id: I3e90b90e807ae775ac66af160a0f8547dcb3597a
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/164
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-21 07:39:57 +02:00
Sven Schnelle 6901b561eb Lenovo H8: Always clear audio mute
The mute bit is set by ACPI before poweroff/going to suspend.
So clear it after resume, to have working volume control
even if the ACPI doesn't clear it on resume.

OSPM should control Audio mute with ec bit 0x30:6, so it is
safe to clear this bit even if the user has audio muted.

Change-Id: I18bebe532bf21cfb61b3d294a396bf15012f9f1a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/162
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2011-08-19 14:17:06 +02:00
Patrick Georgi b09e748f87 libpayload: export get_cbfs_header()
Keep in sync with coreboot's version.

Change-Id: I8a253446bd3b2ce9d05c6076a3f49f0260ecd5f9
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/158
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-18 22:02:53 +02:00
Sven Schnelle 8d0b86c9ab X60: use EC events 0x50/0x58 instead of GPIO GPE for Docking/Undocking
Change-Id: I674e5166f5fb7ba299e6f1231f30434a5bf731c5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/161
Tested-by: build bot (Jenkins)
2011-08-18 20:50:55 +02:00
Sven Schnelle d819853f85 export get_cbfs_header()
Change-Id: I4b6afcee3d0d169e03165a7fb48cfaef2e8253e2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/157
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-18 11:34:53 +02:00
Patrick Georgi c643fdd157 libpayload: Some more compatibility (for flashrom)
libpci defines an arbitrary set of PCI vendor IDs, flashrom uses the
Intel definition. Add it.

flashrom also requires inttypes.h, so add the OpenBSD version

Change-Id: I9bffd8193f635c375ac4d6b6eae8d3d876b95f5f
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/154
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-17 16:26:20 +02:00
Patrick Georgi 8bbdb61113 libpayload: EHCI registers are volatile
Some gcc versions seem to honor volatile at different places in a
struct declaration.

Change-Id: I0df2a3fb2eff4cee8cc1b8ac15d9cd9b86178752
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/155
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-16 21:56:32 +02:00
Jonathan A. Kollasch 4b8f779278 crossgcc: invoke buildgcc with bash, instead of relying on #!/bin/bash
Change-Id: I09192e57e2535b2f8f98cabeb755f10c5520c499
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/151
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2011-08-14 08:03:55 +02:00
Jonathan A. Kollasch f44bb4f4c1 buildgcc: improve portability
`cp --remove-destination` isn't as portable as `rm -f` and `cp`.

Change-Id: Ib05bfc121f7a0b467f8104920e14fbd02191585f
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/150
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-12 09:24:50 +02:00
Marc Jones 2aac3f6c51 Add iasl to buldgcc and rev the version.
Change-Id: If9144cdf088f16bc3974a1784a442a1fd12ac75b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/147
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-10 01:10:40 +02:00
Alexandru Gagniuc 1a2b318625 Do not compile nuvoton superio for all board
The nuvoton WPCM450 code is compiled for all boards regardless of
whether or not they use it. Compile it only for boards needing it.

Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/129
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-09 20:11:01 +02:00
efdesign98 9f6cbde890 AMD Family 14 Agesa warning fix
This change fixes one Agesa warning.  Originally this commit
included some changes that I later deemed unnecessary.

Change-Id: I31ad13bb92509228b89921561c340c95e5136370
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/132
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-09 19:59:49 +02:00
Jonathan A. Kollasch ebbfbd5911 ms7135: add ACPI support
Change-Id: I64a74d3dc0ea2d006ed4b25657d531fb243c2993
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/140
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-06 18:17:07 +02:00
efdesign98 84cbce2364 Update AMD F14 Agesa to support Rev C0 cpus
This change updates the AMD Agesa code to support the Family 14
rev C0 cpus.  It also fixes (again) a ton of warnings, although
not all of them are gone.  The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.

Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-06 18:06:18 +02:00
Jonathan A. Kollasch 0df0e14fb5 Add voltage control of southbridge and RAM on ms7135
Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/126
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04 17:28:36 +02:00
Keith Hui e089a3f68d northbridge/intel/i440bx: Registered SDRAM modules support and fixes
Adds support for initializing registered SDRAM modules on
Intel 440BX northbridge.

Drops unneeded romcc-inspired programming tricks.

Only set nbxecc flags (see 440BX datasheet, page 3-16) when
a non-ECC module has been detected in a row via SPD; also
drops an unneeded intermediate variable used in setting them.

Boot tested on ASUS P2B-LS with regular and registered ECC
SDRAM under Linux and memtest86+.

Change-Id: Idc99d49567cca55f819d6b0e98952b1c3256498a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: http://review.coreboot.org/128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04 08:15:49 +02:00
Patrick Georgi 6de1ee4a30 libpayload: Add liblzma, libcbfs
Add cbfs core from coreboot into libpayload, and to support lzma decode,
add coreboot's lzma code, too. Carl-Daniel agreed to relicense the
lzmadecode wrapper as BSD-l, solving licensing problems.

Change-Id: Id28990fe7e951d99447e265a4880d70a8f208dd2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/115
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-04 08:11:21 +02:00
Patrick Georgi b88351537b split CBFS support into shared core and extended functions
The core is data structures and basic file finding capabilities,
while option ROM handling, and loading stages and payloads is
"extended".

The core is rewritten to be BSD-l (its header already was), so
can be copied to libpayload verbatim.
It's also more robust in finding files in corrupted images, eg.
after partial erase or update.

Change-Id: Ic6923debf8bdf3c67c75746d3b31f3addab3dd74
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/114
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04 08:10:54 +02:00
Patrick Georgi 3b77b723ca libpayload: Add PDCurses and ncurses' libform/libmenu
PDCurses provides an alternative implementation of the curses library
standard in addition to tinycurses.
Where tinycurses is really tiny, PDCurses is more complete and provides
virtually unlimited windows and the full API.
The PDCurses code is brought in "vanilla", with all local changes
residing in curses/pdcurses-backend/

In addition to a curses library, this change also provides libpanel (as
part of the PDCurses code), and libform and libmenu which were derived
from ncurses-5.9.
As they rely on ncurses internals (and PDCurses is not ncurses), more
changes were required for these libraries to work.

The build system is extended to install the right set of header files
depending on the selected curses implementation.

Change-Id: I9e5b920f94b6510da01da2f656196a993170d1c5
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/106
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-04 08:10:41 +02:00
Keith Hui 1ac19e28ee cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
Bring from coreboot v1 support for initializing L2 cache on Slot 1
Pentium II/III CPUs, code names Klamath, Deschutes and Katmai.

Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with
Pentium III 600MHz, Katmai core.

Also add missing include of model_68x in slot_1, to address a
similar problem fixed for model_6bx by r5945.

Also change Deschutes CPU init sequence to match Katmai.

Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: http://review.coreboot.org/122
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04 08:10:12 +02:00
Jonathan A. Kollasch 8e9f156f48 Remove debugging code, or convert it to be selected by kconfig
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/130
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-03 21:28:14 +02:00
Jonathan A. Kollasch c2ffc6739c Use preferred style of fixed-width integer types
Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/125
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-08-03 17:56:42 +02:00
Patrick Georgi ce37765772 crossgcc: update w32api
crossgcc also needs lzma support as w32api is distributed in .tar.lzma

Change-Id: Ia1938fa30262fe0c8bd655a08f9dc731a02e46ba
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/120
Tested-by: build bot (Jenkins)
2011-07-26 21:10:18 +02:00
Patrick Georgi 68df804282 buildgcc: Break if parts of the toolchain are missing
We test for the presence of a couple of tools and even print an error.
But the tool didn't stop there.

Change-Id: I40dcf7894408ea7b24d5f68c76df4b7541f469bd
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/111
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-26 16:35:54 +02:00
efdesign98 3ddb6b85f1 Add xhcbios and ahcibios rom handling
This change adds xhci and ahci bios rom handling that
is similar to the vgabios rom handling in the arch/x86
Makefile.inc to the Persimmon and Torpedo mainboards.
It also adds the basis for AHCI BIOS rom handling to
the Persimmon Kconfig.

Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/109
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 20:02:22 +02:00
efdesign98 95b6611c18 Add the SuperMicro H8QGI platform
This set adds support for the SuperMicro H8QGI mainboard.
It is a publicly available 4 socket board using AMD Family
10 cpus and AMD SR5650 and SB700 bridges.

Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/108
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 19:58:55 +02:00
efdesign98 3cab93ce8e Add SSE3 dependent code
This change separates out changes that were initially found
in the commit for XHCI and AHCI changes to "arch/x86/Makefile.
inc".  It also corrects a comment.  The SSE3 dependent code
adds a pair of CR4 access functions and a blob of code that
re-sets CR4.OSFXSR and CR4.OSXMMEXCPT.

Change-Id: Id97256978da81589d97dcae97981a049101b5258
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/113
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-22 08:22:59 +02:00
efdesign98 00c8c4a316 Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes.  The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements.  This particular change
affects all mainboards that use the SB700, and their changes are
include herein.  These mainboards are:
  Advansus a785e,
  AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
  Asrock 939a785gmh,
  Asus m4a78-em, m4a785-m,
  Gigabyte ma785gm,
  Iei Kino-780am2-fam10
  Jetway pa78vm5
  Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.

Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 00:20:59 +02:00
Tadas Slotkus 09ea8ea1a7 Libpayload: default DESTDIR for 'make install'
If you would try download FILO via svn, then you probably
get error message about libpayload install. This enables
manually installing libpayload in legacy style :)

Change-Id: I9f52be939303c5913611f21477d681e11d286382
Signed-off-by: Tadas Slotkus <devtadas@gmail.com>
Reviewed-on: http://review.coreboot.org/102
Tested-by: build bot (Jenkins)
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-21 08:15:45 +02:00
Patrick Georgi dd3e690220 libpayload: Provide dummy getenv()
Change-Id: I419fcb16e0b10dee9195072e0e6befa6c9e61a69
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/105
Tested-by: build bot (Jenkins)
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-20 10:02:19 +02:00