Commit Graph

15422 Commits

Author SHA1 Message Date
Timothy Pearson 785b3eb6e8 device/pciexp_device: Tune PCIe bridges before scanning children
Change-Id: Ieccafe8864d622c651e6a524e9898505ded15e54
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12187
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-25 04:49:31 +01:00
Timothy Pearson 7d8a478e70 device/pci_device: Set bridge primary bus number before scanning
Certain devices, such as the Intel 82575GB, contain multiple nested
PCIe bridges (for example the PES12N3A).  Coreboot does not set
the primary bus number of the lower bridges, causing upstream
forwarding failure.  This in turn causes coreboot to fail to find
the lowest devices (in this case the NICs), and as a result the
required resources are not allocated and the NICs do not function.

Change-Id: I4fd3aa21a04dbe89ac6a5995e7707af914d432b1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12186
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-25 04:47:10 +01:00
Timothy Pearson d657446884 cpu/amd/car: remove PRINTK_IN_CAR #define that was hardcoded to 1
Change-Id: I5139ee222a0dca7f8e62612a39d30cad7976b505
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12184
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-25 04:25:39 +01:00
Timothy Pearson 1c4508e77c cpu/amd: Add initial support for AMD Socket G34 processors
Change-Id: Iccd034f32c26513edd52ca3a11a30f61c362682d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11940
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-24 21:33:07 +02:00
Martin Roth 1fec04b47e util: add ectool, superiotool, and viatool to what-jenkins-does
Change-Id: Ib39ec8acee8de5678e06792323920d44a75e0ada
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12122
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24 10:56:02 +02:00
Martin Roth 917acb5656 util: update junit.xml target
- Display what's happening to the console as well as logging to the
junit.xml file.
- Log the clean in the junit.xml file so if it fails it doesn't just
appear to not have run the test.
- Run both clean and distclean (if distclean exists and runs clean,
this still only runs clean once) so that if distclean doesn't exist
the clean still happens.  Don't stop the build if the clean step
fails in case there's no distclean in the util makefile.
- Run the util builds multithreaded.  This saves a couple of seconds
and helps find dependency issues that might not be seen if building
single-threaded.

Change-Id: If895295c83faba98661b7c925b65fd436e06b834
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12121
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24 10:55:52 +02:00
Martin Roth 0be83c09a0 util: Update makefiles for junit testing
- Have clean remove junit.xml files.
- Remove junit.xml target from cbmem makefile - this is in the top
level Makefile.inc now.
- add distclean targets to makefiles.
- Make sure all makefiles have .PHONY set up.
- rm commands need -f or they will fail if the file they're trying
to remove doesn't exist, causing the build to fail.

Change-Id: I2f0635f2c0a9417e3377a90c8d67103323c4a72f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12120
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24 10:55:45 +02:00
Timothy Pearson 535452d154 southbridge/amd/sr5650: Fix hardcoded printk() function names in pcie.c
Change-Id: Idf1db091f1d1e40ce2f248bc25d662cf9608b27e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12179
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24 07:18:50 +02:00
Timothy Pearson 70f2736b8e southbridge/amd/sb700: Fix boot hang on ASUS KGPE-D16
Change-Id: I1d7d6715663a13ab94fd6d71808e35f0f7384d00
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11938
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24 07:17:21 +02:00
Timothy Pearson b27dfe9998 southbridge/amd/sb700/acpi: Add IDE / SATA ASL code
Change-Id: I507c93556dd66c3590c8ca11c06cd5b2dd7884c5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12176
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24 07:08:26 +02:00
Timothy Pearson 04cf449e77 drivers/aspeed: Add native text mode VGA support for the AST2050
Change-Id: I37763a59d2546cd0c0e57b31fdb7aa77c2c50bee
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11937
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2015-10-24 06:28:08 +02:00
Timothy Pearson c3fcdccb81 southbridge/amd/sr5650: Fix boot failure on ASUS KGPE-D16
Change-Id: Ia13ba58118a826e830a4dc6e2378b76110fcabad
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11939
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24 06:11:41 +02:00
Timothy Pearson f94ceb138f mainboard/asrock/e350m1: Update CMOS layout to match SIO changes
Change-Id: I3f1f33b50f788b6d57f1a7986c4bdb912426e4f0
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12125
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24 06:01:22 +02:00
Timothy Pearson 478575c049 lib/stack: Add stack overrun detection
Change-Id: I9a59fcb7cf221ae590a047c520e7aff99e23ecf1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11962
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-24 05:57:33 +02:00
Timothy Pearson d59dc4532b mainboard: Update mainboards using the w83795 sensor device
Update mainboards using the w83795 sensor device with sane default
values.  Note that in some cases the defaults may vary from the
defaults provided by the old driver, for example the default fan
speeds and control modes have changed as I do not have any information
on the correct sensor to fan mappings for these boards.

Change-Id: Id2ad6222d7a0f29483b022fa097d7d098c6b4122
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12124
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24 02:07:16 +02:00
Timothy Pearson f7e0a1aaaa drivers/i2c/w83795: Add option to use auxiliary SMBUS controller
Change-Id: I5a9b5eba992853b84b0cb6c3a1764edf42ac49b2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2015-10-24 02:06:52 +02:00
Timothy Pearson acbdade5cd southbridge/amd/sb700: Allow use of auxiliary SMBUS controller
Change-Id: I29ece10eeefc2c75a3829c169f1e1aede7194ec2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12079
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2015-10-24 02:01:17 +02:00
Timothy Pearson cab71b638f drivers/i2c/w83795: Add full support for core functions
Add full support for fan control, fan monitoring, and voltage
monitoring.  Fan speeds and functions are configurable via
each mainboard's devicetree.cb file.

NOTE: This patch effectively rewrites large portions of
the original driver.  You may need to re-verify correct
operation on your hardware if you were using the old
driver code.

Change-Id: I3e246af0e398d65ee43ea708060885c67fd7d202
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11936
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24 02:00:49 +02:00
Timothy Pearson 5a0efd255d southbridge/amd/sr5650: Add optional delay after link training
Certain devices (such as the LSI SAS 2008 controller) do not
respond to PCI probes immediately after link training.  If it
is known that such a device is likely to be installed allow the
mainboard to insert an appropriate delay.

Change-Id: Ibcd9426628cacd6f88e6e3fcbc2b3eb7e3a92081
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11991
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-10-24 01:44:43 +02:00
Timothy Pearson a693f524ca device/smbus: Avoid infinite loop if SMBUS device has wrong parent
If an SMBUS device in devicetree.cb is placed under a parent device
that does not have an SMBUS controller, coreboot will enter an
infinite loop and hang without printing any failure messages.

Modify the loop to exit under these conditions, allowing the failure
message to be printed.

Change-Id: I4c615f3c5b3908178b8223cb6620c393bbfb4e7f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12131
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
2015-10-24 01:28:08 +02:00
Paul Menzel ccc2af14c1 intelvbttool: Add Makefile
Add minimal Makefile based on cbmem’s Makefile.

The make target `junit.xml` is removed as this is handled differently
since commit de9adebb (Add junit.xml code to top Makefile.inc instead of
utils).

Also the `junit.xml` is removed in the make target `clean`.

Additionally, the make target `distclean` is added, as the current
junit.xml code in the top `Makefile.inc` requires that.

Change-Id: I164b1f7733505bca6248d0711d7ad71d635fa926
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11876
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-10-24 00:27:18 +02:00
Tobias Diedrich ae3adffb7d amd/agesa/hudson: Add support for hiding the USB1.1-only OHCI
The hudson chipset has 4 USB controllers, the fourth is USB1.1-only and
(presumably) not used very often, add support for hiding it:
00:10.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 03) USB1 (3.0, XHCI)
00:10.1 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 03)
00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB2 (2.0, OHCI+EHCI)
00:12.2 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 11)
00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB3 (2.0, OHCI+EHCI)
00:13.2 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 11)
00:14.5 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB4 (1.1, OHCI only)

Change-Id: I804e7852fd0a6f870dd118b429473cb06ebac9a4
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/7355
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24 00:22:42 +02:00
Tobias Diedrich 0dab6d192b amd/sb800: Make UsbRxMode per-board customizable
On my Foxconn nT-A3500 on cold boot the board doesn't survive the soft
reboot in the UsbRxMode path and the vendor bios doesn't touch this
Cg2Pll voltage setting either.

The fixup code for UsbRxMode in src/vendorcode/amd/cimx/sb800/SBPort.c
doesn't seem to "CG PLL multiplier for USB Rx 1.1 mode", but rather
lowers the Cg2Pll voltage from the hw default of 1.222V to 1.1V
by setting Cg2Pll_IVR_TRIM in CGPllConfig5 to 1000.

See also USB_PLL_Voltage which is only used in the UsbRxMode code path.

However if this is already the efuse/eprom default for the SB800 then
UsbRxMode is a no-op, so whether or not it gets executed depends on the
very exact hw revision of the southbridge chip and could change between
two instances of the same board.

UsbRxMode used to be unitialized and was first set to default to 1
in http://review.coreboot.org/6474 (change I32237ff9,
southbridge/amd/cimx/sb800: Uninitialized variables in config func):

> > Why initialize those to 1? (just curious)
> See src/vendorcode/amd/cimx/sb800/SBTYPE.h
> git grep 'SbSpiSpeedSupport\|UsbRxMode'
> src/vendorcode/amd/cimx/sb800/SBTYPE.h

I could not find a corresponding errata in the SB800 errata list,
however errata 15 (USB Resets Asynchronously With Port CF9h Hard Reset)
might play into this being unsafe to do since the code uses CF9h to
reset.

So its possible that while previously undefined it still ended up
defaulting to 0 and the codepath exercised on my board is simply
buggy or there is a difference between a true "SB800" and the
"A50 Hudson M1" presumably used on my board.

Change-Id: I33f45925e222b86c0a97ece48f1ba97f6f878499
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10549
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24 00:21:01 +02:00
Tobias Diedrich a4d179af56 amd/acpi: Clean up SMBus references.
Replace the AMD SMBus section with the equivalent SB800 smbus.asl
include or remove already commented-out sections.

Verified by running the cpp preprocessor over the DSDTs and diffing the
results against this patch.

The only change is in src/mainboard/siemens/sitemp_g1p1/dsdt.asl, where
someone added RADD and SADD to the OpRegion, but those are unused, so
removing them is fine.

Change-Id: I074c8a1ed1c9a944d4988752bd0fc42c199c766c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10618
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24 00:17:50 +02:00
Marc Jones 9bb09526fa google/auron: Remove additional SPD file entries
Auron only has three GPIOs for RAMID, so there is no need for
sixteen SPD file entries. Only include 8 SPD entries.

Change-Id: Icf83719a2a5b9271b29f48cde5c66c4c8ccd07f4
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12073
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-23 22:39:07 +02:00
Martin Roth fc706437cb Intel: Move MCRS ResourceTemplate outside of _CRS method
On Broadwell, this reduces the number of 'remarks' in the IASL build
from 222 to 3.

Fixes these remarks:
Object is not referenced (Name is within method [_CRS])

The ACPI compiler is trying to be helpful in letting us know
that we're not using various fields in the MCRS ResourceTemplate
when we define it inside of the _CRS method.  Since we're not
intending to use those objects in the method, it shouldn't be an
issue, but the warning is annoying and can mask real issues.
Moving the creation of the MCRS object to outside of the CRS
method and referencing it from there solves this problem.

This change was made for fsp_baytrail in commit 2eaa0d49
fsp_baytrail: Fix ACPI 'Object is not referenced' warnings

Change-Id: I67a1faf963d1868f4133c7747a43a511cd28a44b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11268
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23 22:32:11 +02:00
Paul Menzel 035926c0a6 roda/rk9: Consolidate `acpi/platform.asl`
The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.

So include these files instead of duplicating the code.

Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).

Change-Id: Ifb434db1b8eb01acf48f26366c5237ae49a8730a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23 22:30:15 +02:00
Paul Menzel bb1b259184 lenovo/t400: Consolidate `acpi/platform.asl`
The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.

So include these files instead of duplicating the code.

Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).

Change-Id: Ide50b34184b80c86b996f86dd589c3cf3bf75587
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11883
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23 22:30:02 +02:00
Paul Menzel 5f302d7bfc lenovo/x200: Consolidate `acpi/platform.asl`
The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.

So include these files instead of duplicating the code.

Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).

Change-Id: I1e69cf0fd73e70ed6656b9ed6f55aba4c56a6edd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11882
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23 22:29:50 +02:00
Paul Menzel 8fc5c64403 southbridge/intel: Move `i82801gx/acpi/platform.asl` to `common/acpi`
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/southbridge/intel/i82801gx/acpi`. Devices with the
southbridge `intel/i82801ix`, like the laptop Lenovo X200, use the exact
same ASL code though. So share this in the directory
`src/southbridge/intel/common/acpi`.

Change-Id: I33b7993bcdbef7233ed85a683b2858ac72c1d642
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23 22:29:01 +02:00
Paul Menzel 469f593498 cpu/intel: Move Power notification ASL code into `common/acpi`
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/cpu/intel/model_6dx/acpi`, although the devices
can also use different Intel CPU models like, for example,
`intel/model_6ex` on the Lenovo T60.

Therefore move the file to the directory `src/cpu/intel/common/acpi` so
that other devices, like Intel GM45 based devices, can also include it.

Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23 22:28:12 +02:00
David Imhoff 6b0933adf7 intel/fsp_baytrail: Fix logging of ISPEnable option
Before this fix the value of PcdEnableSdio was printed as the MIPI/ISP
configuration option.

TEST=Built and booted on Minnowboard Max

Change-Id: Ia9b02d520f4e615f90b45935456b9d97c5d00f11
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10126
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-10-23 22:20:10 +02:00
Felix Held dfb53ef0a5 asrock/e350m1: disable unconnected GPP PCIe clocks
connections checked by desoldering the FCH and looking at the PCB

this lowers the power consumption by about 150-200mW measured on primary side

based on change 

Change-Id: I986c4cc73a247994f2a47fdfd03f585069ca9385
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/11866
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-23 20:45:34 +02:00
Stefan Reinauer 354c11d10e cbfstool: Make sure fileno is available on Cygwin
This patch fixes compilation of cbfstool on Cygwin.

As reported in http://review.coreboot.org/#/c/10027
cbfstool on Cygwin likes to be compiled with -D_GNU_SOURCE.
That patch was abandoned because it would unwantedly turn on
more GNU extensions. Instead of doing that, only enable the
define on Cygwin, switch to -std=gnu99 instead of -std=c99 to
make fileno and strdup actually available.
A MINGW32 check that was forgotten in Makefile was copied over
from Makefile.inc to keep the two files in sync.

This patch has no impact on non-Windows builds.

Change-Id: I068b181d67daf9c7280110e64aefb634aa20c69b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11667
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-23 20:44:35 +02:00
Felix Held 421b47e050 SB800-mainboards: use write8 to disable unused GPP CLK
don't use non-volatile pointers for MMIO access

Change-Id: I9f38012a806e43f2535265f1d25537c59b53904e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12081
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-23 20:44:06 +02:00
Timothy Pearson 907ea331f2 superio/nuvoton/nct5572d: Enable power state after power failure support
Change-Id: Ia0313b9ecd64c9e6f99a140772ebb35abe0175fd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11950
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-23 20:04:07 +02:00
Timothy Pearson a8d73a3957 northbridge/amd/amdmct: Fix Family 15h detection
Change-Id: I3623f8945bd62b7050ec609934f96543552c792b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12018
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-23 20:03:18 +02:00
Timothy Pearson 4cde9784e0 southbridge/amd/sr5650: Fix GPP3a link training in higher width modes
Change-Id: I7503ae42eb8bc91411413ef2cc7e7a723df7091a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11990
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-10-23 20:02:52 +02:00
Timothy Pearson a690a78cda device/hypertransport: Add additional debug output
Change-Id: I94b870f47581a4a2591d02eeb37627666e0f4297
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11945
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
2015-10-23 20:00:07 +02:00
Timothy Pearson 38629f51ad cpu/amd/model_10xxx: Clean up debugging statements
Change-Id: I6dff74b3857e1fb384aefc87b44e7679bd4aab07
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11948
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-10-23 19:59:40 +02:00
Timothy Pearson 76d4636e61 northbridge/amd/amdmct/mct_ddr3: Fix curly brace style violations
Change-Id: Ic27d404a7ed76b58043037e8b66097db6d664501
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11942
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-10-23 19:58:48 +02:00
Timothy Pearson 964aa839ca include/smbios: Update SMBIOS memory structures to version 2.8
Change-Id: Icda915933c4ebf3a735d9e1d4e4dbb1138a06b39
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11955
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
2015-10-23 19:58:17 +02:00
Patrick Georgi efb9d95523 intel/cougar_canyon2: fix build
The reintroduction of cougar_canyon2 crossed beams with the
moving the GMA display brightness data in ACPI into individual
mainboards.

Make things build again by having the board use the same default values
that it used to use automatically. They may be wrong, but no worse than
what was there before.

Change-Id: Id788034c38b42e1c35d9cd17e9bbb2ce49e3e91c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12132
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-23 11:38:53 +02:00
Stefan Reinauer 1ecf252c38 MAINTAINERS: Add script to test database and find maintainers
This utility should make it easier to complete and maintain
the database of coreboot subsystem maintainers (MAINTAINERS
file)

This will need a bit of tender love and care to print information
in an easily machine readable output for the build system, but its
a first start to query the maintainers database.

Build with:
   $ go build util/scripts/maintainers.go

Find a maintainer for a set of files with:
   $ ./maintainers Makefile Makefile.inc
   Makefile is in subsystem BUILD SYSTEM
   Maintainers:  [Patrick Georgi <patrick@georgi-clan.de>]
   Makefile.inc is in subsystem BUILD SYSTEM
   Maintainers:  [Patrick Georgi <patrick@georgi-clan.de>]

Check the maintainer database with:
   $ ./maintainers
   .gitignore has no subsystem defined in MAINTAINERS
   .gitmodules has no subsystem defined in MAINTAINERS
   .gitreview has no subsystem defined in MAINTAINERS
   3rdparty/arm-trusted-firmware has no subsystem defined in MAINTAINERS
   3rdparty/blobs has no subsystem defined in MAINTAINERS
   3rdparty/vboot has no subsystem defined in MAINTAINERS
   COPYING has no subsystem defined in MAINTAINERS
   Documentation/AMD-S3.txt has no subsystem defined in MAINTAINERS
   Documentation/CorebootBuildingGuide.tex has no subsystem defined in MAINTAINERS
   Documentation/Doxyfile.coreboot has no subsystem defined in MAINTAINERS
   [..]

Change-Id: I49c43911971152b0e4d626ccdeb33c088e362695
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12119
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-23 01:47:39 +02:00
Timothy Pearson 33fb4cf0ff northbridge/amd/amdfam10: Fix typo in comment
Change-Id: I0a9b3a66231052622c862bae32b900f52f6efba9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11944
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-10-23 01:19:20 +02:00
Stefan Reinauer 3a043c47a9 cbfstool: Fix tolower() calls on Cygwin
Cygwin complains:

cbfstool.c: 1075:5 error: array subscript has type 'char' [-Werror=char-subscripts]

so add an explicit cast.

Change-Id: Ie89153518d6af2bacce3f48fc7952fee17a688dd
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11666
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-23 01:07:01 +02:00
Nico Huber 8193b068d4 allocator: Page align memory mapped PCI resources
To help hypervisors to assign PCI devices individually to virtualization
guests, page align dynamically allocated MMIO resources.

Tested with kontron/ktqm77 which has dynamically configured onboard
devices on the root bus and secondary buses. Booted Linux and checked
the configuration with `lspci -v`. Got the configuration through Muen's
tools which are very picky about overlapping and alignment. Booted a
Muen based system that uses many onboard devices. GMA, xHCI and one NIC
(on a secondary bus) were verified to function properly.

Change-Id: I2b7115070e1ccad64565feff025289732c3b5e66
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12111
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-22 23:04:55 +02:00
Nico Huber 37743a913f cbfstool/Makefile: Also rm fmd_(parser|scanner).[ch] in clean
Change-Id: I783aa4b2319aaedd57ce9a67ca935392a611298f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12127
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22 23:02:40 +02:00
Nico Huber 5e731a7cfc cbfstool/Makefile: Drop unused, irritating definition of `obj`
Change-Id: Id8dda8a973dcf991ac494c2d50258d1b51e43c6a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12126
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22 23:02:01 +02:00
Nico Huber 954a55b950 gma ACPI: Make brightness levels a per board setting
Those are actually board specific. Keep the old value as defaults,
though. The defaults are included by all affected boards.

Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-22 23:01:36 +02:00