This patch makes all Octopus variants resume from S0ix/S3 on AC plug
and unplug.
Change-Id: Iab054d77368bf2047b6d523188b8c401a7643aaa
Signed-off-by: Derek Basehore <dbasehore@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then
`get_wifi_sar_limits()` assumes that the default filename is used for
CBFS SAR file. This prevents a board from supporting different models
using the same firmware -- some which require SAR support and some
which don't.
This change updates the logic in `get_wifi_sar_limits()` to return
early if filename is not provided by the mainboard. In order to
maintain the same logic as before, current mainboards are updated to
return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default
case.
Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fleex will use SSFC to support RTL5682.
BUG=b:178653122
TEST=abuild
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icb06eabe297c5562bd2171b52cc9671c342e6dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
The current driver is using chip registers map to configure the SAR
sensor, which is opaque, especially when the datasheet is not published
widely.
Use more descriptive names, as defined in Linux kernel documentation at
https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml
BUG=b:173341604
BRANCH=volteer
TEST=Dump all tables, check semtech property:
for i in $(find /sys/firmware/acpi/tables/ -type f) ; do
f=$(basename $i); cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat
done
In SSDT.dsl, we have:
Package (0x06)
{
Package (0x02)
{
"semtech,cs0-ground",
Zero
},
Package (0x02)
{
"semtech,startup-sensor",
Zero
},
Package (0x02)
{
"semtech,proxraw-strength",
Zero
},
Package (0x02)
{
"semtech,avg-pos-strength",
0x0200
},
Package (0x02)
{
"semtech,combined-sensors",
Package (0x03)
{
Zero,
One,
0x02
}
},
Package (0x02)
{
"semtech,resolution",
"finest"
}
}
Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fleex has other project share the same FW. Only fleex has LTE sku.
So we need to make sure it is fleex then check if LTE sku.
BUG=b:181946744
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4 and 5.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9f3d5fed4315fc716acad1a07735221d154c377e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested
with CHROMEOS=n.
Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: Ieeb738afd54e77ee853ee109009f611411aa0d4a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49426
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do LPC/eSPI pad configuration at board-level to match other platforms by
adding an appropriate early gpio table in the bootblock.
The soc code gets dropped in CB:49410.
Change-Id: Ie33bae481f430a1c4410a0a4e2b2a34a3e78adaa
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49411
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:171757619
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Change-Id: I37390535e263b4b9547ad7307278e3360ba836bd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
BUG=b:174118027
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Signed-off-by: Marco Chen <marcochen@google.com>
Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
This change adds support zinitix touchpad for casta/bluebird.
BRANCH=firmware-octopus-11297.B
BUG=b:175618033
TEST=built and verified touchpad worked on casta
Change-Id: I1a8f562de19d1a8160d52c65400553f0c68393e0
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48634
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently the decision of whether or not to use mrc_cache in recovery
mode is made within the individual platforms' drivers (ie: fsp2.0,
fsp1.1, etc.). As this is not platform specific, but uses common
vboot infrastructure, the code can be unified and moved into
mrc_cache. The conditions are as follows:
1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain
switch is true)
2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this
means that memory training will occur after verified boot,
meaning that mrc_cache will be filled with data from executing
RW code. So in this case, we never want to use the training
data in the mrc_cache for recovery mode.
3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this
means that memory training happens before verfied boot, meaning
that the mrc_cache data is generated by RO code, so it is safe
to use for a recovery boot.
4. Any platform that does not use vboot should be unaffected.
Additionally, we have removed the
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the
mrc_cache driver takes care of invalidating the mrc_cache data for
normal mode. If the platform:
1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data
2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set
BUG=b:150502246
BRANCH=None
TEST=1. run dut-control power_state:rec_force_mrc twice on lazor
ensure that memory retraining happens both times
run dut-control power_state:rec twice on lazor
ensure that memory retraining happens only first time
2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig
boot twice to ensure caching of memory training occurred
on each boot.
Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ic334816712370da63471135da8dd598ab02d54ef
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
variant_smi_sleep is called in smm stage so we need to add
variant.c into smm stage. Otherwise it will call the dummy one.
BUG=b:168075958
BRANCH=octopus
TEST=build image passed.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I41df1a30b119ab3e04f9ae01955b6044f137527f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46847
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.
If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:169645448
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.
If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:171478764
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46701
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
invoke LTE power off function to meet LTE power sequence while DUT is
in reboot state.
BUG=b:167565015
BRANCH=octopus
TEST=build and verify on the DUT with LTE
Change-Id: I825cefb524ddaf9a9cb6add31c2ee0eea484f978
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46022
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New SKU ID 5 is used for LTE touch SKU. This patch does LTE power off
for LTE sku and only use Wifi SAR table for non-LTE sku.
BUG=b:168001586
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4 and 5.
Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46643
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
ALS is not stuffed in octopus boards. Hence disable ALS ACPI devices.
BUG=b:169245831
BRANCH=octopus
TEST=Ensure that ALS devices are disabled in ACPI tables.
Change-Id: I5ad28f01b0515a41b314116eb2d05c520df0f86e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch makes Fleex EC wake up AP from s0ix when the state of
charge drops to 5%.
Demonstrated as follows:
1. Boot Fleex.
2. Run powerd_dbus_suspend.
3. On EC, run battfake 5.
4. System resumes.
BUG=b:163721887
BRANCH=Octopus
TEST=Verified on Fleex:
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I4a998ad0aef5a7cfc6fd18995bde5571e6127e77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Only do LTE power off for LTE sku in order to save extra 130ms delay
for non-LTE sku.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If983185ff2f09fb1b2553c6ff1a1473d3254de4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Use Wifi SAR table for non-LTE sku only.
BUG=b:169115341
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I086fa14a9f23e4a0fc0ef8085040219c932dbf17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45640
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
0x12 will be more stable according to validation result on SD card and
USB devices.
BUG=b:163382089
BRANCH=none
TEST=check if SD cards and USB devices work properly
Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: Ic98f27b6164daa3667009300439c61fed43a4a0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45573
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All octopus board share the same power off sequence.
Move to smihandler.c instead variant.c.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2be5a656fb42fff99c56d21aaa73ed9140caad37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45436
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIOs related to power sequence are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:168075958
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9b56ef8ff346c1d4edd5aad04d4a7396c4702ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45193
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:167297664
BRANCH=octopus
TEST=build fleex, and check touchscreen can work
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I910681c258ff5487830e795a8bd08c66be69b1d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44980
Reviewed-by: Justin TerAvest <teravest@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both Gemini Lake boards in the tree use the same value.
Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set default value of ModPhyIfValue parameter in FSPS_UPD.
Without this setting, it will be set to '0' and system may not detect
USB 3.0 device.
BUG=b:163382089
BRANCH=firmware-octopus-11297.B
TEST=Built
Change-Id: Ide3d1637f99dba28251102f771b6ce370cc5d8e4
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
