Commit Graph

25558 Commits

Author SHA1 Message Date
Xiang Wang d945621b5d riscv: fix issues (timestrap & PRIu64)
When I tried to compile the RISC-V code (202e7d4f3c), I found some errors:
    `PRIu64` is undefined
    src/arch/riscv/timestamp.c does not exist

Currently RISC-V does not have the implementation and use of timestamp,
so I temporarily delete the code related to timestamp in the Makefile.
And define PRIu64.

Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-31 10:07:57 +00:00
Martin Roth 5b7c6f52e6 abuild: Fix shellcheck errors
Fix 6 new errors found by shellcheck 0.4.6
SC2155: Declare and assign separately to avoid masking return values.
4 x SC2086: Double quote to prevent globbing and word splitting.
SC2196: egrep is non-standard and deprecated. Use grep -E instead.

One of the SC2086 errors is masked because it needs word splitting.

Change-Id: I7f869e6d208f7247f739619c538be6075b802719
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-07-31 10:07:32 +00:00
Martin Roth 7a98591a1d abuild: Update failed boards handling
- Use TARGET variable for location of passing/failing boards files.
This should better handle the directory, wherever it is.
- Don't save make.log location if make.log is being deleted.

Change-Id: I28e55feef85c9b642ac5ff70ecef113cf7978707
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-31 10:07:26 +00:00
Matt DeVillier 4e71436d5f samsung/stumpy: Add support for libgfxinit
Add support for libgfxinit

Test: boot stumpy, verify all outputs operational prior for pre-OS display

Change-Id: Ia720814c2225502316de5c5e9639c67df65a2ed0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-31 01:57:33 +00:00
Richard Spiegel 4665c593ef mainboard/google/kahlee: Update VBIOS image
The careena board requires a different setting within VBIOS in order to
pass the eDP eye diagram test. Update all kahlee boards to use the new vBIOS.

CQ-DEPEND=CL:1153080
BUG=b:111673328
TEST=Verify, via SOME unspecified method, that the new vBIOS is built into
the Grunt/Careena ROM files.

Change-Id: I268cd3dbce6ba1f7bd781d768f470463846a4e10
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27643
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31 00:50:28 +00:00
Richard Spiegel d30201feaf src/vendorcode/amd/pi/00670F00: Remove IMC support
Per AMD, the Integrated Micro Controller is not a supported feature of the
Stoney Ridge APU.  Systems are expected to implement an external EC for
desired features. Remove all stoney IMC files and functions from vendor code.

BUG=b:111780177
TEST=Build grunt and gardenia

Change-Id: I06e993fa498cc0978c1d037bc6001682407f7fac
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27652
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31 00:46:25 +00:00
Richard Spiegel 7108107fa2 src/soc/amd/stoneyridge: Remove IMC support
Per AMD, the Integrated Micro Controller is not a supported feature of
the Stoney Ridge APU.  Systems are expected to implement an external EC
for desired features. Remove all stoney IMC files and functions from
src/soc/amd/stoneyridge.

There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG
describe these bits, so a new patch will be released later to fix the
names and comment.

BUG=b:111780177
TEST=Build grunt and gardenia

Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27651
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31 00:46:07 +00:00
Richard Spiegel 90b2cca81f mb/amd/gardenia: Remove IMC support
Per AMD, the Integrated Micro Controller is not a supported feature of the
Stoney Ridge APU.  Systems are expected to implement an external EC for
desired features. Remove IMC files and functions from gardenia.

BUG=b:111780177
TEST=Build gardenia

Change-Id: I570b7f8e364b0c2937592590cc033d5a6c9fade0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27650
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31 00:45:46 +00:00
Felix Held 432575c5d3 x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]
When using timeless builds and coreboot crossgcc 6.3.0, the checksum of the
resulting binary doesn't change with applying this commit.

Change-Id: I057abe314622e92000c7e4ff2faa4595edb5244b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 20:44:37 +00:00
Arthur Heymans aade90e68d nb/intel/gm45: Use common code for SMM in TSEG
This makes i82801ix use the common smm southbridge code to set up smm
relocation and smi handler setup. This is needed in this change for the
the smm relocation code relies on some southbridge functions provided
in the common code. Some of the old code is kept for the Q35 qemu
target.

This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.

Currently SMRR msr's are not set on model_1067x and model_6fx since this needs
the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled
properly in the subsequent parallel mp init patchset.

Tested on Thinkpad X200: boots and going to and resuming from S3 still
works fine.

Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23419
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 19:11:00 +00:00
Felix Held 6cd2c2f6ff northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros
Change-Id: Ie95321f3eb6fb17b17eb25e8a54670654c373706
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 19:10:02 +00:00
Arthur Heymans 06f818c932 cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x
According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual"
the SMRR MSR are at a different offset for model_6fx and model_1067x.

This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL.

Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-30 19:03:27 +00:00
Xiang Wang e8d0c0092a riscv: delete src/arch/riscv/prologue.inc
This code was copied from x86. It is not needed for RISC-V.

Change-Id: If6c3bfdc4090e45d171e68a28d27c38dabe91687
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27544
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 19:02:13 +00:00
Patrick Rudolph dbf5a5d0f8 ec/lenovo/h8/acpi: Fix ACPI error in _INI
Store the power on defaults in the _REG method after the ERAM region
is ready for use. It might not be ready when accessed from _INI.

Tested on Lenovo T430.

Change-Id: I70f22f8ac61dd850180fa159313bb0f8e4ab31d9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 18:59:51 +00:00
Patrick Rudolph e67f626664 mb/google/stout: Use new PMBASE API
Change-Id: Ibb13627bcd2ad023f7686b5ae0bd7331e09cf5b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-30 18:59:20 +00:00
Patrick Rudolph a28eb8b2f4 mb/samsung/lumpy: Use new PMBASE API
Change-Id: Ife344d1699a2eff7d93738221a0e87d0481f05d7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 18:58:57 +00:00
Patrick Rudolph baea5994d8 mb/google/link: Use new PMBASE API
Change-Id: If4d6c80e95469341f0c978f302f04508f50280bd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 18:58:49 +00:00
Patrick Rudolph 2dc63895eb sb/intel/bd82x6x/finalize: Use new PMBASE API
Change-Id: Id42bbea1f2deb0be80af2c8008045d37a926126a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 18:58:22 +00:00
Patrick Rudolph ecb2399ab8 mb/google/parrot/smihandler: Use new PMBASE API
Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 18:58:13 +00:00
Richard Spiegel 5d3707bbc3 mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFF
The careena board needs different video settings to pass eye diagram test,
which does not affect negatively the grunt board. In preparation for new
VBIOS, AGESA environment needs eDP high vdiff enabled.

BUG=b:111673328
TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and
boot grunt. Add new code to grunt, build and boot, verify eDP changed.

Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30 18:57:18 +00:00
Richard Spiegel 2e90ee38e7 soc/amd/stoneyridge/northbridge.c: Create a way to change eDP training value
The careena board needs different video settings to pass eye diagram test,
which does not affect negatively the grunt board. In preparation for new
VBIOS, create code that allows changing eDP training parameter.

BUG=b:111673328
TEST=Tested in child patch.

Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30 18:57:06 +00:00
Tim Chen 9b7e096073 mb/google/poppy/variants/atlas: Add new Nanya memory option
- add Nanya NT6CL256T32CM-H1 to memory strapping table

BUG=b:111906760
BRANCH=none
TEST=none

Change-Id: I1432b9ab84f01a7fee1bc562aa40c714ddbf639e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
2018-07-30 18:56:17 +00:00
Matt Delco 8928bc0d63 mainboard/google/nocturne: simplify camera power references
This change primarily moves the PowerResource up to a more common scope so
that the _PRx references are simpler. The ^ scope modifier isn't well
supported everywhere amongst OSes and drivers.  Windows 10 will BSOD
early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could
not find the object referenced by a _PRx) with the way things are currently
laid out).

I've also not seen a firmware outside of coreboot that tries to reference
count _ON and _OFF. Isn't it up to the OS to deference count, and whatever
it tells ACPI is what should happen (i.e., on means on and off means off)?

Some of the _UIDs are also duplicated.  This change makes them unique.

A few cosmetic changes are made so that diffing cam0.asl against
cam1.asl has fewer extraneous differences.

Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-30 18:55:50 +00:00
Matt DeVillier b89bd788be google/caroline: Change debounce time for jack insertion and ejection
Adapted from chromium commit 7633daa
[caroline: Change debounce time for jack insertion and ejection]

We are using max debounce time. During this time line, MICBIAS will be
zero because of jack chasis. At the moment we got 0 button (PLAY/PAUSE)
We need to reduce this time to below 100ms for caroline device.

BUG=b:79559096
TEST=see there is no more irq before jack insertion/ejection irq
complete

Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a
Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1143109
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wonjoon Lee <woojoo.lee@samsung.com>

Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27659
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 18:50:54 +00:00
Hung-Te Lin 1be16f08f2 google/kukui: Enable eMMC in bootblock.
On kukui board, the eMMC is routed to EC for boot ROM emulation when
loading bootblock, and should be set back to real eMMC as early as
possible after bootblock is loaded.

BUG=b:80501386
TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled.
BRANCH=None

Change-Id: Ifefb2e26ed048c38595907cc0875757410129828
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/27601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 18:50:09 +00:00
Rizwan Qureshi 0d3915714c cpu/intel/microcode: Add helper functions to get microcode info
Add 4 helper functions to get microcode info.
* get_current_microcode_rev
	return the the version of the currently running microcode.
* get_microcode_rev
	extract microcode revision from the given patch.
* get_microcode_size
	extract microcode size from the given patch.
* get_microcode_checksum
	extract checksum from the given patch.

The simpler thing would be to just move the struct microcode
to microcode.h so that the structure members can be dereferenced.
To encapsulate the structure details added the helper functions.

This information will be used in future to compare microcodes for update.

Change-Id: I67a08ba40b393874d8cc17363fefe21e2ea904f3
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/27365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 18:49:47 +00:00
Aamir Bohra 2276d4f4a8 soc/intel/common: Add support to configure top swap feature
RTC BUC control register provides a software interface to
configure the top swap feature. This patch adds implementation
to enable/disable top swap feature and gets it accessible in
romstage as well.
The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP
is selected.

To use the topswap feature a second bootblock has to be added
to the cbfs. Below configs aid in doing that,
INTEL_HAS_TOP_SWAP
INTEL_ADD_TOP_SWAP_BOOTBLOCK
INTEL_TOP_SWAP_BOOTBLOCK_SIZE

Enabling and Disabling topswap, using the added API enables user
to boot alternatively from either bootblock.

Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/25805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30 18:49:15 +00:00
Nick Vaccaro 4f9ff53e42 mb/google/poppy/variants/nocturne: enable FPMCU power
Enable power to FPMCU by default on power-on and deassert
the PCH_FPMCU_RST_ODL reset line.

BUG=b:111880258
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel
prompt, wait a few seconds, press power button to wake, then execute
"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes
up empty.

Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 18:48:43 +00:00
Nick Vaccaro d091cd1fc1 mb/google/poppy/variants/nocturne: enable ec host event wake
Enable nocturne to wake from lid attach/detach events.

BUG=b:111803637
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has
commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne
wakes from suspend on a lid attach/detach event.

Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27649
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 18:48:33 +00:00
Alan Chiang e81b2e4712 mb/google/nautilus: Remove obsolete fields
Some fields were only required during early stages of IPU3.

Remove some fields that aren't used for the current version of IPU3.

BUG:None
TEST=Launch camera app and check if it works properly.

Change-Id: I72bcba13cc353a1b16fedeb7543fbbac432fbf5d
Signed-off-by: Alan Chiang <alanx.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/27617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-30 18:48:02 +00:00
Patrick Rudolph 448f5abaf0 mb/cavium/cn8100_sff_evb: Compile devicetree for Linux
Compile the linux devicetree using dtc and add it to CBFS.

Change-Id: I8a98ed7b128f65a6e0109963dbabca91563a315c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30 18:47:46 +00:00
Patrick Rudolph 5cdaa3305e soc/cavium/cn81xx: Use ATF from blobs repo
Use precompiled BL31 from blobs repo.

There's no check for USE_BLOBS here as the included file is "free":
The BL31 is Open-Source and licensed under BSD.

Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30 18:47:26 +00:00
Patrick Rudolph e15556ed3a soc/cavium/bootblock: Get rid of register X1
The register X1 isn't used. Document it and remove it.

Change-Id: I9324ea9de24ba4baaef9dde890c443dd0f921ad9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30 18:46:41 +00:00
Furquan Shaikh 520149dc63 mb/google/octopusi/variants/bip: Fix unused pins and those with external terminations
For unused pins, configure them as GPIO input and use the default
termination. For the pins where board has an external termination,
remove SOC's internal termintation.

BUG=b:110654510
TEST=On Bip, flashed image and verified that it boots to OS. Also
executed a few suspend resume cycles.

Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/27634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30 18:46:01 +00:00
Daniel Kurtz cd62cac9e1 drivers/i2c/da7219: Allow disabling micbias-pulse feature
These two da7219_aad properties are optional:
- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV).
        [<2800>, <2900>]
- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)

When the Mic Bias Higher Voltage feature is not required, firmware should
just not provide the dlg,micbias-pulse-lvl and dlg,micbias-pulse-time
properties.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>

BUG=b:111700809
TEST=On grunt:
 No "Invalid micbias pulse level" in dmesg

Change-Id: Ie99a8962e78c68b3f6927d0de34168f265d4efa9
Reviewed-on: https://review.coreboot.org/27613
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Akshu Agrawal <akshu.agrawal@amd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 18:45:44 +00:00
Philipp Deppenwiese 791ba97d1d security/tpm: Use unique CBMEM names for TCPA logs
Fix regression introduced in commit f18dc5c7
"Add TCPA logging functionality":

Introduced TCPA log got overwritten in acpi.c of x86/arch, due to
CBMEM name collision. Use a different cbmem name to have two independent
TCPA logs.

Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30 15:47:23 +00:00
Philipp Deppenwiese f849972f65 security/vboot: Enable TCPA log extension
* Implement TCPA log for tspi extend function.
* Hook tcpa_log_init into vboot tpm_setup function.
* Add TCPA log output for vboot GBB flags and HWID

Change-Id: I22b1aa8da1a95380c39715727615ce5ce4c9443f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30 15:46:11 +00:00
Philipp Deppenwiese 405a0f5230 soc/intel/fsp_baytrail: Add VBOOT support
* Add vbnv_cmos_failed function to SoC.
* Add VBOOT starts in romstage select.

Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-30 15:45:44 +00:00
Felix Held 86b299ab35 northbridge/nehalem: add MCHBAR AND/OR/AND_OR macros
The newly added macros are used for cleaning up the RAM initializatiion code.

Change-Id: I3d3782ee1fa524cf69b63ccc7eb73e9a2ace84ec
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30 12:33:36 +00:00
Felix Held 00d2b913c3 northbridge/nehalem: clean up header file
* remove duplicate macro definitions
* add brackets to macros

Change-Id: I1f758203afdcb1b18f3c0d786698f9fbf2246e0e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-30 12:31:18 +00:00
zaolin 0ea7471eec mainboard/opencellular/rotundu: Add FMAP support
* Add 8M and 16M fmap configurations.
* Fix kconfig selects.
* Add vboot options and fixes

Change-Id: I49d97a9d324207e45520d43b814b03a20005122a
Signed-off-by: zaolin <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/25084
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 10:26:03 +00:00
Seunghwan Kim 2ee7f483b1 mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default
Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means
LTE tx power is backoff mode as default.

We would set GPP_D21 to high to change LTE tx power to normal mode as
default.

BUG=None
BRANCH=poppy
TEST=Verified default LTE tx power mode is normal mode as default

Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30 06:12:06 +00:00
John Su dc515b5aed mb/google/poppy/variants/nami: Fix fan is always ON
Add the new setting for fan performance state.

BUG=b:111860513, b:11865138
TEST=Fan do not run below trip point

Change-Id: I894460b8b418217e2477608094c37018437cbb78
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-07-30 02:36:30 +00:00
Martin Roth 7a3458432c mainboard/google/kahlee: Pad SPD serial Number with spaces
All of the other SPDs are padded with spaces to make them use the full
size of the serial number field.  The hynix-H5AN8G6NCJR-VKC SPD was not,
and that seems to be causing problems with some tools.

BUG=b:111903749
TEST=Mosys correctly identifies memory on board using that SPD.

Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2018-07-30 02:20:04 +00:00
Felix Held 2bb3cdfb9f sandybridge/raminit_common: use MCHBAR32 macro everywhere
Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29 18:06:44 +00:00
Felix Held 55823c3d36 sandybridge/raminit: use MCHBAR32 macro everywhere
Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-29 17:28:05 +00:00
Felix Held b9267f0cec sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macros
Change-Id: If8b8fd123e0dd15a0fc9dfe178076f8541e29d56
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29 17:27:43 +00:00
Felix Held a662777b6f pnp_device: don't treat missing PNP_MSC devicetree entry as error
Change-Id: I8da01cd462225b633bf2043ab33b35aeddc8d55a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29 15:06:41 +00:00
Felix Held f2ec648fcb device/pnp_device: rewrite pnp_get_ioresource
The rewrite simplifies the code and fixes the limit on the case of IO resources
with the length of 1 byte.

This patch is inspired by the comment of Nico Huber on
Ia99b785dcd9cf56fb236ad7ade54656851f88a5e

If the ones in the mask aren't a continuous block, now a warning message gets
printed.

Change-Id: I0089278f5adf65e8f084580bc5bc1eb2f77b87f7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29 15:06:10 +00:00
Philipp Deppenwiese 66ce18c508 soc/intel: Remove legacy static TPM asl code
Since the TPM software stack refactoring static
TPM ACPI code isn't needed anymore.

Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27715
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-29 12:29:11 +00:00