- The SMU firmware used to be named *.sbin, now is named *.csbin.
Update the makefile so that the files can be named as they are
delivered and don't have to be renamed.
- Add a Kconfig option to allow the secure os binaries to be excluded.
BUG=b:64932297
TEST=Build with old and new firmware, verify file sizes.
Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Adapted from Chromium commit 9756af8.
Add SOC helper to identify BSW SoC stepping. Will be used to
override USB2 phy setting based on stepping in subsequent commit.
Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With FSP 1.1, all FSP blobs are forward-compatible with newer FSP 1.1
header files, so adjust the header revision check to ensure that the
FSP blob isn't newer than the header, rather than an exact version match.
This resolves a version mismatch issue with Braswell ChromeOS devices,
which ship with FSP blobs newer than the publicly-released blob (1.1.2.0),
but older than the current Braswell FSP 1.1 header (1.1.7.0).
TEST: build/boot google/cyan and edgar boards, observe no adverse
effects from using current FSP header (1.1.7.0) with the factory-
shipped FSP blobs (1.1.4.0/1.1.4.2).
Change-Id: I8934675a2deed260886a83fa34512904c40af8e1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the common acpi code.ACPI code is very similar
accross different intel chipsets.This patch is an effort to
move those code in common place so that it can be shared accross
different intel platforms instead of duplicating for each platform.
We are removing the common acpi files in src/soc/intel/common.
This removes the acpi.c file which was previously in
src/soc/common/acpi. The config for common acpi is
SOC_INTEL_COMMON_BLOCK_ACPI which can be defined in SOC's
Kconfig file in order to use the common ACPI code. This patch also
includes the changes in APL platform to use the common ACPI block.
TEST= Tested the patch as below:
1.Builds and system boots up with the patch.
2.Check all the ACPI tables are present in
/sys/firmware/acpi/tables
3.Check SCI's are properly working as we are
modifying the function to override madt.
4.Extract acpi tables like DSDT,APIC, FACP, FACS
and decompile the by iasl and compare with good
known tables.
5.Execute the extracted tables in aciexec to check
acpi methods are working properly.
Change-Id: Ib6eb6fd5366e6e28fd81bc22d050b0efa05a2e5d
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
APL internal UARTs are not used on this mainboard.
Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is one on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I45202937eba11da3bea14fef6ebed70599804335
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Boards with CBMEM_TOP_BACKUP=y can also use POSTCAR_STAGE
for MTRR setup after adding this file in the build.
Change-Id: I5f9a673ff59ccfbba16308d27f653f5cf3b49017
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Postcar failed when loading from stage_cache, if
romstage did not pass same pcf->stack on normal
and resume paths.
Change-Id: I853afb1fbdb942fd671d89950911c850c96e3af3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The change allows to update rmodule parameters after
it has been loaded from stage cache.
Change-Id: Ib825ffe245d447ad3a8246f7dbd52c6e34103a0c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements soc function to get previous sleep state
using chipset_power_state global structure.
acpi_get_sleep_type is needed in PRE_RAM stage when soc selects
CONFIG_EARLY_EBDA_INIT kconfig option.
Change-Id: I79acbfc09c8d255fbf9d73e49e8c7764f3f3fac6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Fix the warnings of klocwork scan.
e.g. "Pointer 'dev' checked for NULL at line 158 will be dereferenced at line 159"
Change-Id: I6cc9c68652b074c666c86456183460ca38a886ed
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We've decided to move control for the 3.0V rail (technically 3.3V on
Scarlet, but who cares about millivolts) back to a GPIO on the AP for
Scarlet rev2. This patch adds the necessary code to enable it and make
ARM TF aware of its existence. Since the pin had previously not been
connected to anything, we shouldn't really need to guard this by board
ID... older Scarlets will just be twiddling an empty pin.
Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Vendorcode expects some DRAM controller registers to
be writable, but they are actually locked after soft
resets if C6 states are enabled.
Without the workaround, raminit fails on soft resets.
Change-Id: I6b9e275e11b2907d026c13341334983a4d9c8889
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's too critical to ignore when sending the message on
SMBus fails, so allow for a fair amount of retries.
Failure here causes watchdog to do hard reset later.
Move it out of mainboard.c as we need to call this
early in romstage while we are debugging.
Change-Id: I1006b079269d6dd44de630db7a5694124af2f974
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression caused by commit
9e94dbf ACPI: Get S3 resume state from romstage_handoff
Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.
Change-Id: I7c9065ccc48dfbdefade698ed275756f17dff7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression caused by commit
9e94dbf ACPI: Get S3 resume state from romstage_handoff
Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.
Change-Id: I464feb1655a51a937b6cf53508dd5c7aa0d8f791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Fix regression caused by commit:
714709f AMD fam10 ACPI: Use common fixed sleepstates.asl
Adding common sleepstates.asl got lost in rebase process.
Change-Id: I4f22ee950ae5637113db8e79ca238cb1b81002aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch adds imon and vmon slot numbers for Maxim 98927 driver.
These values are used to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I4382da4f984507d147751c168e8177b58c88a70f
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change list adds imon and vmon slot numbers as params for
Maxim 98927 driver. These values are looked up in the kernel driver
to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I21d72ba91af83782587f11018b2d1d1c8d4f676c
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There was already a uart.c added to bootblock. Remove the
duplicate addition.
Change-Id: I2d420ff7437d25a596ee9a120964f8d4bc413bc4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Vboot and ChromeOS support in SOC Kconfig, include a separated
verstage in Makefiles.inc as well.
Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously the random seed was fixed, which led to the same sequence of
blocks for each run.
Now that libpayload has time(), no change is needed in the function
rand_init() of tint.
Change-Id: I2e482bbb9d33cdbbf3c15916458329f99fbc4450
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/20980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We don't actually care for them on our testers, just that the files
can be built.
Change-Id: Ib656a085d70e2aeb1601f1943ad8581af3133839
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21420
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AGESA internal headerfiles are allover the place. Luckily, they
have unique names within the Proc/ tree so include every existing
directory in undefined order.
Change-Id: I86f080e514391a3f0f05d379d24d490ce075060e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Besides some internal changes that won't have much effect on coreboot,
the newer version also supports building host tools on systems that
self-designate as i686.
Change-Id: I823bad862805cdec1dfecc8ba046f73ac206d3e8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The regular build doesn't build it, so it fails every now and then due
to changes in its dependencies.
Make sure we notice these early.
Change-Id: I0603b22887487d8871611d91e6f8ab0ec210bff1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/21390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This reverts commit 6c0f3c7ee1.
Reason for revert:
Broke master builds, this was submitted out-of-order, some
of the dependencies have not passed review with +2 yet.
Change-Id: Ib7bcb1b98623d16e074caeca839a936d71ded709
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This recovers FCH configuration on S3 resume path.
Appearst to work, but other defects of HAVE_ACPI_RESUME
must be fixed also before S3 support is re-enabled.
Change-Id: I8d07d2e9dc161b67d854fcc8ec1da1f36900f989
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There is no serial port on this platform.
In addition, put the LPC serial IRQ into quiet mode.
Change-Id: I4b2c93c51e8ddb8b510f0d7f7e3072befeba5d95
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/21226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The deprecation of late (post-romstage) CBMEM initialization was
announced in this blog post:
https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/
There are two warnings:
* In LATE_CBMEM_INIT's help text, I've added a multi-line warning, that
aims to explain the problem.
* In src/mainboard/Kconfig (just below the mainboard selection), there's
a warning which points the user at LATE_CBMEM_INIT, if such a board is
selected.
Also update the function that needs to be implemented, as pointed out by
Keith Hui and Kyösti Mälkki.
Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Inspired by gm45 code, which sets this value the same way.
Some values for tRD on 800 and 1067MHz FSB were set wrong because the
CAS/Freq selection was wrong. CAS was often selected to low and when
fixing CAS this results in tRD being too high, due to an incorrect
lookup table which caused instability.
PASSED memtest86+ during 10h+ on 1067MHZ fsb with 667MHz ddr2, CAS 5
on GA-945GCM-S2L.
Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Also make most significant bit function accessible outside the scope
of this file.
Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Include Makefile from site-local even in absence of DOTCONFIG.
This will allow execution of Makefile option from site-local in absence of
DOTCONFIG as well.
Change-Id: I62d1562687ffe18546add80fdde1196700a65236
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/21303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Kyösti Mälkki