Commit Graph

30722 Commits

Author SHA1 Message Date
Samuel Holland dc9025c14d util/ifdtool: Fix argument parsing for layout/validate
When `mode_validate` was added, a second copy of `mode_layout` was
accidentally added to the multiple-mode-argument check instead. This
prevents `-f` from working. Fix the check to reference the correct
variable.

Change-Id: Ibac6f090550ff63ec9158355b0450da204a300a7
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-16 08:31:19 +00:00
Arthur Heymans 62b6a8394a drivers/usb: Enable EHCI debug during verstage
Change-Id: I14843c1944f2c1e0a26870b576bac549c0cac7f9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-16 08:29:30 +00:00
Joel Kitching f350768a82 vboot: add new vb2ex_abort callback
Required for new VB2_ASSERT and VB2_DIE macros in vboot code.
(See chromium:972956.)

BUG=b:124141368, chromium:1005700
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I61a1036ccab80862d6eb12f9f72286f29e8478cf
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-16 05:47:25 +00:00
Marshall Dawson 94f249254f util/amdfwtool: Grow the Embedded Firmware Structure
Ensure adequate space exists for all Embedded Firmware Structure
fields.

Field definitions are NDA only.  See PID #55758 "AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors".

BUG=b:141790457
TEST=run on Mandolin

Change-Id: I098ffc7c05d27387a877e6b7c8628d98939bd9af
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35667
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-16 02:29:07 +00:00
Paul Fagerburg ae1e14e438 helios: Add TEMP_SENSOR4 to DPTF
Helios adds TEMP_SENSOR4 to the EC ADC2 pin. Add this to
the DPTF.

BRANCH=None
BUG=b:142266102
TEST=`emerge-hatch coreboot`
Verify that Helios builds correctly.

Change-Id: I3bc19f9b9bd644e134987749ad9a4d875ad8b40a
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-10-15 16:15:25 +00:00
Wisley Chen 1425441ce4 mb/google/hatch: set wifi sar for dragonair
Enable wifi sar feature and set wifi sar name for dragonair sku.

BUG=b:142109545
TEST=emerge-hatch coreboot chromeos-bootimage
1. Check wifi_sar-dragonair.hex in /cbfs-rw-raw/dratini
2. Add iwlwifi.debug into kernel params.
3. check SAR value from dmesg only when sku id is 21/22

Change-Id: I0e08610b7c7d2d8da5a749d278bcde26af590e31
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-10-15 15:59:48 +00:00
Wisley Chen d1eb34e432 mb/google/hatch: Initialize FPMCU_PCH_BOOT1
FPMCU_PCH_BOOT1 pin is connected to GPP_C12. So, config GPP_C12.

BUG=b:142188003
TEST=emerge-hatch coreboot

Change-Id: I73a5c3529330ef3e72f4c7d5fcbbd2f6693494d8
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35845
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-15 15:59:37 +00:00
Patrick Rudolph 5199e826db soc/intel/skylake/chip: Unhide P2SB device
APL unhides the P2SB device in coreboot already. Do the same on SKL/KBL.
As the coreboot PCI allocator needs to be able to find the device,
unhide it after FSP-S.

The device is hidden in the SoC finalize function already and not visible
in the OS, as more P2SB device IDs have been added.

Other SoCs aren't updated, because they are too broken.

Fixes "BUG: XXX requests hidden ...." warnings in coreboot log.
Tested on Supermicro X11SSH-TF.

Change-Id: I0d14646098c34d3bf5cd49c35dcfcdce2c57431d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner
2019-10-15 08:19:31 +00:00
Patrick Rudolph 05bad430b6 soc/intel/common/block/sgx: Fix crash in MP init
On Hyper-Threading enabled platforms the MSR_PRMRR_PHYS_MASK was written
when already locked by the sibling thread. In addition it loads microcode
updates on all threads.

To prevent such race conditions only call the code on one thread, such
that the MSRs are only written once per core and the microcode is only
loaded once for each core.

Also add comments that describe the scope of the MSR that is being
written to and mention the Intel documents used for reference.

Fixes crash in SGX MP init.
Tested on Supermicro X11SSH-TF.

Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35312
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-15 08:19:02 +00:00
Nicolas Reinecke b165c4a46f mainboard/lenovo/t410: Add new port
The port is based on the x201 / t410s.
2537-vg5 / i5, no discrete gpu

Tested and working:
* Native raminit
* Native gfxinit
* Booting Seabios 1.12.1
* Booting from EHCI
* Running GNU/Linux 5.0.0
* No errors in dmesg
* EHCI debug on the devices left side, bottom-right
* Keyboard
* Fn keys (Mute, Volume, Mic)
* Touchpad
* TPM
* Wifi
* Sound
* USB
* Ethernet
* S3 resume
* VBOOT

Testing in progress.

Untested:
* VGA
* Displayport
* Docking station

Bugs:
* AC adapter can't be read from ACPI
* TPM not working with VBOOT and C_ENV BB

Details for flashing externally:
1. Disconnect all power
2. Connect the external flasher
3. Connect the power cord (This fixes internal power control)
4. Remove the power cord

Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/11791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-15 06:47:48 +00:00
Nico Huber 465dd5c524 Documentation/gfx: Update support list of libgfxinit
Also get rid of some manual hyphenation.

Change-Id: Ibeb4eceeae48cf375171d0261ed9475010b0d5b1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-14 19:33:22 +00:00
Arthur Heymans 29e53582cc nb/intel/gm45: Don't run graphics init on s3 resume
This assumes ACPI aware OS also have a driver for this particular
hardware, which is the case for at least Linux. This saves ~60ms on S3
resume.

Change-Id: I2dcd399fee8e2d1cd1b70e60e1669a49c7aa8cb4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-14 08:16:00 +00:00
Arthur Heymans 9ed0df4c38 sb/intel/i82801ix: Add common code to set up LPC IO decode ranges
This does the following:
- Add gen[1-4]_dec options to the devicetree to set up generic LPC
  decode ranges in the southbridge code.
- Move setting up some default decode ranges to a common place. If
  somehow a board needs to override this behavior it can happen in the
  mb_setup_superio() hook (that will be renamed when moving to
  C_ENVIRONMENT_BOOTBLOCK).

Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-14 08:15:49 +00:00
Martin Roth d3a1a4171e src/superio: Remove unused superio chips
These SIOs are not being used or tested by abuild, so remove them from the
tree. The only 3 currently unused SIOs that don't get removed here have board
ports in review.

src/superio/fintek/f71805f
src/superio/fintek/f71872
src/superio/intel/i8900
src/superio/ite/it8671f
src/superio/ite/it8716f
src/superio/nsc/pc87309
src/superio/nsc/pc87360
src/superio/nsc/pc87366
src/superio/nsc/pc97317
src/superio/smsc/dme1737
src/superio/smsc/lpc47b272
src/superio/smsc/lpc47b397
src/superio/smsc/sch4037
src/superio/smsc/sio1036
src/superio/via/vt1211
src/superio/winbond/w83697hf
src/superio/winbond/wpcd376i

Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I61d486d2c1e2b85eb292eaa78316c36e1735ebf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-13 19:36:23 +00:00
Elyes HAOUAS 1eb0e195d6 superio/common: Remove unused include 'pnp_def.h'
Change-Id: I2d0b3d73d646fc43f2562aa5af2358398eaf28b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-13 13:50:24 +00:00
Elyes HAOUAS 457750283a mb/hp/z220_sff_workstation: Remove unused include 'pnp_def.h'
Change-Id: Id8e25caf2868c37c9d7c7717dd908152dfc583a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-13 13:50:06 +00:00
Arthur Heymans 2ea4efeefa nb/intel/nehalem: Start VBOOT in bootblock with a separate verstage
Tested on Lenovo Thinkpad X201, selects slot or recovery just fine.

Change-Id: Ia2b2f2b95510388599266264eaed0d64ce9b6ec5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-13 12:46:32 +00:00
Arthur Heymans 2882253237 nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK
A few notable changes:
- Microcode init is done in assembly during the CAR init.
- The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size
  against which the romstage stack guards protected.
- The romstage mainboard_lpc_init() hook is removed in favor of the
  existing bootblock_mainboard_early_init().

Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-13 12:46:18 +00:00
Arthur Heymans b9c9cd75e7 sb/intel/ibexpeak: Move some early PCH init after console init
Some of the initialization isn't necessary before console INIT is
done.

EHCI debug still works fine on the Lenovo Thinkpad X201.

Change-Id: I0c33efd98844f7188e0258cf9f90049d45145e7c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35949
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-13 11:07:00 +00:00
Arthur Heymans b33d8ce5c7 ec/acpi/ec.c Link EC code in bootblock & verstage
This allows to read and set bits in the EC ram in the bootblock or
verstage. This can be useful if one needs to read a keyboard key as an
input for get_recovery_mode_switch in vboot.

Change-Id: I20b2264012b2a364a4157d85bfe5a2303cc5e677
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-12 12:57:04 +00:00
Maxim Polyakov 4fb80753f5 util/inteltool: remove unsupported MSRs for 06_9EH
Change-Id: I5c1e4d20efa7630bf4e6210591790055ead0161c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:56:23 +00:00
Maxim Polyakov 9ebf5317bc util/inteltool: fix 6d0H-6dfH MSR names for 06_9EH
Change-Id: I92e8f5194114f7756e3858ff13c207daebe8167c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:53:35 +00:00
Maxim Polyakov 3e7ff29995 util/inteltool/cpu: fix IA32_PLATFORM_ID MSR addr
According to the documentation [1], IA32_PLATFORM_ID MSR register
address should be 17H.

[1] Table 2-2. Intel (R) 64 and IA-32 Architectures Software Developer’s
    Manual. Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Change-Id: I9a16b162db51d21c7849b3c08c987ab341845b1e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:42:47 +00:00
Maxim Polyakov 43a98b9589 util/inteltool: remove duplicate MSR for 06_9EH
Change-Id: I34981a69ad027444bc757449db2366f51c13f0e3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:40:58 +00:00
Elyes HAOUAS 3c8f9b8291 mb/biostar/am1ml: Use ite's common functions
Change-Id: I0b1356420c9ae419b2a0a247b9dc6c8e92b7689a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:40:31 +00:00
Elyes HAOUAS cd7adbf9c4 mb/roda/rk886ex: Use pnp_write_config function
Change-Id: Ic56367d64b9304b36f5ba5a4b7d5237574eb73ae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:39:54 +00:00
Elyes HAOUAS d6c8bdc664 mb/getac/p470: Use pnp_write_config function
Change-Id: Iaf9a4608f1b7d25cf5d8dbe2c1489b3d2d00f25a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:39:25 +00:00
Nico Huber 484ad0f1f7 mb/{razer,purism}: Don't select NO_POST
The NO_POST option covers more than classical port 80 output, hence
selecting it seems wrong in any case. The default is still rather
user patronizing, but let's keep it.

As a side effect, this fixes the ability to override the default
for NO_POST which Kconfig rejected while these boards selected it.
(Seems like a bug in Kconfig, though.)

Change-Id: I896b08812b1aa6ce249d7acc8073ebcc0f72eace
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-10-11 15:28:20 +00:00
Arthur Heymans 2437fe9dfa sb/intel/i82801gx: Move CIR init to a common place
Some boards with the G41 chipset lacked programming CIR, so this
change add that to those boards too.

Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-11 12:21:25 +00:00
Arthur Heymans cbe5357de0 vendorcode/eltan/Kconfig: Hide the Kconfig options when lacking support
The vendorcode/eltan mboot and verified boot options only build if a
few other Kconfig options are defined.

Change-Id: Ie333d2fbf294e23ec01df06ee551e2d09541c744
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35954
Reviewed-by: Wim Vervoorn
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-11 07:08:27 +00:00
Arthur Heymans 894240d362 vendorcode/siemens: Remove sourcing non existing Kconfig files
There is only one subdir in vendorcode/siemens and it does not feature
a Kconfig file.

Change-Id: I136743344465cea9c769234aa84d9ebe874ef0d2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-10-11 07:08:18 +00:00
Tim Wawrzynczak bac8e8d8ac mb/google/hatch: Add new touchscreen option for Kohaku
The next board rev will have a new option for an Elan touchscreen.  Add
support for this in the devicetree, as well as use the 'probed' property
on both touchscreen options.

BUG=b:141957731
BRANCH=none
TEST=compiles (next board rev not available yet)

Change-Id: I135e693304cbb8dffc0caf4c07846033d6802208
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-10-11 05:05:03 +00:00
John Su d4697a0de7 mb/google/octopus/variants/fleex: Update GPIOs to fix EMR
Update GPIO_138 and GPIO_139 setting to fix EMR function.

BUG=b:141729962,b:141281846
BRANCH=octopus
TEST=verify EMR function in Grob360S.

Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-10 19:00:03 +00:00
Arthur Heymans 246334390b nb/intel/pineview/Kconfig: Remove romcc leftover
This is unused since C_ENVIRONMENT_BOOTBLOCK is used.

Change-Id: Id5af41e455d211eba89cfeb625f4c728b4145da7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-10 15:38:45 +00:00
Michael Niewöhner 6e66d7b8eb soc/intel: sgx: get rid of UEFI-style usage of global variable
Rework SGX enable status in a clean way without using a global variable.

Change-Id: Ida6458eb46708df8fd238122aed41b57ca48c15b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-10 14:06:09 +00:00
Elyes HAOUAS edfe125bf9 mb/{ibase/mb899,kontron/986lcd-m}: Use pnp_write_hwm5_index function
Change-Id: If30a17d053da8f0758085fc36469b564d46049cd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-10 13:52:45 +00:00
Arthur Heymans 7f9b90f0a6 soc/qualcomm: Remove default ops to generate bootblock.bin
This is done by default in the main Makefile.inc.

TEST: With BUILD_TIMELESS=1 the resulting binary is identical before
and after the change.

Change-Id: Ie85e023df1f1c2b0f115e4f92719a511f60019c3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-09 22:24:56 +00:00
Yu-Ping Wu 0e5b196cb6 soc/mediatek/mt8183: Change argument type of mt_set_emi
Since struct dramc_param has been defined, we can pass the struct
directly from mt_mem_init().

BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: If7333fb579eff76dd9d1c2bf6fdfe7eccb22050f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35846
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09 22:24:00 +00:00
Huayang Duan 078332e4d8 soc/mediatek/mt8183: Run DRAM full calibration
Load the calibration params from flash first and check the correctness
of the params. If the params have correct format, perform DRAM fast
calibration with these params to reduce bootup time. Otherwise, load the
DRAM blob and perform DRAM full calibration.

Bootup time of DRAM partial calibration:
 - 1,349,385 usecs with low frequency
 -   924,698 usecs with middle frequency
 - 1,270,089 usecs with high frequency
3,544,172 usecs in total.

Bootup time of DRAM fast calibration:
 - 216,663 usecs with low frequency
 - 328,220 usecs with middle frequency
 - 322,612 usecs with high frequency
867,495 usecs in total.

BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-09 22:22:41 +00:00
Huayang Duan 846be446d3 soc/mediatek/mt8183: Use cached calibration result for faster bootup
Load calibration params from flash. If the format of the params is
correct, use these calibration params for fast calibration to reduce the
bootup time.

Bootup time of DRAM partial calibration:
 - 1,349,385 usecs with low frequency
 -   924,698 usecs with middle frequency
 - 1,270,089 usecs with high frequency
3,544,172 usecs in total.

Bootup time of DRAM fast calibration:
 - 216,663 usecs with low frequency
 - 328,220 usecs with middle frequency
 - 322,612 usecs with high frequency
867,495 usecs in total.

BUG=b:139099592
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35164
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09 22:22:14 +00:00
Yu-Ping Wu 732e215dd8 soc/mediatek/mt8183: Add the shared 'dramc_param' module
The dramc_param module simplifies the communication between coreboot and
MTK DRAM full calibration blob, and is shared by both implementations to
ensure the same format of parameters.

BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-09 22:21:10 +00:00
Yu-Ping Wu 093d8ea323 soc/mediatek/mt8183: Simplify usage of dramc_engine2_end
Since we always write to &ch[chn].ao.dummy_rd after calling
dramc_engine2_end(), this write could be merged into dramc_engine2_end()
to simplify code.

BUG=none
BRANCH=none
TEST=emerge-kukui coreboot

Change-Id: Ibb4bd5ed016118811ad2097098417c19f00f4263
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35749
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09 22:20:05 +00:00
Arthur Heymans 3cde494000 sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage
This is now done during the romstage.

Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-09 22:18:57 +00:00
Bernardo Perez Priego a31e6e8497 mb/google/drallion: Enable UART console for arcada_cml and sarien_cml
Drallion uses UART 0 for console, other two variants remain as UART 2.

BUG=b:139095062
TEST=emerge-drallion coreboot chromeos-bootimage.
     Console should be visible.

Change-Id: I520a07ad6f755bc2e6481329fc69bef9a36e31e2
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35785
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09 22:17:36 +00:00
Wisley Chen 2ef5d1af86 mb/google/hatch: Remove pen device for dratini/dragonair
Dratini/Dragonair doesn't support pen insertion/ejection feature,
so remove it.

BUG=b:142159117
TEST=emerge-hatch coreboot

Change-Id: I64859a162d8dc75ffe55d98b72a056dd72e8de75
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-10-09 22:16:51 +00:00
Greg V 84c491a8c8 mb/[google/intel/lenovo]/*: fix posix shell bug with SPD files
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape
in the same way bash/zsh do. As a result, the decoded files ended up
with ASCII numbers instead of the decoded binary data.

Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68
Signed-off-by: Greg V <greg@unrelenting.technology>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-09 22:16:40 +00:00
Greg V ae47a6f4fa ec/google/chromeec: fix format security warning
Change-Id: I7a7bcb56523d595e8d4f32849aac53d66d416a12
Signed-off-by: Greg V <greg@unrelenting.technology>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35866
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09 22:15:38 +00:00
Greg V 1c3dbdbbf6 drivers/spi: ignore -Wvla on clang too
Change-Id: I99bc6877680b32f2bae78437ab0482baa65496d8
Signed-off-by: Greg V <greg@unrelenting.technology>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-09 22:15:18 +00:00
Himanshu Sahdev fa6024e15e acpi_table_header: Replace hard-coded length via sizeof(acpi_fadt_t)
Minimize use of hard-coded value for acpi_table_header->length to soft
code. Replace length of acpi_header_t with sizeof(acpi_fadt_t).

Change-Id: Ibcae72e8f02497719fcd3f180838557e8e9abd38
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-10-09 22:14:54 +00:00
Shelley Chen 9b93383f5b mb/google/hatch: Set FPS as wake source
BUG=b:142131099
BRANCH=None
TEST=powerd_dbus_suspend, ensure DUT in S0ix
     touch fp sensor and ensure DUT wakes up in S0

Change-Id: If57094aa1076d79ac0886b71fa5532411bfeb45f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-09 22:01:23 +00:00