Commit Graph

39508 Commits

Author SHA1 Message Date
Shelley Chen dd6b0610e3 soc/qualcomm/common: Increase SPI gpios drive strength to 8mA
EE requested that we increase the drive strength for the SPI lines to
8mA.

BUG=b:198627043
BRANCH=None
TEST=EE help verify

Change-Id: Ic887a7eef74f1063f7284db042c5fbd2e1d5bd4c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-01 01:20:58 +00:00
Jakub Czapiga 48f6c2b46f util/cbmem: Add FlameGraph-compatible timestamps output
Flame graphs are used to visualize hierarchical data, like call stacks.
Timestamps collected by coreboot can be processed to resemble
profiler-like output, and thus can be feed to flame graph generation
tools.

Generating flame graph using https://github.com/brendangregg/FlameGraph:
  cbmem -S > trace.txt
  FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg

TEST=Run on coreboot-enabled device and extract timestamps using
     -t/-T/-S options

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-31 23:04:58 +00:00
Tony Huang f00ab8c26a mb/google/brya/var/agah: Replace amp max98390 with max98360
Based on the latest schematic, agah will replace the Maxim 98390
speaker amps with Maxim max98360. This patch updates the
devicetree entries to reflect that.

BUG=b:210970640
BRANCH=brya
TEST=emerge-draco coreboot

Change-Id: I7ea36d276f7ffeae1510483027092e2bc59690fc
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-31 15:03:36 +00:00
Tony Huang bcfc87dbff mb/google/brya/var/agah: Add GL9750 SD card reader support
BUG=b:210970640
TEST=emerge-draco coreboot

Change-Id: I881c2c1ad7b0d10b7ae38fcd9814f757cf56feb5
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-31 15:03:04 +00:00
Dtrain Hsu 67f32c0365 mb/google/brya/var/kinox: set GPP_D0 to NC
Brask set GPP_D0 to GPO in commit b0769db4, but Kinox doesn't support
fingerprint. This patch sets GPP_D0 to NC for matching schematic.

BUG=b:214025396
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I38b9eb2df83cfbdb58d95cb178c1d767299aa4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-31 15:00:00 +00:00
John 7cd968e69b soc/intel/common: Add Kconfig SOC_INTEL_CSE_SET_EOP
The do_send_end_of_post function is implemented in the cse_eop.c file.
This change adds the Kconfig SOC_INTEL_CSE_SET_EOP in cse.c to avoid
build issue.

Change-Id: Ib52404d9ad4c01a460e4cfef331c529d2a53337a
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-03-31 14:22:21 +00:00
Patrick Rudolph ac49aaf0f9 drivers/intel/fsp1_1: Fix code not working with strict-aliasing rules
Change-Id: Ifc95a093cf86c834d63825bf76312ed21ec68215
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-31 14:21:27 +00:00
Patrick Rudolph d7803c89b6 vendorcode/intel: Remove UDK2015 headers
The headers are now unused, drop them.

Change-Id: Ibfaa3029ddc614935481ce736c9d971bf4831b5d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-31 14:21:06 +00:00
Patrick Rudolph 05ca05466c Kconfig: Select UDK2017
On platforms using UDK2015 select UDK2017 instead.
This allows to drop UDK2015 headers.

Tested using timeless builds: The produced binaries are identical.

Change-Id: Ia6032c6520ec889cd63655db982d9bfa476dc24d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-31 14:20:44 +00:00
Patrick Rudolph dcf30e837b soc/intel/denverton_ns: Resolve macro conflicts with UDK2017 headers
Replace LShiftU64 and RShiftU64 as the defined macro conflicts with
UDK2017 headers.

Tested using timeless builds: The produced binaries are identical.

Change-Id: I8f205f663be9c9c31cf384ca89370afa48ca1e15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-31 14:20:22 +00:00
Jianjun Wang 79b35ca481 soc/mediatek/early_init: Fix function return type
Fix return type of early_init_get_elapsed_time_us() to comply with the
data type of return value.

Also replace memset() with struct initializer.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Fixes: commit 41faa22 (soc/mediatek: Add early_init for passing data
       across stages)
Change-Id: I7c361828362c2dfec91358ad8a420f5360243da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-31 01:50:42 +00:00
David Wu e1e30b1504 mb/google/brya/var/kano: Remove SAR sensor
RF team comfirmed that SAR sensor is not necessary for MP,
therefore remove the corresponding entries from the devicetree.

BUG=b:202978964
TEST=Build pass.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I31faf18563848f8d6787fe70bfb28006efea8427
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 23:57:43 +00:00
Terry Chen 239d7d0e5d mb/google/brya/variants/crota: Add memory config for crota
Fill in the memory config based on the the schematic by bernadino 14 adl-p 20220112.pdf

BUG=b:219891328

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 23:55:46 +00:00
David Wu ad2e4eaf7a Revert "mb/google/brya/var/kano: adjust I2C3 speed"
This reverts commit 65aaccda59.
Reason:
1. Fix firmware messages show [ERROR] dw_i2c:invalid bus speed 390000
2. Measure DVT I2C3 speed < 400KHz.

BUG=b:215095284
TEST=There isn't ERROR messages and verify I2C3 speed < 400KHz.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5982c82a55710824692b41e263418e4b4d420b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 23:55:30 +00:00
Sridhar Siricilla abe0d810f0 soc/intel/alderlake: Log CSE RO write protection info for ADL
The patch logs CSE RO's write protection information for Alder Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.

TEST=Verify the write protection details on Gimble.

Excerpt from Gimble coreboot log:
	[DEBUG]  ME: WP for RO is enabled        : YES
	[DEBUG]  ME: RO write protection scope - Start=0x1000, End=0x15AFFF

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 23:55:15 +00:00
Felix Held e3ee917cba soc/amd/sabrina/makefile: use Sabrina as SoC name in amdfwtool call
Now that the amdfwtool support for Sabrina is in place, change the
SoC name parameter passed to amdfwtool from Cezanne to Sabrina.

The fw.cfg file still points to the Cezanne binaries, but since
commit 9cb0a05dfb (soc/amd/sabrina: Add
prompt for AMDFW_CONFIG_FILE) this can be overridden via the Kconfig
config file in the build. As soon as the Sabrina PSP binaries are
available in 3rparty/amd_blobs, the fw.cfg file will be updated to use
the correct ones for Sabrina.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53a8de222e39bd2b92c07661b6c52a02fb651609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63189
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:42:39 +00:00
Felix Held dd031ffee8 soc/amd/sabrina/makefile: drop PSP_S0I3_RESUME_VERSTAGE handling
The PSP_S0I3_RESUME_VERSTAGE Kconfig symbol is only defined in the
Cezanne Kconfig, so drop this from the Sabrina makefile.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9571a302d427981cdf750a1cb3b7f4db9d61a87c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63188
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:42:28 +00:00
Raul E Rangel 879a2789ee mb/google/skyrim: Call espi_switch_to_spi1_pads
We are using the second SPI pads for eSPI.

BUG=b:226635441
TEST=Build skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I43713d7376a28ced2be635668836464ceec46392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63096
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 22:42:01 +00:00
Raul E Rangel d0b059fcd4 soc/amd/sabrina: Add espi_switch_to_spi1_pads
The way to select the pads has changed from Cezanne.

BUG=b:226635441
TEST=Build skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I96baf6b9c169ed61d221352b29ac676bca40da21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63095
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 22:41:53 +00:00
Kyösti Mälkki 1d8c7da5b4 ChromeoS: Retain ACPI CNVS contents on S3 resume
For platforms without EC_GOOGLE_CHROMEEC S3 resume path
always reported ACTIVE_ECFW_RO because acpi_fill_cnvs()
and mainboard_chromeos_acpi_generate() were not called.

Change-Id: Iea71a51aba7ab1b6966389c17a1e06ccc96ae0e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 21:43:00 +00:00
Chris.Wang 4a45771edf mb/google/guybrush/var/dewatt: add specific SPD hex for dewatt
Add the specific SPD hex file for the Samsung memory part with
updating the part number into the SPD table. The ABL needs to
identify the part by checking SPD data to do the proper tuning.

BUG=b:224884904
TEST=Build, validate the SPD data has been applied.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-30 21:40:30 +00:00
Jakub Czapiga 2b3e6d6736 commonlib/timestamp_serialized: Add timestamp enum to name mapping
Some solutions require readable form of timestamps, which does not
contain spaces. Current descriptive timestamp names do not meet this
criteria. Also, mapping enums to their text representation allows for
quick grepping (use of grep command) to find relevant timestamps in the
code.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-30 21:21:53 +00:00
Jakub Czapiga 9760264a96 commonlib/bsd/helpers: Remove redundancy with libpayload defines
Move STRINGIFY() from coreboot string.h to commonlib/bsd/helpers.h
Remove redundant defines from libpayload.h and libpayloads' standard
headers.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-30 21:21:47 +00:00
Terry Chen 707eaced71 mb/google/brya/variants/crota: init overridetree for crota
init overridetree.cb based on the schematic bernadino 14 adl-p 20220112.pdf

BUG=b:226315394

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 15:16:14 +00:00
Frank Wu ebd6dec110 mb/google/brya/var/banshee: Update the GPP_D12 as USB_C3_LSX_RX
Update the GPP_D12 according to USB_C3_LSX_RX.

BUG=b:225081954
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The device can be recognized when it is attached in port3.
localhost /sys/bus/thunderbolt/devices # ls
0-0  1-0  1-0:3.1  1-3  domain0  domain1

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I38caa76c855e683eb0587eb67ee9abc91af4545d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30 15:08:51 +00:00
Jianjun Wang 1c27671504 mb/google/cherry: Add PCIe domain support for dojo
Add override device tree for dojo and add PCIe domain support.

Reference:
  - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-30 14:59:55 +00:00
Joey Peng 51a43f922c mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo
Add thermal table settings for tarlo which shares the same firmware with
taeko

BUG=b:215033683
TEST=emerge-brya coreboot

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 14:54:49 +00:00
Yu-Hsuan Hsu 2363f0563c mb/google/guybrush: Disable EN_SPKR on init
We don't want to enable the speaker on init. It will be enabled while
using GPIO AMP codec in depthcharge.

BUG=b:223289882
TEST=boot guybrush and verify the devbeep and gpio value in kernel

Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30 14:26:04 +00:00
Sean Rhodes 0b158d43df mb/starlabs/lite: Move Verb Table to variant directory
Move the verb table to variant directory to allow for different tables
for different variants.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4260188057d1c3b4e6ea7c82f085fad0cc244881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30 14:23:08 +00:00
Sean Rhodes b5fbb55f0c ec/starlabs/merlin: Add GLKR variant
Add GLKR (N5030) Lite Mk IV variant

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1e17130caa16a605d0d3207d41527df3db6ada81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30 14:22:50 +00:00
Sean Rhodes 78342989c4 ec/starlabs/merlin: Add support for Nuvoton EC's
Support was created for the NPCE9m5x series, using version 1.1
of the datasheet. The specific model tested was the NPCE985P/G,
on the StarLite Mk IV with version 1.00 of the EC firmware.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib66baf1e88f5d548ce955dffa00c9b88255b2f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30 14:22:08 +00:00
Sean Rhodes 6082ee5281 ec/starlabs/merlin: Make EC function names generic
Rather than using `ite_`, use `ec_` so the same functions
can be called for different ECs.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie61af233f731eb47772af1c82c6abdc515bc89cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30 13:49:22 +00:00
Sean Rhodes 36e2b4b2b4 ec/starlabs/merlin: Rename ec.c to more specific ite.c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0bac5e4c101792dd4c6a0d4a1ae4a4c7fcd837d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30 13:48:11 +00:00
Reka Norman f08e3bb516 drivers/tpm: Force enable long IRQ pulses for Ti50 versions under 0.15.
Only Cr50 versions starting at 0.5.5 support long IRQ pulses, so this
feature is enabled based on the value of the board_cfg register (see
CB:61722).

However, Ti50 versions below 0.0.15 don't support the board_cfg
register, and trying to access it will cause I2C errors (see CB:63011).
Also, all Ti50 versions only support long IRQ pulses. Therefore, add a
workaround to force enable long IRQ pulses for boards using Ti50
versions under 0.0.15, instead of enabling it based on board_cfg. This
workaround will be removed once all Ti50 stocks are updated to 0.0.15 or
higher.

BUG=b:225941781
TEST=Boot nivviks and nereid to OS with Ti50 0.0.14 and check there are
none of these I2C errors:
[ERROR]  I2C stop bit not received
[ERROR]  cr50_i2c_read: Address write failed
[ERROR]  cr50_i2c_tis_status: Failed to read status

Change-Id: Iaba71461d8ec79e8d6efddbd505339cdf1176485
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63160
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 13:40:30 +00:00
Eric Lai e156b2bcec mb/google/nissa/var/nivviks: Move WWAN power on sequence forward
Move WWAN power on sequence from OS to coreboot. This can save the
WWAN initial time about 10S. Another purpose is power resource be
removed because we don't power off the LTE in S0ix.

BUG=b:223490884
TEST=FM101-GL work as expected.
Enumerate time from
[   17.747145] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd
[   17.760192] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04
[   17.760210] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[   17.760215] usb 4-2: Product: Fibocom FM101-GL Module
[   17.760220] usb 4-2: Manufacturer: Fibocom Wireless Inc.
[   17.760224] usb 4-2: SerialNumber: 9c88998f
to
[    3.936409] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd
[    3.966695] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04
[    3.989989] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[    4.003813] usb 4-2: Product: Fibocom FM101-GL Module
[    4.019760] usb 4-2: Manufacturer: Fibocom Wireless Inc.
[    4.019762] usb 4-2: SerialNumber: 9c88998f

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0f3fe999ae3a109b739629948b619a389a9059b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-30 13:40:10 +00:00
Sridhar Siricilla 0f5ca5ad8c mb/intel/adlrvp: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig for
ADL RVP board. The flag updates PMC settings in the IFD for Alder Lake
A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is
locked in the production systems, so the Kconfig is deselected.

TEST=Build the coreboot for adlrvp

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-30 13:39:54 +00:00
Felix Held a84c00c9ce mb/amd/chausie/port_descriptors: update DDI descriptors
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I31db6c138a21dc22e7aa473f2215ca2c7594326c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63163
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 01:18:14 +00:00
Felix Held 621a8d69d9 mb/amd/chausie/devicetree: update PCI root ports
Only enable the PCIe root ports that have corresponding DXIO descriptors
and also update the comments to have them match the actual hardware
configuration.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I378c620abb6e52de680669b6edd228874153e399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 01:18:02 +00:00
Felix Held 2b4d1480d6 mb/amd/chausie/port_descriptors: update DXIO descriptors
Change the DXIO descriptors to match the default PCIe lane mapping on
the chausie board. With this configuration and a board-level rework to
bypass the EC control of the NVMe SSD power supply rail, this
configuration results in the SSD being detected on the root port on bus
0 device 2 function 3 and usable as boot device. This was also validated
against the schematics revision B.

Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 01:17:53 +00:00
Raihow Shi c55012bd2a mb/google/brask/variants/moli: update GPIOs for moli
Follow the Moli GPIO Table_20220324.xlsx to update it.
1.Set A15 as the default value.
2.Set A14, A19 NC.
3.Set C3, C4 as the default value.
4.Set D9 as the default value.
5.Set E5, E13 as the default value.
6.Set R4, R5  as the default value.
7.Update E14.
8.Set E12 as the default value.
9.Set D16 as the default value.

BUG=b:220821454
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia54256244111a99cb130b74f78c37815099a021a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30 00:04:48 +00:00
Tim Wawrzynczak 5e9f8a4181 mb/google/brya/var/agah: Fix GPU GPIOs
While adding this train of patches to program the dGPU power sequences,
I noticed some of the GPU GPIOs are incorrectly programmed in ramstage,
so this patch fixes the settings.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I622b1f5cfba84727bb31792358ca4162c7fa9f52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-30 00:04:28 +00:00
Kenneth Chan 1aaa120ae6 mb/google/guybrush/var/dewatt: Update telemetry value
AMD SDLE testing had been done and apply the following telemetry settings for dewatt EVT:
vdd scale:  91288
vdd offset: 279
soc scale:  29785
soc offset: 461

BUG=b:219626910
TEST=1. emerge-guybrush coreboot
     2. pass AMD SDLE test

Change-Id: I4456ffddbf9963f1202a349abe52df2bbb726468
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63136
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 00:03:40 +00:00
Arthur Heymans 4a3331d93c device/pci_device.c: Return if the scan parameter is invalid
Clang is unhappy about codepath of an invalid parameter because
variables remain unset.

Change-Id: I1ba392a48cf3f81a29d9645e5cf220b122d588af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30 00:03:08 +00:00
Igor Bagnucki f0d65213c0 src/console/Kconfig: Add option to disable loglevel prefix
This patch adds an option to disable loglevel prefixes. This patch helps
to achieve clear messages when low loglevel is used and very few
messages are displayed on a terminal. This option also allows to
maintain compatibility with log readers and continuous integration
systems that depend on fixed log content.

If the code contains:
  printk(BIOS_DEBUG, "This is a debug message!\n")
it will show as:
  [DEBUG]  This is a debug message!
but if the Kconfig contains:
  CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
the same message will show up as
  This is a debug message!

Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Change-Id: I911bb601cf1933a4c6498b2ae1e4cb4d4bc85621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-30 00:02:34 +00:00
Karthikeyan Ramasubramanian 773876401d mb/google/skyrim: Disable PSP postcodes
ESPI is not initialized in PSP. Hence any attempt to write to port80
causes failure to boot. Disable PSP postcodes for now and re-enable it
later after ESPI is initialized in PSP.

BUG=b:224618411
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-29 23:32:21 +00:00
Karthikeyan Ramasubramanian 4a8bbea154 soc/amd/sabrina: Do not clear Port80 enable bit in ESPI Decode
This is done to work around a hang when SMU writes to port80. Remove it
after the issue is fixed.

BUG=b:224618411
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63122
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29 22:03:20 +00:00
Jianjun Wang aa751cc371 soc/mediatek: Ensure PERST# deassertion time follows the spec
According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. To ensure the 100ms
delay requirement is met, calculate the elapsed time since assertion. If
it is smaller than 100ms, do an extra delay.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the measured PERST# time:
[DEBUG]  mtk_pcie_domain_enable: 432517 us elapsed since assert PERST#
[INFO ]  mtk_pcie_domain_enable: PCIe link up success (17 tries)

And the SSD information in boot log is as follows:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29 15:41:50 +00:00
Jianjun Wang 2183484e7a mb/google/cherry: Pre-initialize PCIe at the bootblock stage
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be
delayed 100ms (TPVPERL) for the power and clock to become stable.

Instead of asserting PERST# right before PCIe initialization and waiting
for 100ms, which is currently the only function of 'mtk_pcie_pre_init',
so that the extra 100ms delay in ramstage is avoided.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29 15:41:43 +00:00
Jianjun Wang acf16bf4f6 soc/mediatek/mt8195: Add early init support
Add early init support for MT8195 platform.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29 15:41:37 +00:00
Jianjun Wang 41faa22c53 soc/mediatek: Add early_init for passing data across stages
Add support for "early_init_data" region, which can be used to store
data initialized in an early stage (such as bootblock), and retrieve it
in later stages (such as ramstage).

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29 15:41:30 +00:00