Commit graph

39508 commits

Author SHA1 Message Date
Fred Reitberger
81ee8e2f2e soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resume
SMMINFO is already set up in S5, so it should be skipped in S3 resume

TEST=builds

Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25 18:51:22 +00:00
Fred Reitberger
8e3c6f8d33 soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume
SMMINFO is already set up in S5, so it should be skipped in S3 resume

BUG=b:194990818
TEST=Build guybrush

Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25 18:51:12 +00:00
Felix Held
c35790012f soc/amd/sabrina: update soft fuse bit 15 definition
For SoC that don't support LPC any more the definition of the PSP soft
fuse chain bit 15 has changed. Earlier SoCs that still supported a
physical LPC bus used this bit to determine if the I/O port 0x80 POST
code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a
physical LPC bus any more and on those this bit selects if the PSP debug
output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that
the needs to be decoded to eSPI.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25 18:49:43 +00:00
David Wu
24d40fd698 mb/google/brya: Adjust FMD file to chromeos.fmd for kano
The separate FMD file for Kano is no longer required, as it was
only required for early prototype testers, and those devices will
be retired soon, therefore switch back to the original FMD file.

BUG=b:226018550
TEST=Build pass.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25 15:58:52 +00:00
Eric Lai
c4ca20f67f drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15
Ti50 FW under 0.15 is not support board cfg command which causes I2C
errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed.
Add workaround for the old Ti50 chip.

BUG=b:224650720
TEST=no I2C errors in coreboot.
[ERROR]  cr50_i2c_read: Address write failed
[INFO ]  .I2C stop bit not received

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-25 15:58:19 +00:00
Michał Żygowski
66f99f7fa7 mb/dell/snb_ivb_workstations: Add Precision T1650 support
Precision is a Mid Tower chassis platform with very similar mainboard
to OptiPlex 9010. It has one more PCIe port and a PCI port. It also
incorporates C216 chipset instead of Q77 and enables DRAM ECC support.
Other changes are related to subsystem ID and fan control
initialization.

TEST=Boot Dell Precision T1650 and launch Debian 10.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4ec2013d5f53af36cab0d1def19272f5ef1a9516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-03-25 09:28:47 +00:00
Michał Żygowski
7e8b597093 mb/dell: Convert OptiPlex 9010 into directory with variants
New boards like Dell Precision T1650 will be added as variants, in
subsequent commit. They share most of the code, except some EC
initialization tables, PCIe port configuration and subsystem ID.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-03-25 09:26:40 +00:00
Sridhar Siricilla
b017a43a6d soc/intel/common: Add APIs to check CSE's write protection info
The patch add APIs to check CSE Region's write protection information.
Also, adds helper functions to get the SPI controller's MMIO address
to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read
protection details.

During the coreboot image build, write protection is enabled for CSE RO.
It is enabled through a Intel MFIT XML configuration.

TEST=Verify write protection information of CSE Region

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-24 17:34:40 +00:00
Raihow Shi
cb772e54a3 drivers/net/r8168: Add support for Realtek RTL8111K
The Realtek RT8168 and RTL8111K have a similar programming interface,
therefore add the PCI device ID for the RTL8111K into driver for support.

BUG=b:226253265
TEST=emerge-brask coreboot chromeos-bootimage.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I5ad8f14483393d6f25026847cc0d4229d362bba0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-24 15:47:37 +00:00
Varshit B Pandya
b6ebcdfde5 driver/wifi: Add _DSM method for DDRRFIM
coreboot needs to propagate the CnviDdrRfim value info of the feature
enable/disable state into the CNVi via the WiFi DSM ACPI object. This
will be consumed by the Wi-Fi driver and it will act according to
CB enablement configuration. This patch adds _DSM method for that.

Add support for following 2 functions in _DSM method

- Function 0: Function Support Query Returns a bitmask of functions
  supported.
- Function 3: RFI enablement 0 Feature Enable 1 Feature Disable

Note: Wifi Dsm already has provision for SAR. This patch will add
additional support to return RFIM structure based on UUID.

BUG=b:201724512
TEST=Build, boot brya0 and dump SSDT entries

Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
	ToBuffer (Arg0, Local0)
	If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd")))
	{
		ToInteger (Arg2, Local1)
		If ((Local1 == Zero))
		{
			Return (Buffer (One)
			{
				0x09
			})
		}

		If ((Local1 == One)){}
		If ((Local1 == 0x02)){}
		If ((Local1 == 0x03))
		{
			Return (Zero)
		}

		Return (Buffer (One)
		{
			0x00
		})
	}

	Return (Buffer (One)
	{
		0x00
	})
}

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-03-24 07:17:08 +00:00
Mark Hsieh
6156a84932 mb/google/brya/var/gimble: Include 4 new SPDs
Add the four SPD files for LPDDD4 memory parts below to gimble:
1. Hynix H54G56CYRBX247
2. Hynix H54G46CYRBX267
3. Samsung K4UBE3D4AB-MGCL
4. Samsung K4U6E3S4AB-MGCL

BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot"

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I143207cda066603051803b9008eb2e2364f16e46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-24 02:20:08 +00:00
Karthikeyan Ramasubramanian
9cb0a05dfb soc/amd/sabrina: Add prompt for AMDFW_CONFIG_FILE
This will allow configuring the concerned config through an external
defconfig file.

BUG=None
TEST=Ensure that AMDFW_CONFIG_FILE is configurable.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I97817a822c8c41822e699adc31f0e7452f93fdb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62971
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23 21:30:30 +00:00
Kevin Chiu
47da16dc33 mb/google/guybrush/var/nipperkin: update telemetry settings
Update the two load line slope settings for the telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.

VDD scale: 73331 -> 94623
VDD offset: 1893 -> 1847
SOC scale: 31955 -> 29904
SOC offset: 852 -> 756

BUG=b:217963719
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
     pass AMD SDLE/Stardust test

Change-Id: Icad97644dd9391a325dfe1dbb1ec176e1f6d3dc3
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-23 21:29:21 +00:00
Zheng Bao
fb9b784ca2 amdfwtool: Change the some FW's level for A/B recovery
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.

The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.

Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-23 20:17:45 +00:00
Jon Murphy
65e43dd1a8 mb/google/skyrim: Fix Backlight GPIO
Backlight GPIO was set to HIGH, when it should have been set LOW to
enable the backlight in the embedded display.

BUG=b:224618411
TEST=load on Skyrim proto1, observe backlight

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ife3335ca5a3c2517a6817fccf0544e5fcacb1f9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63003
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23 19:38:09 +00:00
Robert Zieba
e2bde83a51 soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present
before enabling the corresponding gpp_clkx_clock_request_mapping bits
which may cause issues with L1SS. This change sets the corresponding
gpp_clkx_clock_request_mapping to off if the corresponding device is
disabled.

BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value
when devices are enabled/disabled, checked that physically removing a
device that is marked as enabled also disables the corresponding clk req
BRANCH=guybrush

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23 19:37:36 +00:00
Joey Peng
e58de0db45 mb/google/brya/var/taniks: Increase TSR2 threshold from 40 °C to 70 °C
Change settings according to thermal team test results

BUG=b:215033682
TEST=build and tested fan works normally on taniks

Change-Id: I567815782ece4ab7fcec7da6b787ee9eec27aba4
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-23 19:37:15 +00:00
Zheng Bao
258405aa06 soc/amd/cezanne: Add PSP Bootloader for AB recovery in fw.cfg
TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is bootloader for A/B
recovery. Both bootloader can be put in the fw.cfg. The amdfwtool
decides which booloader is dropped in the directory.

Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-03-23 19:32:21 +00:00
Michał Żygowski
b825d9435d mb/dell/optiplex_9010/sch5545_ec.c: Fix HWM initialization bugs
Fix the HWM sequence matching to the chassis. HWM sequence for SFF
was incorrectly passed to MT chassis HWM initialization.

Vendor code also applies a fix-up for MT/DT chassis. This fixup was
missing one register read compared to the vendor code. Add the missing
read and guard the fixup depening on the returned value to match the
vendor code behavior. Not doing so resulted in increased fan speeds
on Dell Precision T1650 compared to Dell's firmware.

TEST=Boot Dell Precision T1650 and hear the fans are as silent as on
Dell's firmware

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5c0e1c00e69d66848a602ad91a3e83375a095f44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-03-23 18:14:53 +00:00
Karthikeyan Ramasubramanian
1a24d84566 soc/amd/common/psp_verstage: Write postcodes after ESPI init
On boards where PSP uses ESPI to write postcodes, update the verstage to
do it after ESPI initialization.

BUG=b:224543620
TEST=Build and boot to OS in Nipperkin. Ensure that there are no
attempts to write the post code from PSP verstage before ESPI
initialization.

Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mohan Viswanathan
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-23 16:13:42 +00:00
Teddy Shih
2bd4c98c42 mb/google/dedede/var/beadrix: Enable LTE function by FW_CONFIG option
Enable/disable LTE function based on LTE field of FW_CONFIG.
1. GPIO control
2. USB port setting

BUG=b:213582491
BRANCH=dedede
TEST=FW_NAME=beadrix emerge-dedede coreboot

Change-Id: Icea44992e2e3195d1fd9a888f5ce4650f82280bb
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62801
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23 14:59:31 +00:00
Maulik V Vaghela
85a09ef99b soc/intel/adl-n: Add device ID for TCSS XHCI
This patch adds TCSS XHCI device ID for ADL-N CPU which is required
for USB3 port enumeration.

Document Reference: 645548 revision 1.0 (Chapter 2.3)

BUG=None
BRANCH=None
TEST=Check if device is detected correctly and ACPI entries are
generated for device 0d.0

Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-23 14:59:12 +00:00
Michał Kopeć
a691cbd2eb drivers/pc80/tpm/tis.c: Use fixed TPM ACPI path
Windows 11 installer expects the TPM to reside under \\_SB_.PCI0 in
ACPI device hierarchy, otherwise the TPM is not detected. Hardcode
the path to fix the issue.

TEST=Boot Windows 11 on Clevo NV41MZ and see the TPM is detected
correctly

TEST=Boot Ubuntu 20.04 on Clevo NV41MZ and see the TPM is detected
correctly

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: If0b3136e3eb8eb1bb132132a5f3a7034bdd3b424
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23 14:58:52 +00:00
Terry Chen
5deefc8bd3 mb/google/brya/var/primus{4es}: add delay time to rtd3-cold
This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.We checked power on sequence requires enable pin prior to reset pin, added delay to meet the sequence and test passed on various eMMC SKUs.Base on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.

BUG=b:224648680
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
          test suspend stress 2500 cycles passed on primus

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-23 14:37:34 +00:00
Xi Chen
ad63eabe3a src/mediatek/mt8186: Implement sdram_size() to get real dram size
Originally, dram size is hard-coded to 4GB by default. To support
different dram size, calculate it from the mem chip info stored
in CBMEM.

BUG=b:206014043
TEST=Output "dram size: 0x100000000" on Kingler

Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-23 11:54:28 +00:00
Xi Chen
555c2aeb67 soc/mediatek: Save dram info to cbmem
Store dram info in cbmem for ramstage or payloads to use.

BUG=b:206014043
TEST=Build pass on Kingler

Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-23 11:54:21 +00:00
Sergii Dmytruk
206328d57b lib/device_tree.c: zero-initialize new DT nodes
Prevents bad things from happening later when these new nodes are used.

This issue is hard to observe because:
 1. Heap is zero-initialized, so you need to use allocated memory
    filling it with non-zero values, free, allocate it again, use
    uninitialized.
 2. Most of allocated memory is not freed.
 3. Implementation of free() does something only for one last malloc'ed
    block, making most of freed memory unavailable for future
    allocation.

Change-Id: I38a7ec1949d80f7a2564fac380ce94de6056a0c7
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62928
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22 20:45:26 +00:00
Tim Wawrzynczak
9ad63e4460 mb/google/brya/var/moli: Fix overridetree
Commit 5a0ad1186 missed one chip config member that got converted to
snake case in commit 215a97ee1.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie92106f0fee0bb18863b7063c07673e0f7995c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63005
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22 20:36:25 +00:00
Tim Wawrzynczak
ec5a5cc292 drivers/tpm/cr50: Use cr50_get_firmware_version in get_board_cfg
cr50_get_board_cfg() may be called in ramstage for some mainboards in
order to determine the BOARD_CFG register's value. The code was
written assuming that the firmware version was already retrieved, but
for boards calling this in ramstage, this is not the case. Therefore,
instead of using the cached cr50_firmware_version (which is all 0s in
ramstage at that time), use the cr50_get_firmware_version function
instead.

BUG=b:225206079, b:220685274
BRANCH=firmware-brya-14505.B
TEST=boot on brya0 and see:
[INFO ]  Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.93/cr50_v3.94
[INFO ]  Enabling GPIO PM b/c CR50 has long IRQ pulse support
in the logs.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia6e5f4965a8852793d2f95e6eb21ea87860335a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-22 20:02:20 +00:00
Raihow Shi
5a0ad11868 mb/google/brask/variants/moli: init overridetree for moli
init overridetree.cb based on the schematic adl_rfq_mb_20220310.pdf

BUG=b:220814038

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-22 19:01:46 +00:00
Terry Chen
f613ce0479 mb/google/brya/variants/crota: set up gpio
Set the GPIO configuration of crota by bernadino 14 adl-p 20220112.pdf

BUG=b:219891328

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-22 19:01:25 +00:00
Felix Held
390a28057c soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC device
Despite the SMBus device being function 0 of the FCH PCI device, the
MMIO resource of the FCH IOAPIC is on the LPC device which is function 3
of the same PCI device, so move the FCH IOAPIC initialization code to
the LPC device. Since the HPET was enabled in the same function, also
move it to the LPC device initialization.

TEST=On Mandolin both IOAPICs are still correctly detected by Linux.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22 17:05:21 +00:00
Dtrain Hsu
5d3b1bbce4 mb/google/brya/var/kinox: Modify DDR4 to non-interleaved
Kinox is designed to 8-layer PCB. In order to reduce the length of
memory singals, the DDR4 is designed from interleaved to
non-interleaved.

BUG=b:210094309
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-22 15:21:26 +00:00
Kevin Chang
1f54599b98 mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
GL9763e doesn’t support L0s state, so disable L0s at the root port.

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
2022-03-22 05:04:50 +00:00
Kevin Chang
6e52c1da4a soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config
This change provides config for devicetree to control ASPM per port

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles on taeko.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-22 05:01:57 +00:00
Kevin Chang
4b1f25d82f mb/google/brya/var/taeko: Enable Genesys L1 max entry delay
The workaround causes the eMMC controller to not enter its L1 
during the boot process

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
2022-03-22 03:46:59 +00:00
Ben Chuang
15854c9134 drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
Add an option to set L1 entry delay to Max for GL9763E. The L1 entry
delay will be changed to expected value by sdhci-pci-gli driver in
Linux v5.14.

BUG=b:220079865
TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is
0x3FF.

Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-03-22 03:45:30 +00:00
Yu-Ping Wu
374e6b4080 mb/google: Remove unused cpu device
The cpu device listed in MediaTek platforms' devicetree.cb doesn't
actually do anything, except causing an error during device
initialization:

 CPU: 00 missing read_resources

Therefore, remove it from the devicetree.

BUG=b:224419346
TEST=emerge-corsola coreboot
TEST=Krabby booted up successfully
BRANCH=none

Change-Id: Ibf9f7cf65da6a0dd0a0e1f556d5772573ba3e930
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62805
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-21 20:40:18 +00:00
Felix Held
fc45b1b90b mb/amd/chausie: add APCB binaries if available
The APCB files that provide the firmware components running on the PSP
some mainboard-specific information like the DRAM interface
configuration. Those files aren't yet in the upstream 3rdparty/blobs
repository, so only add those files if they are present and print that
no APCB was added and the image won't boot if they aren't present.

TEST=Both cases behave as expected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-21 17:22:26 +00:00
Nikolai Vyssotski
9f85958b7e mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MB
To have enough space in the A/B RW sections, increase those sizes to 4
MByte and decrease the RO section size to 6 MByte to free up the space
needed for that.

Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-21 17:20:38 +00:00
Sean Rhodes
629f8c5da1 ec/starlabs/merlin: Don't store EC values on change
Since CB:62741, the EC values are backed up to the CMOS when entering
S3, S4 and S5. Consequently, they don't need to be stored when they're
changed.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If0ea392afae4a4d3c605cdea3c5896fbff606215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-21 16:57:54 +00:00
Sean Rhodes
fbb46c5438 ec/starlabs/merlin: Always store EC values
The EC values will be changed when entering S3, S4 or S5, so move
the function that stores the current settings outside of logic
that restricts it to S4 or S5. This means the state isn't lost
when entering S3.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia007a8ad9c08a309489e9f64f1ed311858bfcd10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-21 16:57:37 +00:00
Frank Wu
0c893d2624 mb/google/brya/var/banshee: Add WiFi SAR table
Add WiFi SAR table

BUG=b:225285426
TEST=emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
and checked SAR table can load by WiFi driver.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8fa833409bd69e080fda735c89015b9548252190
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-21 14:16:27 +00:00
John Zhao
b1dd019de2 soc/intel/common: Add IOE P2SB for TCSS
Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB
sideband access and exposes API for TCSS usage.

BUG=b:213574324
TEST=Build platforms coreboot images successfully.

Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-21 14:16:07 +00:00
=
32d53c9df0 mb/google/zork/var/dirinboz: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:211672259
BRANCH=firmware-zork-13434.B
TEST=ALC5682I-VS audio codec can work

Change-Id: Icd4321ec0a284e35511dd4b860a16506f54cf663
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-21 14:14:27 +00:00
=
e204daa3e2 mb/google/zork/var/gumboz: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:215292608
BRANCH=firmware-zork-13434.B
TEST=ALC5682I-VS audio codec can work

Change-Id: I0b0231a3ee9c0dad289ffd50607b3ae6201f56a0
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-21 14:13:56 +00:00
Robert Chen
977282f6ce mb/google/brya/vell: Move WWAN devices for vell
This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are
add to overridetree.cb where WWAN is present for vell.

BUG=none
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-21 14:13:39 +00:00
Sridhar Siricilla
d9beb7bc50 mb/google/brya: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig which
updates PMC settings in the IFD for Alder Lake A0 silicon.
As Alder Lake A0 is intermediate stepping, and the IFD is locked in the
production systems, so the Kconfig is deselected.

BUG=b:190588098
BRANCH=firmware-brya-14505.B
TEST=Build the coreboot for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I81fe7c792dd82d9d547d318ebda55ee4a0f3ac96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-21 14:09:38 +00:00
Rex-BC Chen
d6727ba972 mb/google/corsola: Revise power-on sequence of PS8640
Although the panel initializes fine and the fw recovery screen is
displayed without issues, the current power-on sequence of the
PS8640 violates the spec of the PS8640, which can be confirmed by
measuring it with an oscilloscope.

The sequence is:
- set VDD12 to be 1.2V
- set VDD33 to be 3.3V
- pull hign PD#
- pull down RST#
- delay 2ms
- pull high RST#
- delay more than 50ms (55ms for margin)
- pull down RST#
- delay more than 50ms (55ms for margin)
- pull high RST#

This flow will increase 110ms if firmware display is enabled in
krabby. For normal booting flow, the firmware will not be enabled,
so it will meet boot time requirements of Chrome OS. (Less than 1s.)

Datasheet name: PS8640_DS_V1.4_20200210.docx.
Chapter: 14.

BUG=b:222650141
TEST=show fw display normally in krabby.
TEST=result of waveform meets the spec.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-21 03:11:44 +00:00
Felix Held
5b51faaaea mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, PSPP will be reenabled.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-03-19 18:27:05 +00:00
Felix Held
b9ee6f351b mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, the PSPP policy will be switched to balanced again.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-19 18:26:56 +00:00
Subrata Banik
7c477a9d1a soc/intel/common/block/p2sb: Add helper function to enable BAR
This patch creates a new helper function to enable P2SB BAR.

`p2sb_dev_enable_bar()` takes the PCI P2SB device address (B/D/F)
and BAR address (combining high and low base addresses).

BUG=b:224325352
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-03-19 05:27:28 +00:00
Robert Chen
9b6e851e5b mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid
The touchscreen slave address for landrid is 0x10 same as lantis, so we use SSFC to switch touchscreen controller.

BUG=b:222976965
TEST=emerge-dedede coreboot

Change-Id: I23d3de5e45aa2876c1590a1e09679d652a3f2906
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-19 01:44:15 +00:00
Felix Held
e9172a14f9 mb/google/guybrush/port_descriptors: use enum values for link speed
Use GEN3 from enum dxio_link_speed_cap instead of the number 3.

TEST=Timeless build results in identical firmware image for guybrush

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-18 23:09:21 +00:00
Subrata Banik
2bf9599cf1 vendorcode/intel/edk2/edk2-stable202111: Use fixed size struct elements
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
Change request here:https://github.com/intel/FSP/issues/59

This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.

BUG=b:200113959
TEST=Verified on Meteor Lake platform, without any compilation error

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1f33db43f7932cf6d165d0c70a0e2922dad00a09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 18:41:42 +00:00
Felix Held
79993d8be7 mb/google/brya/nivviks/overridetree: update tcss_aux_ori register name
Commit 215a97ee1c (soc/intel/adl/chip.h:
Convert all camel case variables to snake case) converted the camel case
used in the parameter name to snake case, but
commit bd529e2e20 (mb/google/nissa/var/
nivviks: Add TcssAuxori for nivviks) still used the old names which
breaks the upstream build. his patch is intended to be merged via
fast-path before the 24h are over to fix the tree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b9049553889c77bd8c59a2c4564d36d836a4eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62927
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 17:55:56 +00:00
Rex-BC Chen
bff1210f24 soc/mediatek/mt8186: Disable unused spm_thermal
In MT8186, we need to disable spm_thermal to prevent it from
influencing other wdt status.

There are two hardware pathes which are used for asserting watchdog
from thermal. We can disable status of path 1 because status of
path 2 is used.
1. Thermal -> SPM -> WDT
2. Thermal -> WDT

Spm_thermal (path 1) is a flexible option for software control, and
the hardware designer suggests that we should disable it if we don't
use it.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0ffde6bad3000a64e3b5782edaa72c62da034302
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62890
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:43:45 +00:00
Rex-BC Chen
1e24b20475 soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0
Because we close external signal in kernel driver since MT8195, it's
more reasonable to trigger sw reset with exteranl signal again
whenever the wdt status is not equal to 0.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62797
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:42:40 +00:00
Usha P
bd529e2e20 mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks
Enable SBU orientation handling by SoC for both USBC port0 and USBC
port1. Nivviks USBC port0 do not have retimer, USBC port1 has redriver,
but that do not flip the data lines. Hence we need to set bits for both
the USBC ports.

BRANCH:None
TEST=emerge-nissa coreboot chromeos-bootimage. Flash the image on
nivviks board and verified USBC display is working on both the ports in
normal and inverted connections.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62731
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:42:12 +00:00
Yu-Ping Wu
39e6f85ea2 soc/mediatek: Set soc_ops.set_resources as no-op
Without setting the set_resources field for soc_ops, we will get an
error during device initialization:

 [ERROR]  CPU_CLUSTER: 0 missing set_resources

Because the set_resources field is considered mandatory, explicitly set
it as no-op noop_set_resources.

BUG=b:224419346
TEST=emerge-corsola coreboot
TEST=Did not see the error on krabby
BRANCH=none

Change-Id: Ic82b86f0482a9de09e942c1674be5f0ac615851f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-18 15:41:37 +00:00
Frank Wu
12cc10fe8b mb/google/brya/var/banshee: Replace amp max98357 with max98360
Based on the latest schematic, replace amp max98357 with max98360.

BUG=b:224692387, b:216110896
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62887
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:41:00 +00:00
Frank Chu
d402fdff5d mb/google/dedede/var/galtic: update Wifi SAR for for galnat
Add wifi sar for galnat/galnat360
Use SKU ID to load wifi table.

Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
galnat (sku id:0x140000)*
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
galnat360 (sku id:0x2B0000)*

BUG=b:222008376
TEST=emerge-dedede coreboot chromeos-bootimage \
     coreboot-private-files-baseboard-dedede
     verify the SAR table is correct in each project

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I868a7416a002732736cabea48ce80548ea75e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-18 15:40:44 +00:00
Xi Chen
0ca7aab760 commonlib/bsd: Add struct name "mem_chip_channel" for external access
struct mem_chip_info {
  ...
  struct { --> If no struct name, can't access the channel structure
    ...
  } channel[0];
};

BUG=b:182963902,b:177917361
TEST=Build pass on Kingler

Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I8dcd3b52f33f80afb7885ffdcad826d86b54b543
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-18 15:40:26 +00:00
Ren Kuo
8df9cbb6ab mb/google/brya/var/volmar: Disable thunderbolt
Volmar does not support Thunderbolt, therefore disable all of the TBT
devices in the devicetree. The volmar fit image had been disabled already, cf. chrome-internal:4459289.

BUG=b:2233193
TEST=Build and run on DUT.

Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 15:40:01 +00:00
Dtrain Hsu
b24e45d215 mb/google/brya/var/kinox: Reconfigure GPIO settings
Configure GPIOs according to updated schematics.
- GPP_A21 from NC to TCP_DP1_CTRLCLK.
- GPP_A22 from NC to TCP_DP1_CTRLDATA.
- GPP_E22 from DDIA_DP_CTRLCLK to NC.
- GPP_E23 from DDIA_DP_CTRLDATA to NC.

BUG=b:214025396
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 15:39:47 +00:00
Cliff Huang
2b19d547c0 mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants
This sets EPP value to be 45% for all Adl RVP variants.

Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.

TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-03-18 15:39:33 +00:00
Shon Wang
8d296b1eba mb/google/brya/var/vell: Change AMP driver setting
1.Change I2S GPP_Sx (S0-S3) Native PAD Configuration from NF2 to NF4
2.Select CS35l53 AMP driver for Vell variant.

Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c
Signed-off-by: Shon.Wang <shon.wang@quanta.corp-partner.google.com>
Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 15:39:08 +00:00
Stefan Binding
7cd505873b drivers/i2c/cs35l53: Add driver for generating device in SSDT
This patch is adding support for Cirrus Logic CS35l41/CS35l53
smart amplifier. This part is now used in number of new chromebook's
HW designs by several vendors.

This driver uses the ACPI Device Property interface to generate
the required parameters into the _DSD table format expected by
the kernel. For detailed information about these properties, please
check Linux kernel documentation:
/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml

Change-Id: I2cbb1cef89f8d56ee73fab06c68933a2ab8c3606
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 15:38:21 +00:00
Karthikeyan Ramasubramanian
92dc7d2b4f mb/google/skyrim: Build APCB sources into amdfw when present
BUG=b:224618411
TEST=util/abuild/abuild -t GOOGLE_SKYRIM with and without APCB

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-18 15:14:44 +00:00
Raul E Rangel
4fdcefc9f6 mb/google/skyrim: Fix I2C voltages
Needed so i2c communication works.

BUG=b:224618411
TEST=build skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8ec7c18cae509b5683cb73153fd6d3747cf9d753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62874
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:10:48 +00:00
Raul E Rangel
7496392bd9 mb/google/skyrim: Enable tis_plat_irq_status
This will fix:
> [INFO ]  Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50!

BUG=b:224618411
TEST=Compile skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5add694506ad089adcc8961f101bf507bc39a522
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62873
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18 15:10:39 +00:00
Nick Vaccaro
1abbb96c36 Revert "Revert "drivers/intel/fsp2_0: Allow mp_startup_all_cpus() to run serially""
This reverts a change that was causing hangs and exceptions during boot
on an ADL brya4es.

The hang (or APIC exception) occurs at what appears to be the FSP MP
initialization sequence, prior to the "Display FSP Version Info HOB"
log being displayed :

  [DEBUG]  Detected 10 core, 12 thread CPU.
  [DEBUG]  Display FSP Version Info HOB

This reverts commit 40ca79714a.

BUG=b:224873032
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and verify brya4es
is able to successfully reboot 200 times without any issues.

Change-Id: I88c15a51c5d27fbd243478c923e75962d3f8d67d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-18 07:24:04 +00:00
Wisley Chen
96669864bd soc/intel/common/block/cse: Change loglevel prefix to WARNING
This message is not really an error message, so BIOS_ERR is
inappropriate. The message does seem more like a warning though,
that the developer could have multiple Kconfigs selected to send EOP,
therefore switch to BIOS_WARN instead.

BRANCH=firmware-brya-14505.B
TEST=build

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I57a34334007a6a7443302c2f25de3d5c87c85573
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-18 04:56:35 +00:00
MAULIK V VAGHELA
5008d34003 soc/intel/adl: Remove IOM Mctp command from TCSS ASL
TCSS ASL code was carried forward from TGL and it used to follow the same
sequence.

Recently as part of s0ix hang issue, it was found that sending IOM
MCTP command as part of TCSS D3 Cold enter-exit sequence created an
issue.

We discovered that due to change in hardware sequence, ADL should not
set/reset IOM MCTP during D3 cold entry or exit. This patch removes the
bit setting from ASL file to prevent hang in the system.

This patch also removes obsolete Pcode mailbox communication which is
no longer required for ADL.

BUG=b:220796339
BRANCH=firmware-brya-14505.B
TEST=Check if hang issue is resolved with the CL and no other regression
observed

Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62861
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17 19:45:11 +00:00
Jon Murphy
fcccff35f0 soc/amd/cezanne: Add counter initializers
Some counters are not being initialized and are relying on mainboards to
set their values.  If the mainboards have not implemented these
functions it leads to indeterminate behavior.

BUG=b:224987813
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-17 17:39:25 +00:00
Jon Murphy
cd93e8e67f soc/amd/picasso: Add counter initializers
Some counters are not being initialized and are relying on mainboards to
set their values.  If the mainboards have not implemented these
functions it leads to indeterminate behavior.

BUG=b:224987813
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-17 17:39:08 +00:00
Jon Murphy
2e1d16828a soc/amd/sabrina: Add counter initializers
Some counters are not being initialized and are relying on mainboards to
set their values.  If the mainboards have not implemented these
functions it leads to indeterminate behavior.

BUG=b:224987813
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-17 17:38:54 +00:00
Eric Lai
af92d07503 mb/google/brya: Remove mainboard.asl
Use C code to generate MS0X entry and provide variant hook.

BUG=b:207144468
TEST=check SSDT table has the same entry.
    Scope (\_SB)
    {
        Method (MS0X, 1, Serialized)
        {
            If ((Arg0 == One))
            {
                \_SB.PCI0.CTXS (0x148)
            }
            Else
            {
                \_SB.PCI0.STXS (0x148)
            }
        }
    }

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 16:00:38 +00:00
Cliff Huang
2754787110 mb/google/brya: Remove Pcie Generic driver for WWAN
This was to merge PCIe ACPI code to WWAN device. But, now use recent
_DSD generation changes in FM driver instead. PCie generic driver is
not used for WWAN at this time.

Also, RTD3 devices are moved to overridetree.cb where WWAN is
present.

BUG=b:221250331
BRANCH=firmware-brya-14505.B
TEST=
Check that _DSD is added to WWAN device in SSDT for the variants.
Check that RTD3 is added to WWAN device in SSDT for the variants.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 15:55:12 +00:00
Frank Wu
97f4db72c4 mb/google/brya/var/banshee: Update DPTF parameters
Follow thermal team design to update thermal table.

BUG=b:223492897
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-17 15:54:19 +00:00
Frank Chu
1ab50fd5d5 mb/google/dedede/var/galtic: Add fw_config probe for 2nd touchscreen
For galnat platform, support 2nd ELAN touchscreen via SSFC.
Define FW_CONFIG bits 39 - 40 (SSFC bits 7-8)
for touchscreen controller switch.

BUG=b:221002826
TEST=touch screen is functional.

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id3501205b147c9dc3c96ce8381a3e7492ae8258e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-17 15:01:00 +00:00
Tim Wawrzynczak
5e6fd360de drivers/wifi/generic: Fix properties in generic-under-PCI device case
In the devicetree case where a generic device underneath the Intel PCI
CNVi device carries the device properties, the incorrect device was
passed to wifi_ssdt_write_properties.

Also while here, update the UUID for `DmaProperty` to match what
Microsoft defined here:
https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports

BUG=b:215424986, b:220639445
TEST=dump SSDT and see that _PRW for CNVi device is no longer garbage,
but contains the value from the devicetree (GPE0_PME_B0).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2022-03-17 14:54:28 +00:00
Wisley Chen
dc27d807ba driver/intel/usb4/retimer: Change loglevel prefix
In usb4_retimer_fill_ssdt(), it search all dpf ports and shows message
in not support dpf ports.
It's not error and changes the loglevel prefix to BIOS_INFO.

BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I508ec7662e078893f944edb3d68364c57d5c5a73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 14:44:10 +00:00
Wisley Chen
9006d8b746 soc/intel/alderlake/retimer: Change loglevel prefix
This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to
BIOS_INFO instead.

BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Change-Id: I9dc852a0cd30f95506c205f161a05e8a8c44fcd5
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 14:43:30 +00:00
Wisley Chen
de7cac82d6 ec/google/chromeec: Change loglevel prefix
In most boards, it doesn't write OEM_NAME in CBI to override the
manufacturer name in the SMBIOS table. It' better use the "BIOS_INFO" than "BIOS_ERR"

BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Change-Id: I52eb1e6926eaac30b1dbee13ab750ef15b466d89
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 14:43:04 +00:00
Dtrain Hsu
29571e80b3 mb/google/brya/var/kinox: Modify 15W SOC power control setting
Modify 15W SOC default power settings for kinox.
- PL2 39W
- PL4 100W
- Psys_PL2 65W
- Psys_imax_ma 5000ma
- bj_volts_mv 20000mv

BUG=b:213417026, b:222599762
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62627
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17 14:42:24 +00:00
Subrata Banik
2f1f5ecf8a soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC
This patch refactors the current P2SB common code driver to accommodate
the future SoC platform with provision of more than one P2SB IP in
disaggregated die architecture.

IA SoC has only one P2SB in PCH die between SKL to ADL. Starting with
MTL, one more P2SB IP resides in IOE die along with SoC die. (PCH die is
renamed as SoC in MTL.)

P2SB library (p2sblib.c) is common between PCH/SoC and IOE, and p2sb.c
is added only for PCH/SoC P2SB.

BUG=b:224325352
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-17 14:37:43 +00:00
Raihow Shi
9e4a38795c mb/google/brask/variants/moli: set eMMC pin in bootblock
1.Assert eMMC enable pin in bootblock
2.Deassert eMMC reset pin in bootblock

BUG=b:220821454

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 14:36:46 +00:00
Taniya Das
5fa28a5404 qualcomm/sc7280: Add mdp clock support to turbo in coreboot
This change supports the configuration and enablement of
mdp clock to vote for turbo and supports different display
panel resolutions and framerates.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ibf4f11d02b0edf83461dbb7af99fda5f33cd5b71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62371
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17 14:36:24 +00:00
Taniya Das
af2c89c463 qualcomm/sc7280: Add display external clock support in coreboot
Add support for EDP (Embedded DisplayPort) clocks in coreboot.
This change supports the configuration and enablement of
EDP PIXEL, LINK, LINK_INTF and AUX clocks.

BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59611
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17 14:36:07 +00:00
Eric Lai
e93bce937e mb/google/nissa/var/nivviks: Set gpio override to board_0
Follow the latest schematic change, gpio will match the baseboard.
Return the current table as override.

BUG=b:223677877
TEST=audio is functional on board_0.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I91dc2c9c8811d403c60a4b4f3a7c5ed8de4e527e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-17 14:35:48 +00:00
Matt DeVillier
23be41880c ec/chromeec/ec_smbios: Set system manufacturer for ChromeOS devices
Currently, many Linux drivers use DMI quirks to identify ChromeOS
devices and handle them accordingly: namely they look for the SMBIOS
system manufactuer to be "GOOGLE" or "Google", and the bios-vendor to be
coreboot. Historically this was consistently the case, but recent model
ChromeOS devices allow the OEM to set the mainboard manufacturer, which
is also the default system manufacturer. This breaks many DMI quirks,
notably ones used by SOF (sound open firmware) for audio.

To fix this, set the system manufactuer for ChromeOS devices to "Google"
for devices selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID, leaving the OEM
customization in place for the mainboard manufacturer. Since boards
selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID are the only ones overriding
the default mainboard manufacturer, they are the only ones which need
this correction.

Test: build/boot google/bloog with Linux 5.16, verify SOF drivers
correctly detect device as a Chromebook and load the appropriate
audio firmware.

Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62796
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17 14:35:33 +00:00
Curtis Chen
3fc3e6c609 soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax values
Add ADL-P MCH ID 4, 8, 9, 10 into this list.

BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=Build and check fsp log to confirm the settings are set properly.

Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 14:30:13 +00:00
Subrata Banik
73ad818bc9 soc/intel/common/block/cpu: Enable ROM caching in ramstage
Cache the BIOS region and extended BIOS region if the boot device is
memory mapped, which is mostly the case with Intel SoC platform.
Having the ROM region cached helped to improve the pre-boot time.

TEST=Able to boot redrix to Chrome OS without seeing any sluggishness.
Additionally verified on EHL board (from siemens), shows significant
savings in payload loading time as below:

Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:

upstream:
  90:starting to load payload                    1,072,459 (1,802)
 958:calling FspNotify(ReadyToBoot)              12,818,079 (11,745,619)

with this patch:
  90:starting to load payload                    1,072,663 (2,627)
 958:calling FspNotify(ReadyToBoot)              5,299,535 (4,226,871)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-17 06:02:04 +00:00
Subrata Banik
1f28c853de soc/intel/common/fast_spi: support caching ext_bios in ramstage
This patch provides a way to cache `ext_bios` region for all stages to
save boot time.

TEST=Able to see the ext_bios region in MTRR snapshot when cached on
the Brya variants.

Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:

upstream:
  90:starting to load payload                    1,072,459 (1,802)
 958:calling FspNotify(ReadyToBoot)              12,818,079 (11,745,619)

with this patch:
  90:starting to load payload                    1,072,663 (2,627)
 958:calling FspNotify(ReadyToBoot)              5,299,535 (4,226,871)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-17 06:01:49 +00:00
Subrata Banik
242e2665d0 include/efi: Clean up efi_datatype.h file
This patch cleans up `efi_datatype.h` to allow other SoC and/or driver
code to use this file.

`PiPei.h` file only gets added from UDK2017 hence, the platform with the
older EDK2 base (prior to UDK2017) is unable to resolve this file
dependency.

This CL removed the `PiPei.h` header and only added the required header
file `PiPeiCis.h` for platforms with UDK base >= 2017.

BUG=b:200113959
TEST=Able to build Brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9177814fcf41e5950ace94050356f0273f765c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 06:00:54 +00:00
Eric Lai
6e3d42ab42 drivers/wifi/generic: Fix is_cnvi function
dev->ops = &wifi_cnvi_ops need is_cnvi be true. This cause the exclusive
statement so is_cnvi never be true in !DEVTREE_EARLY.

BUG=b:224317408
TEST=no assertion in coreboot.
[EMERG]  ASSERTION ERROR: file 'src/acpi/acpigen_pci.c', line 24

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I1ca6312ce164c43021686b483f6579164614cede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-17 04:57:43 +00:00
Ravi Kumar Bokka
4573ca42e6 soc/qualcomm/common: Add dram information to CBMEM table
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-03-16 23:08:05 +00:00
Felix Singer
944291d458 mb/hp/snb_ivb_laptops: Move selects from Kconfig.name to Kconfig
Move selects from Kconfig.name to Kconfig so that the configuration is
in one place and not distributed over two files.

Change-Id: I500f6422c1f8975de8b0bcc8b95cba2bcd4ebe27
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16 18:27:28 +00:00
Dtrain Hsu
335edc0f5d mb/google/brya/var/kinox: Enable PCIe-eMMC bridge
Enable PCIe-eMMC bridge for Kinox.

BUG=b:218786363, b:211176722
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:57:26 +00:00
Dtrain Hsu
60260a5ed6 mb/google/brya/var/kinox: Modify the DPTF/Fan parameters
Follow the Thermal_paramters_list-0314.xlsx to modify DPTF/Fan parameters.

BUG=b:221180425, b:222020226, b:221182596
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:57:06 +00:00
Sridhar Siricilla
073da0cbae soc/intel/common: Retry MEI CSE DISABLE command
As per ME BWG, the patch retries MEI CSE DISABLE command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.

TEST=build and boot the Brya board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:56:50 +00:00
Sridhar Siricilla
92bd71ff74 soc/intel/common: Retry END_OF_POST command
As per ME BWG, the patch retries END_OF_POST command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.

BUG=b:200251277
TEST=Verify EOP retry mechanism for brya board.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:56:34 +00:00
Jianjun Wang
5111326c5c soc/mediatek: PCI: Remove global variable
Remove global variable and use 'pcidev_path_on_root()' to get the base
address of PCIe controller.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-16 16:55:52 +00:00
Jianjun Wang
c0808b6497 soc/mediatek: Add chip config for setting PCIe config
Add chip config for setting PCIe config.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-16 16:55:26 +00:00
Raul E Rangel
d59b3dd085 soc/amd/common/block: Add mainboard_handle_smi
The current SMM framework only allows the mainboard code to handle GPEs.
i.e., Events 0 - 23. This change allows the mainboard code to handle any
SMI events not handled by the SoC code. This will allow the mainboard
code to handle `SMITYPE_ESPI_SMI`.

BUG=b:222694093
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I81943e8cb31e998f29cc60b565d3ca0a8dfe9cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-16 16:33:32 +00:00
Felix Singer
589609c8e7 mb/hp/snb_ivb_laptops: Rename BOARD_HP_SNB_IVB_LAPTOPS
Rename `BOARD_HP_SNB_IVB_LAPTOPS` to `BOARD_HP_SNB_IVB_LAPTOPS_COMMON`
to indicate and to make it clear that this option serves as base for
others.

Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and also with
`INCLUDE_CONFIG_FILE` disabled. coreboot.rom remains identical.

Change-Id: Icadeb8a33ae0787d2cd5da460065a2ed15256d64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16 15:55:18 +00:00
Felix Singer
339ca7f11a mb/hp/snb_ivb_laptops/Kconfig{,.name}: Reorder selects alphabetically
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and
coreboot.rom remains identical.

Change-Id: I54367c7c663ad288ccdcbd4e7289546489a68f30
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16 15:54:35 +00:00
Mark Hsieh
f25e42c4f4 mb/google/brya: set GPP_D0 to GPO
Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is
directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP
firmware successfully.

BUG=b:222188263, b:223906569
TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint
Firmware Test.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-16 04:10:59 +00:00
Ravi Kumar Bokka
42fcb2a8f4 libpayload: Parse DDR Information using coreboot tables
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59193
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-16 01:21:44 +00:00
Jes Klinke
19baa9d51e i2c: Add configurable I2C transfer timeout
This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US,
which controls how long to wait for an I2C devices to
produce/accept all the data bytes in a single transfer.
(The device can delay transfer by stretching the clock of
the ack bit.)

The default value of this new setting is 500ms.  Existing
code had timeouts anywhere from tens of milliseconds to a
full second beween various drivers.  Drivers can still have
their own shorter timeouts for setup/communication with the
I2C host controller (as opposed to transactions with I2C
devices on the bus.)

In general, the timeout is not meant to be reached except in
situations where there is already serious problem with the
boot, and serves to make sure that some useful diagnostic
output is produced on the console.

Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-15 22:06:27 +00:00
Michael Niewöhner
d3b85223fd soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.

Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15 19:22:19 +00:00
Sean Rhodes
bba7e601a8 intel/common/block: Add APL and GLK PCI IDs for HDA
Add PCI ID's for APL/GLK so they can use HDA.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-15 19:21:46 +00:00
Kevin Chiu
29919f81fa mb/google/guybrush/var/nipperkin: update APU STT setting
BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     update the thermal setting value by measurement and
     pass the thermal performance test

Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-15 19:19:36 +00:00
Frank Wu
bd0ba39172 mb/google/brya/var/banshee: Add camera privacy setting
Using the GPP_F19 as privacy switch for camera in banshee.

BUG=b:223712143, b:216110896
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-15 19:19:21 +00:00
Werner Zeh
9b565de3a0 lib/spd: Do not print part number if it is not available
If the DRAM part number is not available in the SPD data (meaning filled
with 0x00) do not print it in the log.

Change-Id: If7224c6e114731b1c03915a2bde80f57369d0cee
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-15 19:18:54 +00:00
Rex-BC Chen
69e3cab7f9 soc/mediatek/mt8186: change pmic hwcid from warning to info
The pmic hwcid dumping should not be a warning, so we modify it to info.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15 19:17:48 +00:00
Rex-BC Chen
129b8ae551 soc/mediatek/common: Add halt() after triggering wdt reset
It's more reasonable to halt when we trigger watchdog reset because
the whole system should be reset afterwards.

BUG=b:222217317
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15 19:17:12 +00:00
MAULIK V VAGHELA
a4cdb5b381 mb/google/brya: Disable C1-state auto demotion for Brya & Brask
C1-state auto demotion feature allows hardware to determine C1-state as
per platform policy. Since Brya sets performance policy to balanced from
hardware, auto demotion can be disabled without performance impact.

Also, disabling this feature results in 110 mW power savings during
video playback.

Note that C1state Autodemotion feature is not applicable for ADL-P SoC.
Hence recommendation is to keep it disabled.

BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Code compiles and correct value of c1-state auto demotion is passed
to FSP. Also power and performance impact has been measure by respective
teams.

Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-03-15 18:11:37 +00:00
MAULIK V VAGHELA
99356386a6 soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion
FSP has a parameter to enable/disable c1-state autodemotion feature.
Boards/Baseboard can choose to use this feature as per requirement.

This patch hooks up this parameter to devicetree

BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Check code compiles and correct value has been passed to FSP.

Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15 18:11:16 +00:00
MAULIK V VAGHELA
215a97ee1c soc/intel/adl/chip.h: Convert all camel case variables to snake case
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.

By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.

During renaming process, this patch also removes unused variables
listed below:
-> SataEnable   // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used

Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.

BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.

Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15 18:10:41 +00:00
Subrata Banik
4703edc943 {mb, soc}: Move mrc_cache invalidating logic into memory common code
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced
per mainboard logic to invalidate the mrc_cache.

This patch moves mrc_cache invalidating logic into IA common code and
cleans up the code to remove unused argument `dimms_changed` from SoC
and mainboard directory.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:18:28 +00:00
Subrata Banik
47b836af96 soc/intel/common: Pass FSPM_UPD * argument for spd functions
This patch adds `FSPM_UPD *` as argument for
mem_populate_channel_data() and read_spd_dimm().

This change will help to update the architectural FSP-M UPDs in
read_spd_dimm().

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I770cfd05194c33e11f98f95c5b93157b0ead70c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:17:38 +00:00
Subrata Banik
2eb51aace5 {mb, soc}: Change memcfg_init() and variant_memory_init() prototype
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.

This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:17:25 +00:00
Shelley Chen
5730d018d1 mb/google/herobrine: consolidate hoglin/herobrine QUP inits
Hoglin and Herobrine (proto1) should share majority of GPIOs.
Conslidating the QUP initializations in mainboard.  Also, putting
fingerprint init in a conditional as not all devices will have an FP
sensor.

BUG=b:182963902,b:223826899
BRANCH=None
TEST=booted BIOS on hoglin and check for i2c errors in dmesg

Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14 22:28:56 +00:00
Mars Chen
d99e773460 mb/google/trogdor: Add variant Gelarshie
New board introduced to trogdor family.

BUG=b:223101874
BRANCH=none
TEST=make

Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com>
Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14 22:04:26 +00:00
Casper Chang
f7abb4fccf mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
Currently the BayHub eMMC enable pin is using the default
configuration from the baseboard, which leads to RTD3 not being able
to control the GPIO when exiting and entering suspend. To fix this,
program the GPIO in the ramstage GPIO table.

BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
     scope enable pin while performing suspend stress and enable pin
     works as expected.
     test suspend stress 1000 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 16:18:52 +00:00
Sean Rhodes
13f49ce754 mb/starlabs/labtop: Pull SSD Pin to low when entering S3
Pull GPP_D16 to low when suspending, otherwise it will remain active
and use power.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2cbe7caf66e8d8c27414aca3b74416c2b8115ea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-14 15:57:16 +00:00
Werner Zeh
06fe5d565d mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
DDR4 SPD data needs to be 512 byte to comply with the spec.

Though there is no vital timing data used beyond 256 byte there are some
part information which will be used to show the part info in the
coreboot log. If the buffer is too small this log shows garbage.

This patch increases the SPD buffer size from 256 byte to 512 to avoid
side effects.

Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-14 15:53:54 +00:00
Sridhar Siricilla
282c2a6472 soc/intel/common: Use generic enum type values
The patch uses generic enum type values for EOP command handler. So,
it renames cse_eop_result enum type to cse_cmd_result and also renames
the enum values to have generic name.

TEST=Build the code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie0efa8fff08318ed863010db289959d113f4767e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:51:45 +00:00
Sridhar Siricilla
1506b77b60 soc/intel/common: Use heci_reset() in the CSE TX and RX flows
The patch implements error handling as per the ME BWG guide. The BWG
recommends HECI interface reset if there is a timeout or malformed
response is received from the CSE. Also, the patch triggers HECI
interface reset if the CSE link state is not ready in the heci_send()
API.

TEST=Verify HECI Interface reset in the simulated error scenarios.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:51:29 +00:00
Sridhar Siricilla
6836da2e5a soc/intel/common: Implement error codes for for heci_send_receive()
The patch implements below changes:
1. Implements different error codes and use them in appropriate
 failure scenarios of below functions:
  a. heci_send()
  b. recv_one_message()
  c. heci_receive()

2. As heci_send_receive() is updated to return appropriate error codes
 in different error scenarios of sending and receiving the HECI
 commands. As the function is updated to return 0 when success, and
 non-zero values in the failure scenarios, so all caller function have
 been updated.

BUG=b:220652101
TEST=Verified CSE RX and TX APIs return error codes appropriately in
the simulated error scenarios.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:51:12 +00:00
Dtrain Hsu
4b8079152a mb/google/brya/var/kinox: update overridetree
1. Update override devicetree based on schematics.
2. ALC5682I-VS is for audio codec.

BUG=b:218786363, b:214025396, b:212183045
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:49:43 +00:00
Raul E Rangel
b52b7010ef mb/google/guybrush: Fix building with VBOOT_STARTS_IN_BOOTBLOCK
The verstage.c file contains PSP verstage specific code. We don't need
it when using x86 verstage.

BUG=b:193050286
TEST=Build and boot guybrush with x86 verstage

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:48:57 +00:00
Cliff Huang
938f33e9f7 mb/google/brya: Set EPP to 45% for all Brya variants
This sets EPP value to be 45% for all Brya variants.

Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.

BUG=b:219785001
BRANCH=firmware-brya-14505.B
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:48:29 +00:00
Cliff Huang
0bb2225718 soc/intel/alderlake: Add EPP override support
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.

BUG=b:219785001
BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:48:11 +00:00
Teddy Shih
ca9658bdb2 mb/google/dedede: Update DPTF setting
Update PL1, PL2, and temperature sensor values from thermal team,
as well as, we remove unused temperature sensors according to
baseboard/devicetree.cb and mainboard schematic. After we check
DTT setting, the thermal and performance test pass.

BRANCH=dedede
BUG=b:204229229
TEST=on beadrix, run following commands:
localhost /tmp # cat /sys/class/thermal/thermal_zone*/type
x86_pkg_temp
INT3400 Thermal
TSR0
TSR1
TCPU
localhost /tmp # cat /sys/class/thermal/thermal_zone*/temp
45000
20000
32800
32800
39000

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62729
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:47:50 +00:00
Felix Held
ae7ec18d3d mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2
The one USB2 port on the XHCI2 controller should have the port ID 2.0,
since it's the first USB2 port on that XHCI controller.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a370132960939bccec4eb69a6590d0880b04137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:47:21 +00:00
Felix Held
b0d555733a mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
GFX HDA is the audio controller that provides audio output via the
external display connection, ACP is the audio coporcessor for the on-
board audio codec and XHCI2 is the third XHCI controller that provides
one USB 2.0 port. All those devices are used, so enable them in the
board's devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:47:07 +00:00
Eric Lai
e6f71a5d28 mb/google/nissa/var/nivviks: Hook up SD host controller GL9750
Select GL9750 driver and add power sequence according to datasheet:
GL9750S-OIY04 rev1.22.

BUG=b:223304292
TEST=check GL9750 can get enumerated by kernel 5.15.
01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01)

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-14 15:46:49 +00:00
Eric Lai
232dcb938a mb/google/nissa/var/nivviks: Enable pen garage
Enable pen garage. Pen detect is active low. And wake system when
eject.

BUG=b:223476974
TEST=evtest work as expected.
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
  Event type 0 (EV_SYN)
  Event type 5 (EV_SW)
    Event code 15 (SW_PEN_INSERTED) state 0
Properties:
Testing ... (interrupt to exit)
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-14 15:46:24 +00:00
Cliff Huang
5069f6c3c8 drivers/pcie/generic: Add support to generate code under companion device instead
Only one ACPI device should be added to a PCIe root port. For the root
ports which already have device created, the generated code from this
driver needs to be merged with the existing device.

By default, this driver will create new device named DEV0.
This change allows to generate code under an existing device.

ex: (generate code under PXSX):
    Scope (\_SB.PCI0.RP01.PXSX)
    {
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
            Package (0x01)
            {
                Package (0x02)
                {
                    "UntrustedDevice",
                    One
                }
            }
        })
    }

BUG=b:221250331
BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10 23:57:16 +00:00
Bora Guvendik
860672e987 soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table after normalizing to the zero-point value. Although
consumer CSE sku also supports this feature, it was validated on
CSE Lite sku only.

BUG=b:182575295
TEST=Able to see TS elapse prior to IA reset on Brya/Redrix

990:CSME ROM started execution                        0
944:CSE sent 'Boot Stall Done' to PMC                 88,000
945:CSE started to handle ICC configuration           88,000 (0)
946:CSE sent 'Host BIOS Prep Done' to PMC             90,000 (2,000)
947:CSE received 'CPU Reset Done Ack sent' from PMC   282,000 (192,000)
  0:1st timestamp                                     330,857 (48,857)
 11:start of bootblock                                341,811 (10,953)
 12:end of bootblock                                  349,299 (7,487)

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10 23:23:13 +00:00
Jon Murphy
9df0085193 mb/google/skyrim: Configure WLAN
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN.  Mappping derived from Skyrim schematic.

BUG=b:214412172
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 23:22:33 +00:00
Jon Murphy
d42d8ea0a2 mb/google/skyrim:Update GPIO 32
GPIO 32 was not allocated correctly, updating to reflect the native
function use of the pin

BUG=b:214412172
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 23:21:49 +00:00
Ravi Kumar Bokka
9b2914fe62 mb/google/herobrine: Add trackpad initialization
Initialize trackpad on Qualcomm reference boards

BUG=b:182963902,b:223826899
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I93e866d92cf37887a98de88b4b2d768562515670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62226
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 18:19:59 +00:00
Raul E Rangel
f63dd17bb1 mb/google/guybrush: Enable DEBUG_SMI for non-serial firmware
In order to copy the PSP verstage logs into x86 cbmem, we need to enable
DEBUG_SMI. This will include the CBMEM console code in SMM. I only
enable DEBUG_SMI when UART is disabled because SMM doesn't currently
save/restore the UART registers. This will result in clearing the
interrupt enable bits and makes it so you can no longer use the TTY.

BUG=b:221231786, b:217968734
BRANCH=guybrush
TEST=Build serial and non serial firmware and verify DEBUG_SMI is set
correctly.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 17:24:06 +00:00
Raul E Rangel
54786fece8 soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
Now that SMM can write to CBMEM we can simply replay the transfer buffer
cbmem console to move it into the main cbmem console.

replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols.
Since the SMM rmodule get linked with a different linker script than
bootblock/romstage it doesn't have access to these symbols. In order to
pass these symbols into SMM, we parse the bootblock.map file and
generate an early_ram.ld script. This script is then used when linking
SMM.

I replay the buffer in `smm_soc_early_init` because this call happens
before `console_init()`. `console_init()` prints the SMM header and we
want to append the verstage contents before printing the header to avoid
confusion.

BUG=b:221231786
TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when
doing `cbmem -c`.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 17:23:35 +00:00
Raul E Rangel
e6cd6caf31 cpu/x86/smm: Add weak SoC init and exit methods
This change provides hooks for the SoC so it can perform any
initialization and cleanup in the SMM handler.

For example, if we have a UART enabled firmware with DEBUG_SMI, the UART
controller could have been powered off by the OS. In this case we need
to power on the UART when entering SMM, and then power it off before we
exit. If the OS had the UART enabled when entering SMM, we should
snapshot the UART register state, and restore it on exit. Otherwise we
risk clearing some interrupt enable bits.

BUG=b:221231786, b:217968734
TEST=Build test guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I946619cd62a974a98c575a92943b43ea639fc329
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 17:06:51 +00:00
Kevin Chiu
496734379d mb/google/guybrush/var/nipperkin: turn off WWAN DPR
Sets GPIO 42 to high to turn off WWAN DPR

BUG=b:216735313
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     make sure GPIO42 is high

Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-10 15:18:55 +00:00