Commit Graph

39508 Commits

Author SHA1 Message Date
Dtrain Hsu 60260a5ed6 mb/google/brya/var/kinox: Modify the DPTF/Fan parameters
Follow the Thermal_paramters_list-0314.xlsx to modify DPTF/Fan parameters.

BUG=b:221180425, b:222020226, b:221182596
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I5f44120430029130d38b89d0eab6bbf205aca929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:57:06 +00:00
Sridhar Siricilla 073da0cbae soc/intel/common: Retry MEI CSE DISABLE command
As per ME BWG, the patch retries MEI CSE DISABLE command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.

TEST=build and boot the Brya board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:56:50 +00:00
Sridhar Siricilla 92bd71ff74 soc/intel/common: Retry END_OF_POST command
As per ME BWG, the patch retries END_OF_POST command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.

BUG=b:200251277
TEST=Verify EOP retry mechanism for brya board.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-16 16:56:34 +00:00
Jianjun Wang 5111326c5c soc/mediatek: PCI: Remove global variable
Remove global variable and use 'pcidev_path_on_root()' to get the base
address of PCIe controller.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-16 16:55:52 +00:00
Jianjun Wang c0808b6497 soc/mediatek: Add chip config for setting PCIe config
Add chip config for setting PCIe config.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-16 16:55:26 +00:00
Raul E Rangel d59b3dd085 soc/amd/common/block: Add mainboard_handle_smi
The current SMM framework only allows the mainboard code to handle GPEs.
i.e., Events 0 - 23. This change allows the mainboard code to handle any
SMI events not handled by the SoC code. This will allow the mainboard
code to handle `SMITYPE_ESPI_SMI`.

BUG=b:222694093
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I81943e8cb31e998f29cc60b565d3ca0a8dfe9cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-16 16:33:32 +00:00
Felix Singer 589609c8e7 mb/hp/snb_ivb_laptops: Rename `BOARD_HP_SNB_IVB_LAPTOPS`
Rename `BOARD_HP_SNB_IVB_LAPTOPS` to `BOARD_HP_SNB_IVB_LAPTOPS_COMMON`
to indicate and to make it clear that this option serves as base for
others.

Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and also with
`INCLUDE_CONFIG_FILE` disabled. coreboot.rom remains identical.

Change-Id: Icadeb8a33ae0787d2cd5da460065a2ed15256d64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16 15:55:18 +00:00
Felix Singer 339ca7f11a mb/hp/snb_ivb_laptops/Kconfig{,.name}: Reorder selects alphabetically
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and
coreboot.rom remains identical.

Change-Id: I54367c7c663ad288ccdcbd4e7289546489a68f30
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-16 15:54:35 +00:00
Mark Hsieh f25e42c4f4 mb/google/brya: set GPP_D0 to GPO
Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is
directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP
firmware successfully.

BUG=b:222188263, b:223906569
TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint
Firmware Test.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-16 04:10:59 +00:00
Ravi Kumar Bokka 42fcb2a8f4 libpayload: Parse DDR Information using coreboot tables
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59193
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-16 01:21:44 +00:00
Jes Klinke 19baa9d51e i2c: Add configurable I2C transfer timeout
This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US,
which controls how long to wait for an I2C devices to
produce/accept all the data bytes in a single transfer.
(The device can delay transfer by stretching the clock of
the ack bit.)

The default value of this new setting is 500ms.  Existing
code had timeouts anywhere from tens of milliseconds to a
full second beween various drivers.  Drivers can still have
their own shorter timeouts for setup/communication with the
I2C host controller (as opposed to transactions with I2C
devices on the bus.)

In general, the timeout is not meant to be reached except in
situations where there is already serious problem with the
boot, and serves to make sure that some useful diagnostic
output is produced on the console.

Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-15 22:06:27 +00:00
Michael Niewöhner d3b85223fd soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.

Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-15 19:22:19 +00:00
Sean Rhodes bba7e601a8 intel/common/block: Add APL and GLK PCI IDs for HDA
Add PCI ID's for APL/GLK so they can use HDA.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-15 19:21:46 +00:00
Kevin Chiu 29919f81fa mb/google/guybrush/var/nipperkin: update APU STT setting
BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     update the thermal setting value by measurement and
     pass the thermal performance test

Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-15 19:19:36 +00:00
Frank Wu bd0ba39172 mb/google/brya/var/banshee: Add camera privacy setting
Using the GPP_F19 as privacy switch for camera in banshee.

BUG=b:223712143, b:216110896
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-15 19:19:21 +00:00
Werner Zeh 9b565de3a0 lib/spd: Do not print part number if it is not available
If the DRAM part number is not available in the SPD data (meaning filled
with 0x00) do not print it in the log.

Change-Id: If7224c6e114731b1c03915a2bde80f57369d0cee
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-15 19:18:54 +00:00
Rex-BC Chen 69e3cab7f9 soc/mediatek/mt8186: change pmic hwcid from warning to info
The pmic hwcid dumping should not be a warning, so we modify it to info.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15 19:17:48 +00:00
Rex-BC Chen 129b8ae551 soc/mediatek/common: Add halt() after triggering wdt reset
It's more reasonable to halt when we trigger watchdog reset because
the whole system should be reset afterwards.

BUG=b:222217317
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-15 19:17:12 +00:00
MAULIK V VAGHELA a4cdb5b381 mb/google/brya: Disable C1-state auto demotion for Brya & Brask
C1-state auto demotion feature allows hardware to determine C1-state as
per platform policy. Since Brya sets performance policy to balanced from
hardware, auto demotion can be disabled without performance impact.

Also, disabling this feature results in 110 mW power savings during
video playback.

Note that C1state Autodemotion feature is not applicable for ADL-P SoC.
Hence recommendation is to keep it disabled.

BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Code compiles and correct value of c1-state auto demotion is passed
to FSP. Also power and performance impact has been measure by respective
teams.

Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-03-15 18:11:37 +00:00
MAULIK V VAGHELA 99356386a6 soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion
FSP has a parameter to enable/disable c1-state autodemotion feature.
Boards/Baseboard can choose to use this feature as per requirement.

This patch hooks up this parameter to devicetree

BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Check code compiles and correct value has been passed to FSP.

Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15 18:11:16 +00:00
MAULIK V VAGHELA 215a97ee1c soc/intel/adl/chip.h: Convert all camel case variables to snake case
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.

By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.

During renaming process, this patch also removes unused variables
listed below:
-> SataEnable   // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used

Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.

BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.

Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-15 18:10:41 +00:00
Subrata Banik 4703edc943 {mb, soc}: Move mrc_cache invalidating logic into `memory` common code
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced
per mainboard logic to invalidate the mrc_cache.

This patch moves mrc_cache invalidating logic into IA common code and
cleans up the code to remove unused argument `dimms_changed` from SoC
and mainboard directory.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:18:28 +00:00
Subrata Banik 47b836af96 soc/intel/common: Pass `FSPM_UPD *` argument for spd functions
This patch adds `FSPM_UPD *` as argument for
mem_populate_channel_data() and read_spd_dimm().

This change will help to update the architectural FSP-M UPDs in
read_spd_dimm().

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I770cfd05194c33e11f98f95c5b93157b0ead70c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:17:38 +00:00
Subrata Banik 2eb51aace5 {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.

This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-15 10:17:25 +00:00
Shelley Chen 5730d018d1 mb/google/herobrine: consolidate hoglin/herobrine QUP inits
Hoglin and Herobrine (proto1) should share majority of GPIOs.
Conslidating the QUP initializations in mainboard.  Also, putting
fingerprint init in a conditional as not all devices will have an FP
sensor.

BUG=b:182963902,b:223826899
BRANCH=None
TEST=booted BIOS on hoglin and check for i2c errors in dmesg

Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14 22:28:56 +00:00
Mars Chen d99e773460 mb/google/trogdor: Add variant Gelarshie
New board introduced to trogdor family.

BUG=b:223101874
BRANCH=none
TEST=make

Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com>
Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-14 22:04:26 +00:00
Casper Chang f7abb4fccf mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
Currently the BayHub eMMC enable pin is using the default
configuration from the baseboard, which leads to RTD3 not being able
to control the GPIO when exiting and entering suspend. To fix this,
program the GPIO in the ramstage GPIO table.

BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
     scope enable pin while performing suspend stress and enable pin
     works as expected.
     test suspend stress 1000 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 16:18:52 +00:00
Sean Rhodes 13f49ce754 mb/starlabs/labtop: Pull SSD Pin to low when entering S3
Pull GPP_D16 to low when suspending, otherwise it will remain active
and use power.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2cbe7caf66e8d8c27414aca3b74416c2b8115ea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-14 15:57:16 +00:00
Werner Zeh 06fe5d565d mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
DDR4 SPD data needs to be 512 byte to comply with the spec.

Though there is no vital timing data used beyond 256 byte there are some
part information which will be used to show the part info in the
coreboot log. If the buffer is too small this log shows garbage.

This patch increases the SPD buffer size from 256 byte to 512 to avoid
side effects.

Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-14 15:53:54 +00:00
Sridhar Siricilla 282c2a6472 soc/intel/common: Use generic enum type values
The patch uses generic enum type values for EOP command handler. So,
it renames cse_eop_result enum type to cse_cmd_result and also renames
the enum values to have generic name.

TEST=Build the code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie0efa8fff08318ed863010db289959d113f4767e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:51:45 +00:00
Sridhar Siricilla 1506b77b60 soc/intel/common: Use heci_reset() in the CSE TX and RX flows
The patch implements error handling as per the ME BWG guide. The BWG
recommends HECI interface reset if there is a timeout or malformed
response is received from the CSE. Also, the patch triggers HECI
interface reset if the CSE link state is not ready in the heci_send()
API.

TEST=Verify HECI Interface reset in the simulated error scenarios.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:51:29 +00:00
Sridhar Siricilla 6836da2e5a soc/intel/common: Implement error codes for for heci_send_receive()
The patch implements below changes:
1. Implements different error codes and use them in appropriate
 failure scenarios of below functions:
  a. heci_send()
  b. recv_one_message()
  c. heci_receive()

2. As heci_send_receive() is updated to return appropriate error codes
 in different error scenarios of sending and receiving the HECI
 commands. As the function is updated to return 0 when success, and
 non-zero values in the failure scenarios, so all caller function have
 been updated.

BUG=b:220652101
TEST=Verified CSE RX and TX APIs return error codes appropriately in
the simulated error scenarios.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:51:12 +00:00
Dtrain Hsu 4b8079152a mb/google/brya/var/kinox: update overridetree
1. Update override devicetree based on schematics.
2. ALC5682I-VS is for audio codec.

BUG=b:218786363, b:214025396, b:212183045
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:49:43 +00:00
Raul E Rangel b52b7010ef mb/google/guybrush: Fix building with VBOOT_STARTS_IN_BOOTBLOCK
The verstage.c file contains PSP verstage specific code. We don't need
it when using x86 verstage.

BUG=b:193050286
TEST=Build and boot guybrush with x86 verstage

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:48:57 +00:00
Cliff Huang 938f33e9f7 mb/google/brya: Set EPP to 45% for all Brya variants
This sets EPP value to be 45% for all Brya variants.

Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.

BUG=b:219785001
BRANCH=firmware-brya-14505.B
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:48:29 +00:00
Cliff Huang 0bb2225718 soc/intel/alderlake: Add EPP override support
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.

BUG=b:219785001
BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-14 15:48:11 +00:00
Teddy Shih ca9658bdb2 mb/google/dedede: Update DPTF setting
Update PL1, PL2, and temperature sensor values from thermal team,
as well as, we remove unused temperature sensors according to
baseboard/devicetree.cb and mainboard schematic. After we check
DTT setting, the thermal and performance test pass.

BRANCH=dedede
BUG=b:204229229
TEST=on beadrix, run following commands:
localhost /tmp # cat /sys/class/thermal/thermal_zone*/type
x86_pkg_temp
INT3400 Thermal
TSR0
TSR1
TCPU
localhost /tmp # cat /sys/class/thermal/thermal_zone*/temp
45000
20000
32800
32800
39000

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62729
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:47:50 +00:00
Felix Held ae7ec18d3d mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2
The one USB2 port on the XHCI2 controller should have the port ID 2.0,
since it's the first USB2 port on that XHCI controller.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a370132960939bccec4eb69a6590d0880b04137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:47:21 +00:00
Felix Held b0d555733a mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
GFX HDA is the audio controller that provides audio output via the
external display connection, ACP is the audio coporcessor for the on-
board audio codec and XHCI2 is the third XHCI controller that provides
one USB 2.0 port. All those devices are used, so enable them in the
board's devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-14 15:47:07 +00:00
Eric Lai e6f71a5d28 mb/google/nissa/var/nivviks: Hook up SD host controller GL9750
Select GL9750 driver and add power sequence according to datasheet:
GL9750S-OIY04 rev1.22.

BUG=b:223304292
TEST=check GL9750 can get enumerated by kernel 5.15.
01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01)

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-14 15:46:49 +00:00
Eric Lai 232dcb938a mb/google/nissa/var/nivviks: Enable pen garage
Enable pen garage. Pen detect is active low. And wake system when
eject.

BUG=b:223476974
TEST=evtest work as expected.
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
  Event type 0 (EV_SYN)
  Event type 5 (EV_SW)
    Event code 15 (SW_PEN_INSERTED) state 0
Properties:
Testing ... (interrupt to exit)
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-14 15:46:24 +00:00
Cliff Huang 5069f6c3c8 drivers/pcie/generic: Add support to generate code under companion device instead
Only one ACPI device should be added to a PCIe root port. For the root
ports which already have device created, the generated code from this
driver needs to be merged with the existing device.

By default, this driver will create new device named DEV0.
This change allows to generate code under an existing device.

ex: (generate code under PXSX):
    Scope (\_SB.PCI0.RP01.PXSX)
    {
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
            Package (0x01)
            {
                Package (0x02)
                {
                    "UntrustedDevice",
                    One
                }
            }
        })
    }

BUG=b:221250331
BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10 23:57:16 +00:00
Bora Guvendik 860672e987 soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table after normalizing to the zero-point value. Although
consumer CSE sku also supports this feature, it was validated on
CSE Lite sku only.

BUG=b:182575295
TEST=Able to see TS elapse prior to IA reset on Brya/Redrix

990:CSME ROM started execution                        0
944:CSE sent 'Boot Stall Done' to PMC                 88,000
945:CSE started to handle ICC configuration           88,000 (0)
946:CSE sent 'Host BIOS Prep Done' to PMC             90,000 (2,000)
947:CSE received 'CPU Reset Done Ack sent' from PMC   282,000 (192,000)
  0:1st timestamp                                     330,857 (48,857)
 11:start of bootblock                                341,811 (10,953)
 12:end of bootblock                                  349,299 (7,487)

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-10 23:23:13 +00:00
Jon Murphy 9df0085193 mb/google/skyrim: Configure WLAN
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN.  Mappping derived from Skyrim schematic.

BUG=b:214412172
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 23:22:33 +00:00
Jon Murphy d42d8ea0a2 mb/google/skyrim:Update GPIO 32
GPIO 32 was not allocated correctly, updating to reflect the native
function use of the pin

BUG=b:214412172
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 23:21:49 +00:00
Ravi Kumar Bokka 9b2914fe62 mb/google/herobrine: Add trackpad initialization
Initialize trackpad on Qualcomm reference boards

BUG=b:182963902,b:223826899
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I93e866d92cf37887a98de88b4b2d768562515670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62226
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 18:19:59 +00:00
Raul E Rangel f63dd17bb1 mb/google/guybrush: Enable DEBUG_SMI for non-serial firmware
In order to copy the PSP verstage logs into x86 cbmem, we need to enable
DEBUG_SMI. This will include the CBMEM console code in SMM. I only
enable DEBUG_SMI when UART is disabled because SMM doesn't currently
save/restore the UART registers. This will result in clearing the
interrupt enable bits and makes it so you can no longer use the TTY.

BUG=b:221231786, b:217968734
BRANCH=guybrush
TEST=Build serial and non serial firmware and verify DEBUG_SMI is set
correctly.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 17:24:06 +00:00
Raul E Rangel 54786fece8 soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
Now that SMM can write to CBMEM we can simply replay the transfer buffer
cbmem console to move it into the main cbmem console.

replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols.
Since the SMM rmodule get linked with a different linker script than
bootblock/romstage it doesn't have access to these symbols. In order to
pass these symbols into SMM, we parse the bootblock.map file and
generate an early_ram.ld script. This script is then used when linking
SMM.

I replay the buffer in `smm_soc_early_init` because this call happens
before `console_init()`. `console_init()` prints the SMM header and we
want to append the verstage contents before printing the header to avoid
confusion.

BUG=b:221231786
TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when
doing `cbmem -c`.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 17:23:35 +00:00
Raul E Rangel e6cd6caf31 cpu/x86/smm: Add weak SoC init and exit methods
This change provides hooks for the SoC so it can perform any
initialization and cleanup in the SMM handler.

For example, if we have a UART enabled firmware with DEBUG_SMI, the UART
controller could have been powered off by the OS. In this case we need
to power on the UART when entering SMM, and then power it off before we
exit. If the OS had the UART enabled when entering SMM, we should
snapshot the UART register state, and restore it on exit. Otherwise we
risk clearing some interrupt enable bits.

BUG=b:221231786, b:217968734
TEST=Build test guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I946619cd62a974a98c575a92943b43ea639fc329
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10 17:06:51 +00:00
Kevin Chiu 496734379d mb/google/guybrush/var/nipperkin: turn off WWAN DPR
Sets GPIO 42 to high to turn off WWAN DPR

BUG=b:216735313
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     make sure GPIO42 is high

Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-10 15:18:55 +00:00
Jianjun Wang b4a712279f soc/mediatek/mt8195: Enable PCIe support
Enable PCIe support for mt8195.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-10 15:18:14 +00:00
Jianjun Wang ac1410d25f soc/mediatek/mt8195: Add driver to configure PCIe
Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early
stage to reduce the impact of 100ms delay.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6799c53b03a33be91157ea088d829beb4272976
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-10 15:17:47 +00:00
Karthikeyan Ramasubramanian 112887142e soc/amd/cezanne/psp_verstage: Log the platform boot mode report
Log the platform boot mode reported by PSP verstage to PSP stage 1
bootloader. This helps to improve the debuggability.

BUG=b:193050286
TEST=Build and Boot to OS in Nipperkin. Ensure that the platform boot
mode is logged in the verstage logs.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I752ee56f2af48215a770d799432d02f0609757cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-10 15:16:32 +00:00
Karthikeyan Ramasubramanian 2c6cc6bf39 mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM
GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2.
But it is programmed incorrectly in the concerned ACPI device. Pass the
correct GPIO.

BUG=b:204401306
TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object
contains the right GPIO. Ensure that the screen visibility gets updated
by pressing the privacy screen button.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-10 15:16:14 +00:00
MAULIK V VAGHELA ed6f7e4a65 soc/intel/adl: Send EOP early in the boot sequence
As part of boot time optimization, one of the culprit was CSE where
response to End Of Post (EOP) command used to take ~60ms. Earlier patch
was pushed to delay the EOP to reduce response time to ~5-7 ms. During
this stage overall platform boot time was ~1.15 seconds.

Once boot time was optimized to ~ 1 seconds, CSE EOP time again
increased to ~80 ms since coreboot used to send EOP at the time where
CSE was busy. This created some back and forth moving of sending EOP
command function within coreboot sequence.
Upon debugging using traces, it was found that coreboot used to send
EOP late where CSE was busy loading other IP payload, so it might take
more time to respond.

In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow where
FSP used to send EOP once silicon init is done and coreboot used to
rely on FSP to send this message.

Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time
reduces from ~60 ms to ~20 ms on Brya board.

Note that once SoC code sends EOP, coreboot common code won't send it
again since common code already has check in case EOP is sent earlier.

BUG=b:211085685
BRANCH=firmware-brya-14505.B
TEST=Tested on Brya system before and after the changes. Observed ~40ms
savings in boot time.

Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-03-10 15:15:57 +00:00
MAULIK V VAGHELA 61b8f89ce3 intel/common/block/cse: Add option to send EOP early via SoC
Earlier while trying to optimize boot time End Of Post (EOP) time kept
increasing (~80 ms) when boot time decreased to around 1 second.
This was because CSE was busy with own firmware loading.

When EOP was moved later in boot stage it again created issue since CSE
got busy with other payload loading for OS boot, so response to EOP
got delayed by ~70-80 ms.

In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow
where FSP used to send EOP once silicon init is done and coreboot used
to rely on FSP to send this message.

Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP
time reduces from ~60 ms to ~20 ms on Brya QS board.

Since this setting might vary for each SoC, SoCs can decide when to send
EOP in the boot sequence. This patch adds Kconfig option to send EOP via
SoC

BUG=b:211085685
BRANCH=firmware-brya-14505.B
TEST=Code compilation is fine for Brya board. Boot time test is done
using entire patchset and EOP time is reduced to ~25ms from earlier ~80ms.

Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-10 15:15:38 +00:00
Ronak Kanabar 40ca79714a Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially"
This reverts commit 6af980a2ae.

BUG=b:199246420
Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-03-10 15:14:22 +00:00
zoey wu a4b821a9af mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4.

BUG=b:219831754

Signed-off-by: zoey wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10 15:13:22 +00:00
Raihow Shi 1c14957254 mb/google/brask/variants/moli: Reduce PSysMax to 11 A
Decrease PSysMax from 13.52 A to 11 A for Moli variant according to its power circuitry, implying Psys_Pmax = 11A * 19.5V = 214.5W

BUG=b:215258941

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10 15:13:09 +00:00
Sean Rhodes c397f004b7 soc/apollolake: Hook up VTD to CMOS
Hook up vtd_enable to CMOS value of "vtd".

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I16b43f0489f652d650e820c36b2b9bea61cf3c8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10 15:11:38 +00:00
Sean Rhodes 445466e0d6 mb/starlabs/labtop: Remove unnecessary return value from MWAK
Don't return 0x00 when running MWAK as it is not needed.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic62eab8ae5319aff37c61fc29d701d9a36ada919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10 15:08:56 +00:00
Sean Rhodes 18a7c0fc7a ec/starlabs/merlin: Use ECWR function
Use ECWR function, instead of writing raw values to emem, to avoid a
lack of syncronisation as it uses a mutex.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I90cfd3e1752fe25493bd72ea6bcab1fd9318d2e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10 15:08:40 +00:00
Sean Rhodes 26cf0f954e ec/starlabs: Write the correct value for KLBE when suspending
The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.

Switch argument will write the correct value, and prevent the setting
being reset.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I40dc78c743f4201a11ea0c26a8af716cab42b805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10 15:08:14 +00:00
Sean Rhodes 40455e9478 ec/starlabs: Write the correct value for KLSE when suspending
The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.

Switch argument will write the correct value, and prevent the setting
being reset.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I93444cdb96eaf729630b48551d0853511b584634
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10 15:07:57 +00:00
Sean Rhodes 7b0239d8ca ec/starlabs: Write the correct value for TPLE when suspending
The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.

Switch argument will write the correct value, and prevent the setting
being reset.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iabeec47bf492b698f95d86aa2d08ba9caedd75f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10 15:07:39 +00:00
Sean Rhodes 141e6fd245 ec/starlabs: Store the correct value for KLBE when suspending
The current code will read the raw value from the EC, which doesn't
match the respective setting in CMOS.

Switch argument will store the correct value.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic2a83df9a270de6d7bab295e732a6c13accbe17c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62606
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 15:07:21 +00:00
Sean Rhodes f58134b4ca ec/starlabs: Store the correct value for KLSE when suspending
The current code will read the raw value from the EC, which doesn't
match the respective setting in CMOS.

Switch argument will store the correct value.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I62e0fc3b6fcae72f2d8eacf37a390b4e4b1f0783
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62605
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 15:06:59 +00:00
Sean Rhodes 700b5155ac ec/starlabs: Store the correct value for TPLE when suspending
The current code will read the raw value from the EC, which doesn't
match the respective setting in CMOS.

Switch argument will store the correct value.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I921be8aea55b95f1ba233d2640d9bae80f8c3703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62604
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 15:06:23 +00:00
Sean Rhodes 56a6e0eb7e mb/starlabs/labtop: Always run PTS
Remove the dependency on Arg0 so PTS always runs.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I96c44397d62848231039330a32de781f75bb56bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2022-03-10 15:05:49 +00:00
Sean Rhodes 6074b20bd1 ec/starlabs/merlin: Change RPTS method to Serialized
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id64d321846dc042d4092d39ce9598d028ab15ed0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-10 15:05:24 +00:00
Sean Rhodes 0a5fc7170f soc/apollolake: Correct SMBus interrupt
This solved the error:
    i801_smbus 0000:00:1f.1: can't derive routing for PCI INT A
    i801_smbus 0000:00:1f.1: PCI INT A: not connected
    i801_smbus 0000:00:1f.1: SPD Write Disable is set
    i801_smbus 0000:00:1f.1: SMBus using polling

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idebd581b7ed6d193d83340b7dc94248df43525c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-10 15:04:59 +00:00
Rex-BC Chen 4fd80b286b soc/mediatek/mt8186: Modify internal capid to 0xE0
The mainboard may not be able to disable the internal cap, so we want
to set 0xe0 for all boards to minimize the internal cap. And a
mainboard implementation may choose XTAL with higher cload if the
frequency requirement is met, and the total capacitance can be tuned
externally for different boards.

BUG=b:218439447
TEST=set capid to 0xe0.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62563
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 15:04:34 +00:00
Cliff Huang 6277077d88 cpu/intel/common: Add support for energy performance preference (EPP)
This provides support to update energy performance preference value.

BUG=b:219785001
BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 22:57:04 +00:00
Wonkyu Kim 9f4010753d soc/intel/common: Include Meteor Lake device IDs
Reference: chapter2 in Meteor Lake EDS vol1 (640228)

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62581
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09 22:28:33 +00:00
Felix Held 697fa74027 soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER
Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to
clarify that this isn't the address the SPI flash gets mapped, but the
address of the SPI controller MMIO region. This also aligns the register
name with the PPR.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-09 19:01:15 +00:00
Tim Wawrzynczak 6f73a202d3 drivers/wifi,soc/intel/adl: Move CnviDdrRfim property to drivers
Some non-SoC code might want to know whether or not the CNVi DDR RFIM
feature is enabled. Also note that future SoCs may also support this
feature. To make the CnviDdrRfim property generic, move it from
soc/intel/alderlake to drivers/wifi/generic instead.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2022-03-09 18:03:28 +00:00
Julius Werner 797a110856 prog_loader: Change legacy_romstage_select_and_load() to return cb_err
This is passing through a cb_err from cbfs_prog_stage_load(), so it
should be declared to return that as well.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I5510d05953fe8c0e2cb511f01f862b66ced154ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62656
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09 17:20:48 +00:00
Angel Pons 43d9f8b08e vc/google/chromeos/Kconfig: Fix typo
heirarchy ---> hierarchy

Change-Id: I5cbd77a156852e6f8ad6eafc316ee33f153635b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-03-09 15:38:45 +00:00
Rex-BC Chen cb783c87d2 soc/mediatek/mt8186: set pin drive strength to 8mA for NOR
Set NOR pin drive to 8mA to comply with HW requirement.

This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186
Functional Specification.

BUG=b:218775654, b:216462313, b:212375511
TEST=SPI SI tests for AP to NOR pass for both kingler and krabby.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-09 14:31:15 +00:00
Guodong Liu ada2a63dab soc/mediatek/mt8186: Add GPIO driving functions
Add GPIO driving functions to adjust pin driving.

The value of drive strength is different for each SoC, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.

This implementation is according to chapter 5.1 in MT8186 Functional
Specification.

BUG=b:218775654, b:216462313, b:212375511
TEST=build pass

Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62471
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09 14:31:02 +00:00
David Wu 6555c4c601 mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
Based on testing results from the thermal team, they have decided
to update PL1, PL2 and PL4 for U28 SKUs.

BUG=b:221338290
TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-03-09 14:30:11 +00:00
John Su fadd0ff40a mb/google/brya/variants/felwinter: Fix stylus UI behavior bug
Fix stylus UI behavior bug.
1) it appears the kernel's gpio_key driver is not expecting
an IRQ descriptor for the `gpio` property, therefore change
to an active-low input.
2) The wakeup event was configured backwards.

Change list
- Configure GPP_A7 as "ACPI_GPIO_INPUT_ACTIVE_LOW".
- Change wakeup_event_action from ASSERTED to DEASSERTED.

BUG=b:220992812
TEST=emerge-brya coreboot chromeos-bootimage and verify pass

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 14:29:44 +00:00
Jon Murphy c07d1bdc71 mb/google/skyrim: Add FW_CONFIG Definition
BUG=b:214415048
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ia6bb3f717b3d30fe5f166dfc958024e931a070c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-09 14:29:25 +00:00
Raul E Rangel c5160986cf cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
This change will allow the SMI handler to write to the cbmem console
buffer. Normally SMIs can only be debugged using some kind of serial
port (UART). By storing the SMI logs into cbmem we can debug SMIs using
`cbmem -1`. Now that these logs are available to the OS we could also
verify there were no errors in the SMI handler.

Since SMM can write to all of DRAM, we can't trust any pointers
provided by cbmem after the OS has booted. For this reason we store the
cbmem console pointer as part of the SMM runtime parameters. The cbmem
console is implemented as a circular buffer so it will never write
outside of this area.

BUG=b:221231786
TEST=Boot non-serial FW with DEBUG_SMI and verified SMI messages are
visible when running `cbmem -1`. Perform a suspend/resume cycle and
verify new SMI events are written to the cbmem console log.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-09 14:26:26 +00:00
Wisley Chen ef44779726 mb/google/brya/var/redrix{4es}: Config VR_DOMAIN_GT's slew rate to 1/8
Config VR_DOMAIN_GT's slew rate to 1/8 as well.

BUG=b:204009588
TEST=build and verified by Power team.

Change-Id: I766b828ad83710913323cf1485e09c1e0fd5e4c2
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 14:23:42 +00:00
Wisley Chen 21fb05606f mb/google/bry/anahera{4es}: Disable TCSS port1
Disable unused TCSS Port1.

BUG=b:223082190
TEST=Build

Change-Id: I63f4b7d89a1e37a00c58201ecc88bb336d0932c9
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 14:23:25 +00:00
Wisley Chen 3e5518d72b mb/google/brya/var/anahera{4es}: Configure Acoustic noise mitigation
Enable Acoustic noise mitigation and set slew rate to 1/8

BUG=b:223082189
TEST=build and verified by power team

Change-Id: I256cc57fb54e5d62e22470a01e7efef359d57083
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 14:23:00 +00:00
Krishna Prasad Bhat a1b9f9f611 mb/google/nissa: Add fmd file for nissa
Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash
layout for brya is of 32MB size, and nissa is expected to have 16MB SPI
NOR flash. The current composition of AP firmware exceeds 16MB. To get
an estimate of the unutilized region in the current flash layout for
nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware
size to under 16MB and to remove the RW_UNUSED regions from the final
fmd file.

Below table gives the size reduction from brya fmd to nissa fmd:

+----------------+-------------------+---------------+
|     Region     | Earlier size (KB) | New size (KB) |
+================+===================+===============+
|      SI_ME     |        5116       |      3772     |
+----------------+-------------------+---------------+
| RW_SECTION_A/B |        8192       |      4344     |
+----------------+-------------------+---------------+
|   VBLOCK_A/B   |         64        |       8       |
+----------------+-------------------+---------------+
|    ME_RW_A/B*  |        3008       |      1434     |
+----------------+-------------------+---------------+
|    RW_LEGACY   |        2048       |      1024     |
+----------------+-------------------+---------------+
|     RW_ELOG    |         16        |       4       |
+----------------+-------------------+---------------+
|   SHARED_DATA  |         8         |       4       |
+----------------+-------------------+---------------+
|   VBLOCK_DEV   |         8         |       0       |
+----------------+-------------------+---------------+
|  RW_SPD_CACHE  |         4         |       0       |
+----------------+-------------------+---------------+
|    RW_NVRAM    |         24        |       8       |
+----------------+-------------------+---------------+
|      WP_RO     |        8192       |      4096     |
+----------------+-------------------+---------------+
|       GBB      |        448        |       12      |
+----------------+-------------------+---------------+

*Based on LZMA compression on ME_RW_A/B regions. With LZMA compression,
this region can be 1434K. Without this, ~665K will be more in each of
these regions.
Patch: https://review.coreboot.org/c/coreboot/+/62358/

BUG=b:202783191
BRANCH=None
TEST=Build and boot Nivviks.

Cq-Depend: chrome-internal:4584911
Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-09 14:22:46 +00:00
Krishna Prasad Bhat dddcdc5f73 mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig
Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 14:22:11 +00:00
Krishna Prasad Bhat a67a92e3c0 soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on
ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to
ME_RW_A/B regions.

On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B
regions.

FMAP REGION: ME_RW_A
Name                           Offset     Type           Size   Comp
me_rw                          0x0        raw           1275246 LZMA
(1957888 decompressed)
(empty)                        0x1375c0   null           193056 none

FMAP REGION: ME_RW_B
Name                           Offset     Type           Size   Comp
me_rw                          0x0        raw           1275246 LZMA
(1957888 decompressed)
(empty)                        0x1375c0   null           193056 none

Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 14:21:57 +00:00
Arthur Heymans 2e7e2d978b coreboot_tables.c: Expose the ACPI RSDP
The ACPI RSDP can only be found in:
- legacy BIOS region
- via UEFI service

On some systems like ARM that legacy BIOS region is not an option, so
to avoid needing UEFI it makes sense to expose the RSDP via a coreboot
table entry.

This also adds the respective unit test.

Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-09 14:21:01 +00:00
Sean Rhodes e06ded83fd soc/apollolake: Hook up CnviMode to devicetree
Hook PCH_DEVFN_CNVI (0c.0) to CnviMode.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8b51e98952a39bd432e9bc63eea57a40dd6cf106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-09 14:20:13 +00:00
Sean Rhodes 45041caaba ec/starlabs: Correct Keyboard Backlight offsets for GLK
Correct the offsets used for the keyboard backlight control:
    ECRAM_KBL_STATE         0x19
    ECRAM_KBL_BRIGHTNESS    0x18

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I23bac43301635e6b18f1cbd28311e7210b049c70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-09 14:18:59 +00:00
Sean Rhodes 7dea2e5548 mb/starlabs/labtop: Remove duplicate value from Kconfig
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0324747f936be27ee39e586124005530d5c424b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-09 14:18:40 +00:00
Michał Żygowski 0e545b252d mb/dell/optiplex_9010: Fix chassis types
Discovered this chassis identification number on Dell Precision
T1650 which is much OptiPlex 9010 alike. Precision T1650 is a Mid
Tower (MT) chassis.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2266fe39606b947a3d30a9462377fd56c39c2fa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-03-09 09:27:35 +00:00
Michał Żygowski f7c268c253 mb/dell/optiplex_9010/mainboard.c: Add missing space
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3487b0ab94e565862ed727e9a91bd1efb364d43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-03-09 09:27:06 +00:00
Subrata Banik 60b2ab8d1f {drivers/security}: Replace `cb_err_t` with `enum cb_err`
This patch replaces remaining `cb_err_t` with `enum cb_err` after commit
hash 69cc557c (commonlib/bsd: Remove cb_err_t) removes majority of
`cb_err_t` instances.

TEST=Able to build the brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3392f9c2cfb4a889a999c8ea25066c89979f0900
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-09 08:40:43 +00:00
Julius Werner 69cc557cfb commonlib/bsd: Remove cb_err_t
cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 02:18:21 +00:00
Jianjun Wang 270b0b60ac soc/mediatek: Add PCIe support
Add PCIe support for MediaTek platform.

Reference:
  - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)
  - linux/drivers/pci/controller/pcie-mediatek-gen3.c

This code is based on MT8195 platform, but it should be common in each
platform with the same PCIe IP in the future.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-09 00:48:01 +00:00
Michael Niewöhner a96c3da0c5 soc/intel/tgl: chipset devicetree: correct TraceHub device alias
Device 1f.7 is TraceHub, not the PCH Thermal device, which doesn't exist
anymore on TGL. Correct the device´s alias.

Reference: Intel doc# 631119-007
Change-Id: I30a4ab1e801f6cdb0f2e03f105bf8cc09592eed8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-08 17:55:32 +00:00
Michael Niewöhner fdc4e8e0c0 soc/intel/tgl: drop orphaned VR domains enum
Change-Id: I937bdf032e1ed86900334d41655f3e6272f66a6f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08 17:55:25 +00:00
Sean Rhodes 4d1bf7b847 ec/starlabs: Guard Max Charge in Kconfig
Guard Max Charge EC write in Kconfig so it's only used on
platforms that support it.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7be39cd9543c8253d53070950edc6908a21e864a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08 16:07:11 +00:00
Jakub Czapiga ad6157ebdf timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-08 16:06:33 +00:00
Sean Rhodes e96ade6981 mb/starlabs/labtop: Add LabTop Mk IV
Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21

No known issues.

https://starlabs.systems/pages/labtop-mk-iv-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58428
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-08 16:05:46 +00:00
Jeff Daly 1e4d9d573c sb/intel/common/firmware: Hook up adding 10GbE LAN firmware
Add ability to use ifdtool to add LAN firmware to image using Kconfig

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Id45ab4b69a85a5f8e52c0c4b130b6d729222b4c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08 15:04:03 +00:00
Jeff Daly abd4b96eb4 util/ifdtool: Add support for Denverton SoC
Denverton is a special version of IFD2 flash layout.  It defines
10GbE firmware regions (11/12) and the IE (10) region which
other IFD2 platforms do not have.  Denverton does not include the
legacy GbE region (3) or the EC region (8) which other IFD2
platforms do have.

TEST='ifdtool -p dnv coreboot.rom' and verify correct output

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08 15:03:39 +00:00
Raihow Shi 5ff5225962 mb/google/brask/variants/moli: set up gpio
Set the GPIO configuration of moli

BUG=b:220821454

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I7ec41cb843419c32337b66f3877eda5d730cea35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-08 15:03:08 +00:00
Sean Rhodes 28a30426fe ec/starlabs/merlin: Disable ACPI support last when suspending
When entering suspend, ACPI support is disabled by setting OSFG to 0x00.
This has been moved to be the final action, so it is after saving the
current EC settings.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5705efab42d2fe0fd5abc6c17eeea46ead27db17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08 15:02:33 +00:00
Sean Rhodes 2ba886aa6c ec/starlabs/merlin: Use ECRD function
Use ECRD function, instead of getting raw values from emem, to avoid a
lack of syncronisation as it uses a mutex.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I31113ef9af3a1e171e3e1f226e7adcfa0fbce61b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08 15:02:17 +00:00
Werner Zeh 4b2490eed6 drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC address
Set the log level to BIOS_NOTICE for the case where the mainboard can
not provide a MAC address since this can be a valid case. Showing this
message with log level BIOS_ERR is not appropriate.

In addition, rephrase the message to make clear that if the mainboard
does not provide a MAC address the one stored in the MAC will be used.

Change-Id: Ibfc58845f0ea47ced048b446e685c4860a29f075
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-03-08 15:01:54 +00:00
Reka Norman a909c7f613 mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for
bluetooth. So update the nivviks overridetree to enable port 10 instead
of port 8, which is the external port used for bluetooth with PCIe WLAN.

BUG=b:222595137
TEST=Bluetooth works on nivviks

Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2022-03-08 15:01:24 +00:00
Jianjun Wang 8565b94a53 device/mmio.h: Move readXp/writeXp helpers to device/mmio.h
These helpers are not architecture dependent and it might be used for
different platform.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ic13a94d91affb7cf65a2f22f08ea39ed671bc8e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62561
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-08 08:25:36 +00:00
Casper Chang 0e834a9455 mb/google/brya/var/primus{4es}: add enable pin to rtd3-cold
Currently the BayHub eMMC controller is only going into its reset
state when the RTD3 sequence is initiated. This causes it to
still consume too much power in suspend states. This CL adds the
power enable GPIO into the RTD3 sequence as well, which will turn
off the eMMC controller (a true D3cold state) during the RTD3
sequence.

BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
     test suspend stress 100 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-08 01:39:28 +00:00
Ronak Kanabar 42c460d3e5 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v3091_00
The headers added are generated as per FSP v3091_00
Previous FSP version was v2511_04
Changes include:
- Update MemInfoHob.h

BUG=b:222415800
BRANCH=None

Change-Id: I260544e0502174ab141fa31ac78ede803b4f161e
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-03-07 20:13:48 +00:00
Tim Wawrzynczak c0d7d6b564 mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
cr50 firmware revisions starting at 0.5.5 and later are able to extend
their IRQ pulses to be a minimum of 100us long. This change will enable
cr50 long interrupt pulses when it detects the feature is supported by
the detected firmware version. If the capability was detected, then
GPIO PM will be enabled for the device, otherwise it will be disabled.

BUG=b:202246591
TEST=boot brya0, check console logs for the correct message, and
verify the GPIO PM registers.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-07 19:11:57 +00:00
Tim Wawrzynczak 1e50dfbcde drivers/tpm/cr50: Add I2C bus support to cr50 driver
This allows mainboards using an I2C bus to communicate with the cr50
to reuse the functionality related to firmware version and BOARD_CFG.

BUG=b:202246591
TEST=boot on brya0, see cr50 FW version in logs

Change-Id: Ide1a7299936193da3cd3d15fdfd1a80994d70da0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-07 18:07:17 +00:00
Tim Wawrzynczak 6b8599f29a drivers/tpm/spi: Refactor out some cr50-specific logic
Mainboards accessing the cr50 over an I2C bus may want to reuse some of
the same firmware version and BOARD_CFG logic, therefore refactor this
logic out into a bus-agnostic file, drivers/tpm/cr50.c. This file uses
the new tis_vendor_read/write() functions in order to access the cr50
regardless of the bus which is physically used. In order to leave SPI
devices intact, the tis_vendor_* functions are added to the SPI driver.

BUG=b:202246591
TEST=boot to OS on google/dratini, see the same FW version and board_cfg
console prints as before the change.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-07 18:06:24 +00:00
Joey Peng f019d986b1 mb/google/brya/var/taniks: Add GL9750 SD card reader support
Add GL9750 SD card reader support.

BUG=b:222402409
TEST=Build FW and check device function normally.

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ied36719914de214ae7d810f3d03a508e95fbf66a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07 17:51:51 +00:00
Wisley Chen 18972f8bce mb/google/brya/var/redrix{4es}: Disable TCSS PCIe port1
Disable unused TCSS PCIe port1

BUG=b:217238553
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage

Change-Id: I2bdfdb23d010a1e24c986ab52b5cef6eedcb674e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07 17:51:37 +00:00
Michał Kopeć 45037f786c soc/intel/tigerlake: Hide PMC and IOM devices
Windows complains on missing drivers for these ACPI devices. Hide them
from OS as it doesn't influence the hardware operation. Linux can
still probe the drivers correctly.

TEST=Boot Windows 11 and see there are no devices with missing drivers.
Boot Ubuntu 20.04 and check that drivers corresponding to ACPI HIDs are
still probed.

Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: I6c30c08ab730749bddef7ea67c7470c1554bd572
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07 17:51:07 +00:00
Daisuke Nojiri c3dab9c427 mb/google/brya/vell: Enable USB2 port for KBD MCU
Vell has a keyboard MCU connected to USB2 port 7. This patch enables
the port.

localhost# usb_updater2 -f
Found device.
found interface 0 endpoint 1, chunk_len 64
READY
-------
start
target running protocol version 6 (type 1)
maximum PDU size: 4096
Flash protection status: 0000
version:      prism_v2.0.12137+c4ae1432f5
key_version: 1
min_rollback: 0
offset: writable at 0xc000
Current versions:
Writable      prism_v2.0.12137+c4ae1432f5

BUG=b:203664745,b:211496726
TEST=Run 'usb_updater2 -f' on Vell.

Change-Id: Iad2140dbdf5e34332388f3f43b3ede3d22e73087
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07 17:50:42 +00:00
Tim Wawrzynczak 8dc28c48e1 mb/google/brya/var/{brya*,redrix*}: Add DmaProperty for WWAN
ChromeOS considers the WWAN devices to be untrusted, therefore enable
the new DmaProperty in the WWAN's _DSD to indicate to the OS that these
devices should have IOMMU restrictions applied to them.

BUG=b:215424986
BRANCH=brya
TEST=dump SSDT

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9c9e73b7ea0575ab87cc980fb4786338047155de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-07 17:49:31 +00:00
Tim Wawrzynczak 0292703b96 drivers/wwan/fm: Include option to add ACPI _DSD for DmaProperty
Similar to commit 09c047c, the WWAN device might be considered an
untrusted device by some platforms, therefore add an option to add the
same `DmaProperty` to the WWAN _DSD.

BUG=b:215424986
BRANCH=brya
TEST=dump SSDT, see new property

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If485ac5314fae6e6faefac43fcfcea4f4cdd02c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-07 17:48:44 +00:00
Matt DeVillier e611905eb3 mb/google/hatch/var/jinlon: Fix EPS detection and disablement
Commit ebf14826
[mb/google/hatch/var/jinlon: Switch to using device pointers]
broke jinlon boards without an electronic privacy screen (EPS) by
disabling the parent device (iGPU) instead of the EPS when determined to
be not present via SKU ID.

Commit c5a3a4a6
[mb/google/hatch (baseboard): add ACPI backlight support]
broke EPS detection by adding a duplicate iGPU device to the devicetree,
resulting in the EPS entry being skipped.

Fix both of these issues by assigning the device alias to the EPS child
device, not the parent (iGPU). Rename the alias for clarity, and combine
the duplicate device definitions for the iGPU.

Test: build/boot google/jinlon SKU w/o EPS, observe GPU functional
in both firmware boot screens and Linux OS.

Change-Id: I0615ce361497abe6872085b0dec83292607e53dd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62593
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-07 17:37:15 +00:00
Matt DeVillier 269b8e2cc5 mb/google/glados: Restore ChromeEC tablet mode switch for caroline, cave
Commit 017b5c453a
[ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT config]

broke tablet mode on google/caroline and cave in mainline Linux kernels
by changing the inclusion of the ChromeEC tablet mode ACPI handler. Fix
this by addding it back (using the updated name guarding the inclusion
of the tmbc ACPI).

Test: build/boot google/cave under Linux 5.16, observe tablet mode
handled correctly.

Change-Id: Ie0ae5b6a61f104b5e973383344d289cc2e2a7b8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-07 17:22:14 +00:00
Sridhar Siricilla be082fe9f4 soc/intel/alderlake: Use Kconfigs for Descriptor Region
The patch uses Kconfigs for Descriptor Region and Descriptor Region
size instead of locally defined macros

TEST=Build and boot Brya board

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3f9461c8604383f995a4438f45286b14fb94deaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2022-03-07 17:09:57 +00:00
Sridhar Siricilla b24c528e46 soc/intel/alderlake: Define Kconfigs for Descriptor Region
The patch defines Kconfigs for FMAP Descriptor Region and Descriptor
Region size. The Kconfigs will be used by follow-up patches.

TEST=Build Brya code

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia3481acefbda885617607675aef2afbb81c21c77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07 17:09:41 +00:00
Wisley Chen c5e1a02689 mb/google/brya/var/redrix{4es}: Re-enable USB2 port for Bluetooth
BT didn't work due to commit 03c0853f4d.
Commit 03c0853f4d accidentally set the Bluetooth USB2 port
to "empty", therefore re-enable USB2 port 9.

BUG=b:217238553, b:222238381
TEST=build and verfied BT work/suspend successfully

Change-Id: Ie94ef847fc130019f1e06983fc5039f1f564cd3a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07 17:07:21 +00:00
Cliff Huang 20ee22c2cc mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and Redrix
This change is to move MPTS (Mainboard Prepare To Sleep) method from
wwan_power.asl to SSDT.

MPTS is mainboard-specific method, while wwan_power.asl is meant for
WWAN from its name.

Having fixed MPTS method (i.e. DSDT) can not cover the case where device
only presents and certain CBI bit(s) is(are) set.

In Redrix and Brya, there are SKUs with or without 5G, 4G device. For
those with 4G, MPTS method should be different. For those with no WWAN
device, no MPTS is needed.

Having MPTS generating in SSDT also eliminates the need for introducing
Kconfig flags to support different devices in the future.
MPTS method is created inside mainboard_fill_ssdt function in which the
corresponding variant function is called.

This will generate the following for the mainboard:
Scope (\_SB)
{
    Method (MPTS, 1, Serialized)
    {
        Local0 = \_SB.PCI0.RP01.RTD3._STA ()
        If ((Local0 == One))
        {
            \_SB.PCI0.RP01.PXSX.DPTS (Arg0)
        }
    }
}

Test:
Check the SSDT for MPTS method under \_SB after boot to OS
Use shutdown command and check the GPIO pins from logical analyzer

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-07 15:47:52 +00:00
Rehan Ghori 3fe7653c33 mb/google/hatch/scout: Add i2c HID driver
Add HID driver for i2c-1 for Ilitek touchscreen.

BRANCH=None
BUG=b:187289163
TEST=Build and flash coreboot; confirm an entry for hidraw for I2C-1 for
Ilitek touchscreen.

Change-Id: I9e42c36a35654cf3e2b41f78b209f4b89e8b05bd
Signed-off-by: Rehan Ghori <rehang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-07 15:29:01 +00:00
Felix Singer 43b7f41678 src: Make PCI ID define names shorter
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.

Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'

* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-07 08:32:09 +00:00
Kevin Chang 872c34a57f Revert "mb/google/brya/var/taeko: Fix PLD group order (W/A)"
This revert commit acb17fec34.

This issue was fixed in the OS, therefore the workaround can be
reverted.

BUG=b:210497855
BRANCH=firmware-brya-14505.B
TEST=build coreboot and boot into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ic836e0cf53c2f9d30bd12851be285d864b2256b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-04 15:46:49 +00:00
Ryan Chuang e6fb29f2c0 soc/mediatek/mt8195: Update header version from 1.8.1 to 1.9.1
Move some structures to common folder (CB:61293), so we need to update
header version.

BUG=none
TEST=dram calibration pass

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Id82cbef9cb10dba71489ea96f67c329de9aadc49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-04 12:17:02 +00:00
Ryan Chuang d0c03ad9f7 soc/mediatek/mt8192: Update header version from 1.7.1 to 1.8.1
Move some structures to common folder (CB:61293), so we need to update
header version for this.

BUG=none
TEST=dram calibration pass

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I8cf12f4967af116eaef88c1f688567f1da9fa6e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-04 12:16:55 +00:00
Matt DeVillier 42f214de66 mb/google/zork: fix SMMSTORE size, alignment in default FMAP
SMMSTORE needs to have 64k size (minimum) and have 64k alignment as
enforced by asserts added in commit 1ba6049
[drivers/smmstore/store.c: Add static assertion based on fmap].
Adjust size and alignment of SMMSTORE region in FMAP to ensure those conditions are met.

Test: build google/morphius without asserts being tripped for above conditions.

Change-Id: Ied04e93379e1507f5e6b2a1b71e4098a4561e5d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03 23:33:52 +00:00
Reka Norman 5cd9ab64a2 mb/google/brya/var/nivviks: Configure WCAM DMIC data pin
GPP_S6 was accidentally configured twice instead of configuring GPP_S7.
So configure GPP_S7 according to the schematics.

BUG=b:222218450
TEST=WCAM DMIC works on nivviks

Change-Id: I5de36aaa504a8856803c783564162c36416b50b7
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62511
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-03 23:30:20 +00:00
Matt DeVillier de5d8ba559 mb/google/glados: Drop TPM PIRQ
The Infineon TPM 1.2 used on glados boards doesn't use a PIRQ;
Linux only works with 'tpm.tis_interrupts=0" and Windows fails to
init the TPM citing a lack of available resources. With the PIRQ
removed, both Linux and Windows are happy / the TPM is available
for use.

Test: build/boot Linux 5.16.x and Windows 11 on google/chell

Change-Id: I544695505291bbebe062df636cc8ddd139c08c2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-03 23:30:05 +00:00
Ian Feng 2d5642c70d mb/google/brya: Change "mainboard: EC init" loglevel prefix
Change loglevel prefix "BIOS_ERR" to "BIOS_DEBUG".

BUG=b:220639445
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ie3de63fc13e7a5ed6a4b4617542851782fbb6f00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62508
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-03 23:29:25 +00:00
Felix Held af17f0b7ce soc/amd/*/northbridge,root_complex: add comment about PCI BARs
Add a comment to point out that the read_resources functions aren't
missing a pci_dev_read_resources call that would add the resources for
the BARs of the PC device.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03 22:45:41 +00:00
Felix Held b1197af7f5 soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource index
In the northbridge's and root complex' read_resources function, the
GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index
which might be misleading. Instead use idx++ as a unique index for this
resource.

TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:

Before:  PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed)
After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed)


Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8061364879d772469882fc060f92676de6f600a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03 22:45:28 +00:00
Felix Held 56b037b857 soc/amd/*/northbridge,root_complex: simplify mmconf_resource index
In the northbridge's and root complex' read_resources function, the
mmconf resource used the number of the MMIO_CONF_BASE MSR as index which
might be misleading. Instead use idx++ as a unique index for this
resource.

TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:

Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed)
After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed)

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03 22:45:02 +00:00
Tim Wawrzynczak afaee235fa drivers/{pcie,wifi}/generic: Update untrusted property name
In order to align with established standards for establishing DMA
boundaries[1] from ACPI, the UntrustedDevice property has been renamed
to DmaProperty, which follows Microsoft's implementation. After
discussions with Microsoft, they have agreed to make the `UID` property
optional, so it is left out here, and instead it can be applied to:

1) Internal PCI devices
2) PCIe root ports
3) Downstream PCI(e) devices

[1]: https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports

BUG=b:215424986

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id70e916532e3d3d70305fc61473da28c702fc397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-03 20:46:13 +00:00
Felix Held 114d650fce soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.asl
After the patch that moved the generation of the PPKG object to
Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03 18:34:15 +00:00
Felix Held 91d006c003 soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entries
Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Stoneyridge with the other AMD SoCs. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.

TEST=None, but equivalent change on Picasso was verified to not break
anything on Mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03 18:34:05 +00:00
Felix Held ebb6723115 soc/amd/picasso/acpi: rename cpu.asl to pnot.asl
After the patch that moved the generation of the PPKG object to
Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03 18:33:51 +00:00
Felix Held cf2eeff3cf soc/amd/picasso/acpi: generate PPKG object in generate_cpu_entries call
Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Picasso with Cezanne and Sabrina. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.

TEST=Mandolin still boots successfully to Linux desktop and dmesg
doesn't show any any possibly related problems.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03 18:33:43 +00:00
Sean Rhodes af4bac9e50 ec/starlabs/merlin: Don't report a battery capacity higher than design capacity
If B1FC (Battery Full Capacity) is higher than B1DC (Battery Design
Capacity), only report the design capacity. This handles cases where
the battery calibration is incorrect, and the battery runs out before
the OS thinks it's empty.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-03 14:08:02 +00:00
Shon Wang 3b9077af71 mb/google/brya/var/vell: Change to ELAN touchpanel driver
Disabled G2touch driver and add ELAN touchpanel driver for vell.
Due to incorrect BIOS setting, touch screen IC FW can't update and work.
According to ELAN's recommendations, we coreect the ELAN2513 driver's setting and change I2C address to 0x10

BUG=b:221340736
TEST=emerge-brya coreboot and can flash touch screen FW

Change-Id: I22f04fa21b542e21e88c46547779cfb55beb5c12
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
2022-03-03 14:07:43 +00:00
Raul E Rangel bd58aea706 soc/amd/common/vboot: Verify location of CBMEMC transfer buffer
Since we want to read the non-x86 CBMEMC from SMM we need to be stricter
on where we read from. This change forces the verstage binary and x86
code to agree on the CBMEMC transfer buffer location and size.

BUG=b:221231786
TEST=Boot guybrush and verify verstage transfer buffer still ends up in
cbmem

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02 21:30:06 +00:00
Dtrain Hsu e802d08011 mb/google/brya/var/kinox: update gpio settings
Configure GPIOs according to schematics

BUG=b:218786363
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I939bc5f8963e9cba762adeb4828729fd14e29520
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02 21:12:55 +00:00
Raul E Rangel 08de3e3bd8 soc/amd/common/vboot: Remove parameter to replay_transfer_buffer_cbmemc
We don't need to force the caller to look up and cast the transfer
region. We can do it in the function.

BUG=b:221231786
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02 21:11:54 +00:00
Raul E Rangel fe1418db3d soc/amd/common/vboot: Split transfer buffer methods into separate file
I want to reuse the transfer buffer methods in SMM, so I need to add
them into their own file. I renamed `setup_cbmem_console` to
`replay_transfer_buffer_cbmemc` so it has a more descriptive name. I
also fixed the comment on `verify_psp_transfer_buf`.

BUG=b:221231786
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02 21:11:32 +00:00
Raul E Rangel 409e5cb0f6 soc/amd/common/psp_verstage: Save transfer buffer during S0i3 resume
We need to save the transfer buffer so we can transfer the cbmem
console and timestamps into x86 DRAM.

BUG=b:221231786
TEST=Boot guybrush and verify S0i3 resume works. Also dumped the
transfer buffer from the OS and verified the console contents got
transferred.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02 21:09:40 +00:00
Felix Held 89d6764fd5 acpi/acpi: drop weak cpu_get_lapic_addr implementation
All SoCs/chipsets that select ARCH_X86 will end up using the
implementation in cpu/x86/lapic/lapic.c, so to avoid confusion, drop the
unused weak implementation that returns a different value.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iffcd8c80260f9a7d81dda41a0ad08bffc7620c33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-02 18:26:19 +00:00
Werner Zeh 257e2507fa mb/siemens/mc_ehl: Disable HS400 mode for eMMC
In order to achieve a stable eMMC interface disable the HS400 capability
of the host controller. This will result in an operating mode of maximum
HS200 (200 MHz single data rate) which leads to a more relaxed timing.

Change-Id: I0e125dd569b00f59ae0fd2f76169c4461291b47a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-03-02 18:25:54 +00:00
Arthur Heymans f879d36551 device/pci_device.c: Improve pci_bridge_route() readability
Both the secondary and subordinate bus numbers are configured in this
function but it's not easy to search for in the tree as the PCI writes
are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Use separate
variables and PCI config writes to improve the readability.

Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-03-02 13:15:12 +00:00
Rex-BC Chen c89f252608 soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
The XTAL 26MHz test failed on krabby, so we adjust RTC capid from
default value 0x88 to 0xC0 for MT8186. We also add a new log message
to show the capid value which is read from MT6366.

This implementation is according to chapter 5.13 in MT8186 Functional
Specification.

BUG=b:218439447
TEST=set capid to 0xc0.
TEST=XTAL 26MHz test passed.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-02 13:13:24 +00:00
Rex-BC Chen 025fb17372 soc/mediatek: remove unused RTC_GPIO_USER_MASK
RTC_GPIO_USER_MASK is not used in any drivers, so we remove them.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-02 13:13:10 +00:00
Zhuohao Lee d036a70d74 mb/google/brya: enable the SPD_CACHE_ENABLE
google/brask is using SODIMMs for DRAM. Reading spd data is
surprisingly slow (~170 ms), therefore enable the SPD cache.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=run on the device and measure the boot time decrease.

Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02 13:10:47 +00:00
Zhuohao Lee 84eb532ec3 mb/google/brya/variants: add the smbus addr for dimm1
Align the setting with the adlrvp

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and works correctly in the brask

Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02 13:10:33 +00:00
Zhuohao Lee b8b40964fc mb, soc: Add the SPD_CACHE_ENABLE
In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
     the device could speed up around 150ms with this feature.

Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02 13:10:21 +00:00
Gaggery Tsai 9d0fc3f396 mb/google/brya/var/vell: Remove Rcomp settings
This patch removes Rcomp settings. In MRC design, it checks if the
Rcomp settings from the board is 0 or null, if so, it uses the
recommended Rcomp values. Otherwise, it uses the Rcomp settings passed
from the UPD. From the change history of MRC, we're chasing a moving
target. This RCOMP setting in coreboot is an old setting while the
Rcomp settins in MRC are optimized settings. Moving forward, if there
is a new stepping, it might be changed again which increases the
maintenance effort in coreboot. IMHO, we should let MRC to set the
optimized RCOMP values for the design.

BUG=b:219378758
TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and
     PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are
     filled properly by MRC.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02 13:09:28 +00:00
Casper Chang 7a7a533725 mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after
warm reboot.
Config GPP_B3 unlocked to make reboot works on primus. Also set
GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power
on sequence.

BUG=b:221488504
TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage
     test reboot 30 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-02 07:41:43 +00:00
Julian Schroeder 017ad9a41d soc/amd/common/fsp/fsp_validate.c: print warning instead of error
If an AMD FSP binary has no valid image revision information, print a
warning instead of an error.

Change-Id: Ie9c5a387b81205fe93382778090260e41e261776
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-01 20:59:29 +00:00
Raul E Rangel 554f9e6b20 mb/amd/chausie: Always enable developer mode
Chausie doesn't have recovery mode buttons so it's impossible to
manually enter recovery mode to enable developer mode. This means we
need to force developer mode.

BUG=none
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 17:29:58 +00:00
Tim Wawrzynczak 63632d7d82 security/tpm: Add vendor-specific tis functions to read/write TPM regs
In order to abstract bus-specific logic from TPM logic, the prototype
for two vendor-specific tis functions are added in this
patch. tis_vendor_read() can be used to read directly from TPM
registers, and tis_vendor_write() can be used to write directly to TPM
registers.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I939cf5b6620b6f5f6d454c53fcaf37c153702acc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-01 16:52:31 +00:00
Tim Wawrzynczak 591c7ebf18 drivers/tpm/spi: Convert static functions to enum cb_err return types
Instead of using raw integers to indicate success/failure, enum cb_err
can be used to makes things clearer, so this patch converts most
functions to return that instead of int.

TEST=boot to OS on google/dratini, no TPM errors seen

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ifb749c931fe008b16d42fcf157af820ec8fbf5ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 16:52:21 +00:00
Kevin Chiu d736fd4ea7 mb/google/guybrush/var/nipperkin: update thermal setting
Enable STT and decrease sustained_power_limit_mW to 12W

BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     update the thermal setting value by measurement and
     pass the thermal performance test

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I5b7b0156fb4a1e2be8528a5787ed82acff93f06c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-01 11:57:58 +00:00
MAULIK V VAGHELA a4af1b58a5 intelblocks/cse: Skip sending EOP during S3 resume
coreboot should skip sending EOP during S3 resume since CSE doesn't
require EOP in resume path.

Currently EOP is being sent during PAYLOAD_BOOT or PAYLOAD_LOAD stage
which doesn't get called during S3 resume.

In case EOP is moved in earlier stage, coreboot might send EOP in S3
resume as well. This patch adds check before calling cse_send_eop.

BUG=b:211085685
BRANCH=None
TEST=Check by moving EOP to earlier stage. EOP sending is skipped during
S3 resume.

Change-Id: I8f22446974bc1e7b2d57468633c36bb99ffe1436
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-01 11:57:38 +00:00
Sean Rhodes 5da05b6e35 mb/starlabs/lite: Add StarLite Mk III
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iddbf2022d03735d6a0e6d098c21643f5fdc875f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-01 11:56:26 +00:00
Sean Rhodes c64626c9d9 ec/starlabs/merlin: Remove unused keyboard.asl
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ife0f5b8b6102b543a7ace6739fa44d32ca80dcde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-01 11:55:06 +00:00
Sean Rhodes f6ea89d684 ec/starlabs/merlin: Add spaces to adhere to coding style
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0e965513d5888398834cab8c8445e97372f2b115
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-01 11:54:53 +00:00
Krishna Prasad Bhat e1ff978c9a mb/intel/adlrvp: Enable eMMC device for ADL-N RVP
Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder
Lake N RVP from devicetree.

Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-03-01 11:54:26 +00:00
Raul E Rangel 56dbb4ac39 lib/Makefile: Add ability to specify -ldflags for rmodules
This will allow linker flag customization for rmodules.

BUG=b:221231786
TEST=Build guybrush with patch train and verify ldflags are passed

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib65476759e79c49d90856dcd7ee76d7d6e8a679a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-28 22:02:22 +00:00
Fred Reitberger 527d73f1bf mb/amd/chausie/Kconfig: Add EC FW to RO_REGION_ONLY
Include chausie EC and EFS only in the RO region when building with
vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B
regions.

Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28 21:28:13 +00:00
Tim Wawrzynczak 7a94ad720e soc/intel/common/block/acpi: Return existing Object for _DSM subfunction
Currently the LPIT Get Constraints _DSM subfunction returns a package
containing the path to a nonexistent device (\NULL). This is used to
work around an issue with Windows, where returning an empty package will
cause a BSOD.  However, using this non-existent device can also cause
confusion, as on Linux, it shows an error in dmesg, e.g.

    ACPI Error: AE_NOT_FOUND, While resolving a named reference package
    element - \NULL (20200925/dspkginit-438)

Therefore, this patch modifies this returned package slightly to include
the path to ACPI_CPU_STRING for CPU 0, which should always be emitted on
Intel platforms that use the PEP driver.

Tested on google/brya0 on ChromeOS 5.10 kernel
Tested with current Windows 11 ISO

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If74a1620ff0de33bcdba06e1225c5e28c64253e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
2022-02-28 18:50:13 +00:00
Arthur Heymans b4ba289fa5 cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
This will allow to migrate all platform to the parallel_mp init code
and drop the old lapic_init code.

Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58700
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-28 13:33:59 +00:00
David Wu 6179f7b618 mb/google/brya/var/kano: add enable_off_delay_ms to 30
Kano changes load switch of touch screen to TPS22914C (is not with
discharge) on DVT board, EE suggests to add enable_off_delay_ms to 30ms
to fix DUT can't enter S0ix issue.

BUG=b:220811619
TEST=Boot kano to OS and run S0iX test 2500 cycles.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7ea5693d457c5f60246348d2d8fa1f4130b7d4c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2022-02-28 13:32:04 +00:00
Jon Murphy e6e46c968a mb/google/skyrim: Enable PCIe devices in devicetree
BUG=b:214414301
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6b12950843f3ee3b5abe4ef9c6bd5aba528cc4ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:31:40 +00:00
Jon Murphy 0bc013b15a mb/google/skyrim: Enable AP <-> D2 communication
Configure D2 I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for D2 device and enable the required
config items.

BUG=b:214414776
TEST=Build

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I57b6d0e9da9935596e54b8eab400440e518b4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28 13:31:27 +00:00
Jon Murphy ee67ddc707 mb/google/skyrim: Add eSPI configuration
BUG=b:214413613
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If1177dda705738222ce7f6f42dceafb14d37c98c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:30:58 +00:00
Jon Murphy 4f4f32ba20 mb/google/skyrim: Add initial fch irq routing
BUG=b:214417045
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6de1e4877323e18ec9d95f182c7d3fccd51d4998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:30:31 +00:00
Jon Murphy 410b7cb97e mb/google/skyrim: Add initial I2C configuration
Add I2C peripheral reset configuration required during early init.
Enabled I2C generic and HID drivers.

BUG=b:214414677
TEST=Build

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I06e564cf6eca844101d70ff865f3074b45a55d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28 13:30:13 +00:00
Jon Murphy f79cc51b3f mb/google/skyrim: Log mainboard events to elog
BUG=b:214414851
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic427f88fee7739b064a8836e07841c80c99212a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:29:57 +00:00
Jon Murphy 6ad5f4ec16 mb/google/skyrim: Add ACPI configuration for USB ports
The USB port configuration was derived from the PPR and schematics.
This board has 6(some multi-purpose) ports.
Primary functions are:
2 USB-C ports
1 USB SS+ type A port
2 Cameras
1 Bluetooth transceiver

BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:29:42 +00:00
Jon Murphy 6e368f79ec soc/amd/sabrina: Add XHCI configuration
Add xhci 2 controller support for additional USB port/ Dummy setting

BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28 13:29:24 +00:00
Cliff Huang 96bb0ba9e7 drivers/wwan/fm: Add support for _PTS for Fibocom 5G WWAN
Add DPTS (device prepare to sleep) method that is to be called in
mainboard's \_SB.MPTS, which is called in _PTS.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie308f74940a33711a398bc11d0550cb06b55cdcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-28 13:29:02 +00:00
Nico Huber f514b8ae82 device/pci_device: Fix PCIe bridge detection
PCI bus 0 is not below any PCI device. In case of pci_domain_scan_bus(),
it's our virtual `domain` device.

Expecting a PCI device above bus 0 resulted in undefined behavior for
all boards with PCI. Only boards with a PCI device 00:00.0 that looked
like a PCIe bridge showed issues, though (e.g. OCP/DeltaLake).

Change-Id: I1fd68b9dc0d2e388ec2bbba4adbadd33e14f0171
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 777ffff442 (device/pci_device.c: Scan only one device for PCIe)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62376
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-28 13:28:12 +00:00
David Wu e6ab52e289 mb/google/brya/var/kano: Add wifi sar table
1. Add wifi sar table for kano
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG

BUG=b:214393458
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Icddd583e5ee31e08b615df6fb2f4ceeb7f0c8131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-02-28 13:27:53 +00:00
Angel Pons 0cd1a87d50 sb/intel/lynxpoint: Fix up comment
Change-Id: Ie46b63d192b8e4871442f6b0db5b1575168f89ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-28 13:27:22 +00:00
Frank Chu 9fc741d32f mb/google/dedede/var/pirika: Add Wifi SAR for pasara
Add wifi sar for pasara

BUG=b:216411442
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ida475307c8448c5c2758c289da7708484bcb89e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28 13:27:11 +00:00
Jon Murphy b4156412db mb/google/skyrim: Enable USB controllers in devicetree
BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:39:02 +00:00
Jon Murphy 10ff9375ae mb/google/skyrim: Enable internal graphics
BUG=b:214416935
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-26 00:19:36 +00:00
Jon Murphy 4b2e04a53b mb/google/skyrim: Enable console UART
BUG=b:214414501
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26 00:18:40 +00:00
Jon Murphy eab1827b66 mb/google/skyrim: Set up FW_CONFIG
BUG=b:214415048
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ida8d226f84726f2eb03b07618907b0ce3928bec5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:18:09 +00:00
Jon Murphy e3e1801a33 mb/google/skyrim: Enable eSPI SCI events
Enable ESPI SCI events

BUG=b:214416630
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If47ba561f140eb474cad30e24b0a7c85cdd76203
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62149
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:17:40 +00:00
Jon Murphy 2a7445a165 mb/google/skyrim: Add smihandler
BUG=b:214415408
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:17:25 +00:00
Jon Murphy cbf0f98c61 mb/google/skyrim: Enable Chrome EC
BUG=b:214413613
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:17:10 +00:00
Jon Murphy 9e00571b49 mb/google/skyrim: Enable variants for Skyrim
BUG=b:214414033
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I034ab8a06842bee12060103b4a1bc4e3db69e42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26 00:16:39 +00:00
Jon Murphy af025d6ee1 mb/google/skyrim: CONFIG_CHROMEOS
BUG=b:214415401
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I045f76c366a1a72814536a2be984b7ad5a438a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62043
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:16:17 +00:00
Jon Murphy 960fb2f4b8 mb/google/skyrim: Enable ACPI tables
Add GPIO initialization and ACPI generation for tables

BUG=b:214415303
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:15:58 +00:00
Subrata Banik 4de2c342fb soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq
This fixes no practical problem, especially for coreboot where only
one process should access the SPI controller. It makes the code look
more spec compliant.

As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.

Software must initiate the next SPI transaction when this bit is 0.

Add non-blocking mechanism with `5sec` timeout to report back error
if current SPI transaction is failing due to on-going SPI access.

BUG=b:215255210
TEST=Able to boot brya and verified SPI read/write is successful.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-26 00:15:28 +00:00
Raul E Rangel 737ad67d12 soc/amd/common/psp_verstage: Add missing post codes on S0i3 resume
We print these out in the normal flow, so lets add them for S0i3 resume
as well.

BUG=b:221231786
TEST=Perform suspend/resume cycle on guybrush and verify we get the new
POST codes.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26 00:09:27 +00:00
Raul E Rangel 5e0ed5016c soc/amd/{common/psp_verstage,soc/picasso}: Remove workbuf shrinking
This feature was never used. Let's remove it to keep things simple.

BUG=221231786
TEST=Boot test guybrush and morphius and verify transfer buffer is
correctly passed.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-26 00:09:18 +00:00
Zhuohao Lee 0b108a14c0 mb/google/brask: Update PCH power cycle related durations
The power rails discharge time of brask has been measured, the longest
discharge time of the power rails are smaller than 150ms so it is safe
to set the pwr_cyc_dur to 1 second. Since the brask is derived from the
brya, we could apply the same setting from the brya. The setting is
copied from commit dee834aa.

BUG=b:214454454
BRANCH=firmware-brya-14505.B
TEST=`test_that firmware_ECPowerButton` passed.

Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25 20:46:19 +00:00
Zhuohao Lee 09f3b6cf21 mb, soc: change mainboard_memory_init_params prototype
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the
input which make the board has no chance to modify data in the
FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing
the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on
its requirement.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass

Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25 20:45:49 +00:00
Usha P 3ecee3cdd9 mb/intel/adlrvp: Add support for MAX98373 codec
- Add configurability using FW_CONFIG field in CBI, to enable/disable
I2S codec support for MAX98373 codecs
- AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion
board

Bug=None
Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on
expansion card

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-25 20:44:27 +00:00
Elyes Haouas 92c2ccda0c sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macro
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 20:42:36 +00:00
Arthur Heymans bd90a226a3 nb/intel/ironlake: Fix sending HECI messages
This code only worked when the payload (a packed struct) was 4 byte
aligned. With gcc11 this happens to not be the case.

Change-Id: I5bb4ca4b27f8554208b12da177c51091ea6a108f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 20:41:54 +00:00
MAULIK V VAGHELA d9c5b14f1e intelblocks/pcie: Correct mapping between LCAP port and coreboot index
coreboot uses port index which is 0 based for all PCIe root ports.
In case of PCIe remapping logic, coreboot reads LCAP register from PCIe
configuration space which contains port number (mostly 1 based). This
assumption might not be true for all the ports in coreboot.

TBT's LCAP registers are returning port index which are based on 2.
coreboot's PCIe remapping logic returns port index based on index 1.

This patch adds variable to pcie_rp_config to pass lcap_port_base to the
pcie remapping function, so coreboot can map any n-based LCAP encoding
to 0-based indexing scheme.

This patch updates correct lcap_port_base variable for all PCIe root
ports for all SOCs, so that function returns correct 0-based index from
LCAP port number.

BUG=b:210933428
BRANCH=None
TEST=Check if code compiles for all ADL boards

Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 18:59:51 +00:00
Felix Held 928a9c8f04 cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic number
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:44:45 +00:00
Felix Held 972d9f2cce arch/x86: consolidate HPET base address definitions
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:44:11 +00:00
Felix Held 887d4ed912 soc/intel/denverton/include/iomap: drop unused DEFAULT_HPET_ADDR define
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie92bd54b072d545944b3d0251e9727ce493bb864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 17:43:11 +00:00
Felix Held f47d17d81e sb/intel/common/hpet: use HPET_BASE_ADDRESS definition
Use the definition from arch/x86 instead of a local redefinition.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If172cde267062a8e759a9670ac93f4e74e8c94d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 17:42:59 +00:00
Felix Held 4b2464fc90 arch/x86: factor out and commonize HPET_BASE_ADDRESS definition
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-25 17:42:45 +00:00
Felix Held 46a3a044ad soc/intel/baytrail,braswell/include/iomap: drop unused HPET_BASE_SIZE
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I875916488a99af768d087691549a93f6fd5169ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 17:42:31 +00:00
Felix Held 4e03727e63 arch/x86/Kconfig: add HPET_MIN_TICKS
Some Intel southbridges have HPET_MIN_TICKS in their Kconfig files, but
the CONFIG_HPET_MIN_TICKS symbol is used in the common acpi code in
acpi/acpi.c, so define this option in arch/x86/Kconfig to have it
defined in all cases where the function that ends up using this
information gets called. Since we now have the type information for this
Kconfig option in a central place, it can be dropped from the Kconfig
file of the Intel southbridges that change the default value.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe012069dd4b51c15a8fbc6459186ad2ea405a03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:42:20 +00:00
Felix Held 7f8c737fe9 acpi/acpi: use read32p instead of pointer dereferencing
Using read32p to get the contents of the first 4 bytes of the HPET MMIO
region instead of a pointer dereference should clarify what's done in
that piece of code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iecf5452c63635666d7d6b17e07a1bc6aa52e72fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62297
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:41:58 +00:00
Jason Glenesk ce876aaa8f mb/google/guybrush: enable coreboot to request spl fuse
Enable guybrush based platforms to send fuse spl command to PSP when
required.

BUG=b:180701885
TEST=On a platform that supports SPL fusing. Confirm that PSP indicates
fusing is required, and confirm coreboot sends command. Fusing is
required when the image is built with an SPL table requiring newer
minimum versions. A message indicating fusing was requested will appear
in the serial log. "PSP: Fuse SPL requested"

Change-Id: I7bce01513af4e613f546e491d9577c92f50cb85c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-02-25 16:43:15 +00:00
FrankChu 85c64e3ff6 mb/google/volteer/var/collis: update default codec HID to 10EC5682
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:192535692
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30fa886a39bd7082442a3a2b95fdf2d2b84ddd1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-25 16:39:47 +00:00
Shelley Chen 1d72afbd2a herobrine: Add Villager variant
BUG=b:218415722
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_VILLAGER -x -a -B

Change-Id: I84935ea280023cb0df1dd51fcd2a83d80db17710
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-25 07:01:48 +00:00
Jon Murphy d2873756a7 mb/google/skyrim: First pass GPIO configuriation for Skyrim
BUG=b:214415401
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I60b3b3cd50eea1253df2ae3e0aea83bb89e54702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62042
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 02:07:10 +00:00
Felix Held 26f0310317 mb/amd/chausie/devicetree: add i2c_scl_reset
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23ec6bcb6a2b3627866165972fd6ba1c75367533
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62188
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 00:44:45 +00:00
Felix Held 9ec4bf2fcb mb/amd/chausie/devicetree: enable I2C controllers
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97f37c45ffe945e6bb071c8205343943edc524ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61871
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 00:44:36 +00:00
Kevin Chang f1313ece44 mb/google/brya/var/taeko: Add GL9750 SD card reader support
Add GL9750 SD card reader support.

BUG=b:220987566
TEST=Build FW and check device function normally.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I8f6ca45a320d34dfd820ef0b6e0d3163fab26027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 21:39:25 +00:00
Jon Murphy 9042427ea2 mb/google/skyrim: Add stubs to configure GPIOs
BUG=b:214415401
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ieeda9aa0c18b5befea67d2849bd4114da0c348a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62041
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 21:38:18 +00:00
Sean Rhodes 3a260ad8f1 soc/apollolake: Allow configuring individual USB ports on GLK
Allow configuring the limited fields that FSP-S provides.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I56c37338eaa978fdb2c63807331493e8aecbdf60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-24 17:10:37 +00:00
Elyes Haouas 532e043b66 treewide: Write minor version at acpi_create_fadt() function
When "fadt->FADT_MinorVersion" is not explicitly set to the right value, gcc sets it up to "0".
So set it correctly for treewide.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ic9a8e097f78622cd78ba432e3b1141b142485b9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Lance Zhao
2022-02-24 17:10:02 +00:00
Terry Chen 95f8f92451 mb/google/brya: Add SPD configs for Crota
Add a mem_parts_used.txt for Crota, containing the
memory parts used in proto builds. Generate Makefile.inc and
dram_id.generated.txt using part_id_gen.

DRAM Part Name                 ID to assign
MT62F1G32D4DR-031 WT:B         0 (0000)
MT62F512M32D2DR-031 WT:B       1 (0001)
H9JCNNNBK3MLYR-N6E             1 (0001)
H9JCNNNCP3MLYR-N6E             0 (0000)
K3LKBKB0BM-MGCP                2 (0010)

BUG=b:215443524
TEST=emerge-brya coreboot

Change-Id: I0ff6ffea4b879b6e1287e1e3cb9fd36a80f52ed6
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-24 01:25:32 +00:00
Angel Pons 4cee77bce3 nb/intel/ironlake: Clean up `jedec_read()` function
Deduplicate a condition and reflow some lines.

Tested on HP ProBook 6550b, still reaches TianoCore payload.

Change-Id: If5786f34585e15100385d452b5b03a36da4c7c87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-24 01:20:41 +00:00
Angel Pons fa5ed059eb nb/intel/ironlake: Fix some quickpath init magic
Correct some Quickpath initialisation steps according to findings from
two different Intel reference code binaries as well as MCHBAR register
dump comparisons between vendor firmware and coreboot.

The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources.

Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init
now completes successfully instead of causing hangs before raminit.
Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still
reaches payload (e.g. TianoCore).

Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-24 01:18:56 +00:00
Angel Pons e2531ffaa8 nb/intel/ironlake: Move out HECI remainders into southbridge
Move the remaining HECI-related stuff to southbridge scope, as the HECI
hardware is in the southbridge. Note that HECI BAR is now enabled a bit
earlier than before, but this shouldn't matter.

Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-24 01:18:03 +00:00
Robert Chen e39d371909 mb/google/brya/var/vell: Corrects ACPI _PLD macro setting
This patch is to denote the correct side of ACPI _PLD usb C ports.

        +-------------------------+
        |        LCD              |
        |                         |
        |                         |
        +-------------------------+
PORT_C2 |                         | PORT_C1
PORT_C3 |  DB                 MB  | PORT_C0
        |                         |
        +-------------------------+

BUG=b:220634230
TEST=emerge-brya coreboot

Change-Id: I84515f98b6cdab5768df75690b0f5ca1bb9ad96d
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 00:32:24 +00:00
Wisley Chen 77711b8677 mb/google/brya/var/anahera{4es}: Add MT53E2G32D4NQ-046 WT:C support
Add new memory MT53E2G32D4NQ-046 WT:C support

BUG=b:220821471
TEST=emerge-brya coreboot

Change-Id: I4c21254213c2107d015adebb510612e0256ffb5c
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 00:31:58 +00:00
Wisley Chen a243111a6d mb/google/brya/var/redrix{4es}: Add MT53E2G32D4NQ-046 WT:C
Add new memory MT53E2G32D4NQ-046 WT:C support.

BUG=b:220804962
TEST=emerge-brya coreboot

Change-Id: I3353d7c119798ebb0b5ee1ea32161e54b4eec826
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 00:31:41 +00:00
Eugene Myers b2c681fc4a security/intel/stm: Make STM setup MP safe
Some processor families allow for SMM setup to be done in parallel.

On processors that have this feature, the BIOS resource list becomes
unusable for some processors during STM startup.

This patch covers two cases: (1) The BIOS resource list becomes twice
as long because the smm_relocation function is called twice - this is
resolved by recreating the list on each invocation. (2) Not all
processors receive the correct resource list pointer - this is resolved
by having every processor execute the pointer calculation code, which is
a lot faster then forcing all processors to spin lock waiting for this
value to be calculated.

This patch has been tested on a Purism L1UM-1X8C and Purism 15v4.

Signed-off-by: Eugene Myers <cedarhouse@comcast.net>
Change-Id: I7619038edc78f306bd7eb95844bd1598766f8b37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2022-02-24 00:27:37 +00:00
Eugene Myers a514192ffe security/intel/stm: Use correct SMBASE for SMM descriptor setup
Commit ea3376c (SMM module loader version 2) changedhow the
SMBASE is calculated.

This patch modifies setup_smm_descriptor to properly acquire the
SMBASE.

This patch has been tested on a Purism L1UM-1X8C and a Purism 15v4.

Signed-off-by: Eugene Myers <cedarhouse@comcast.net>
Change-Id: I1d62a36cdcbc20a19c42266164e612fb96f91953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61688
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 00:27:08 +00:00
Felix Held b582ce0814 arch/x86/Kconfig: drop HPET_ADDRESS_OVERRIDE
Commit b433d26ef1 (arch/x86: Define
HPET_ADDRESS_OVERRIDE) added this Kconfig option and referenced the
via/cx700 chipset which has been dropped before the 4.9 release. No SoC
in the current tree selects HPET_ADDRESS_OVERRIDE and all SoCs have
their HPET mapped at 0xfed00000, so drop this unused and no longer
needed Kconfig option.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4021ed6f84473c7a9223323fc8aa5d3f935d8084
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62276
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 00:14:10 +00:00
Felix Held 6f413d1c3f soc/amd/*/include/soc/iomap.h: rework HPET base address check
The AMD SoCs had a check to make sure that HPET_ADDRESS_OVERRIDE isn't
set so that the HPET_ADDRESS Kconfig option will have the right default
value. Instead check if the HPET_ADDRESS Kconfig value matches the
HPET_BASE_ADDRESS define in the SoC code which is the case if
HPET_ADDRESS_OVERRIDE isn't selected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icf1832eb36c031e93ba24f342e9a8a7bf13faecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 00:14:02 +00:00
Rob Barnes 22372f4ac9 cr50: Increase cr50 i2c probe timeout
Turns out 200ms still isn't enough in the worst reset conditions.
There's been some reports of failures at 200ms with some older
cr50 versions. Let's not take any chances and bump this way up
since if this fails, it prevents boot.

BUG=b:213828947
BRANCH=None
TEST=Reboot and suspend_stress on Nipperkin

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5be0a80c064546fd277f66135abc9d0572df11cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-23 16:26:03 +00:00
Xi Chen d239aaf741 src/mediatek: Refactor dramc_param to share more structures
The ddr_base_info struct, which stores basic DDR information, should be
platform independent. Currently the struct is defined in each SoC's
dramc_parah.h. To prevent code duplication, move it as well as other
related structs and enums to a common header.

Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-02-23 15:06:27 +00:00
Rex-BC Chen 3a3920263a soc/mediatek/mt8186: disable VSRAM_CORE
VSRAM_CORE is not used on kingler/krabby, so we disable it.
This implementation is according to chapter 3.7 in MT8186 Functional
Specification.

BUG=b:220071688
TEST=the rail steadily shows 0V in either S0, S3, and S5.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5256f6a2c0ca5a951dc79f564575b526a84463fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62253
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-23 15:05:40 +00:00
Uwe Poeche eee62c1537 drivers/mrc_cache/mrc_cache.c: Change loglevels
Since commit 7cd8ba6eda (console: Add loglevel prefix to interactive
consoles) on the very first boot some errors occur because no MRC data
is present in the MRC cache. This is normal because the memory training
is not done yet.

This patch changes the loglevel to BIOS_NOTICE which will prevent an
error in the log in this case.

Change-Id: I1e36590e33507515e5b9dd4eb361b3dbe165511e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61973
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-23 15:05:12 +00:00
Mario Scheithauer f6056113e5 console: Fix LOG_FAST macro
In the LOG_FAST macro, the comparison was incorrectly made with 'level'
value. Correct is the comparison with 'speed'.
With the wrong comparison you cannot set a lower level for console log,
the highest level is always output.

TEST:
- Boot mc_ehl2 with console log level 5 and check output

Change-Id: Ib5b4537ae2cbf01c51c3568d312b5242c4bee7bb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-22 23:13:50 +00:00
Elyes Haouas e6ce594da6 mb/gizmosphere/gizmo/OptionsIds.h: Remove extra empty line
Change-Id: I8ad968da1771004f7f5869e5434473a498edeaa2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:25:38 +00:00
Elyes Haouas d08a76e3ea mb/lenovo/g505s/acpi/ec.asl: Correct the path to "mainboard.h"
Change-Id: I273e29a26cf1c1ba34b95eb11bcb59a1360371e1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:25:25 +00:00
Elyes Haouas 6d508dfc2d mb/lenovo/g505s: Format code
Change-Id: I9cce00e1634d62a63b3563d54a7a0c56058d0e39
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:23:24 +00:00
Elyes Haouas 8f38e5f5dc sb/amd/cimx/sb800/amd_pci_int_defs.h: Fix serial IRQ INT name in comment
Change-Id: If351d93c47de2ef76fb24525ff6d134b35c5f3fe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:18:24 +00:00
Elyes Haouas 4450bee6b3 sb/amd/pi/hudson/early_setup.c: Fix typo in comment
Change-Id: Ib631cdc0794dc91df27cb984d5c585e0eee4a2ad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:17:15 +00:00
Elyes Haouas 090fcec945 southbridge/amd/*/*/reset.c: Reduce stylistic differences
Change-Id: I2f58098e786e9b61b0d059723c375a90559e95a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:15:39 +00:00