This comment was added with the AMD family 15h Trinity IOMMU support in
commit 88ebbeb7e2 and looks like a copy of
the comment about the subtractive decode ranges in the LPC device. The
IOMMU doesn't have any subtractively decoded I/O or MMIO ranges and this
is also not what the code does. This resource is the MMIO region to
configure the IOMMU instead, so fix the comment in all copies of the
IOMMU support code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Sabrina is compatible with the common AMD ACPIMMIO function block
mapping and access functions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I890375654a9cb1156e481c5586007ac81ab84120
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The PM2 ACPIMMIO region should only be accessed with 8 bit accesses.
Using 16 or 32 bit read accesses will return the data from the first
byte for all 2 or 4 bytes and 16 or 32 bit write accesses will result in
only the first byte being written which is both unexpected behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge
and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on
Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is
only defined for Sabrina. Since the default value of undefined bits is 0
it isn't a problem to have descriptions for reserved reset status bits
on some SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Implementation for setup_lapic() did two things -- call
enable_lapic() and virtual_wire_mode_init().
In PARALLEL_MP case enable_lapic() was redundant as it
was already executed prior to initialize_cpu() call.
For the !PARALLEL_MP case enable_lapic() is added to
AP CPUs.
Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Sabrina has no SATA controller, so remove the corresponding PIRQ
mapping. This was verified with PPR #57243 Rev 1.53.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The common AMD data fabric register access code is valid for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97fb2c6006c09297584845a83342e75058d35713
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The common AMD SMU code and the common AMD SMN access code that gets
selected by the common SMU code are valid for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic220dbb2f73b89554ac7e7b7e6dc7525ae8e9faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The common AMD FCH AOAC bit definitions and helper functions are correct
for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie791cca0dc760e53e0f5c69c63ac78270ba6ad4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Sabrina uses an identical I2C controller as Picasso and Cezanne. Also
both the type and version read-only register of the I2C controller
contain identical values.
The dma_cr, dma_tdlr, dma_rdlr and clr_restart_det registers that are
defined in the dw_i2c_regs struct in the common Designware I2C code
aren't defined in the PPRs of Picasso, Cezanne and Sabrina, but since
common DW I2C code doesn't access those, this is no problem.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I90732aa98518010686f73f80bee229b13e9bc89c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
I2C bus 0..2 on Sabrina uses a different pad type which supports 1.1V
and 1.8V levels, but doesn't support 3.3V I2C levels. Compared to the
existing I2C pad control registers the bit definitions are different, so
add a separate function to configure those pads which however still has
the same function signature and is compatible with same data structs
used for the devicetree settings. PPR #57243 Rev 1.50 was used as a
reference.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO for future improvements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
No mainboard in the current tree implements mainboard_i2c_override. In a
follow-up commit the i2c_pad_control struct is introduced to be able to
make more parameters controllable by devicetree settings in the future.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f9ed5d50d26e4623dc5888cc8af090fdd00fc03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61566
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It
doesn't control if port 80s are written. This flag also doesn't
currently control LPC init. The PSP is currently hard coded to remove
any LPC init.
BUG=b:215425753
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61534
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add platform_report_mode function which report current developer mode
status to the PSP. L1 widevine app in the PSP will use this information
to select key box.
BUG=b:211058864
TEST=build and boot guybrush
TEST=build picasso chrome os boards
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Using enum cb_err as return type instead of int improves the readability
of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Commit 86302a806c (soc/amd/{common,
cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE) added this Kconfig
option before the initial commit that added soc/amd/sabrina as copy of
soc/amd/cezanne landed in the tree, so port the change forward to
Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2e8df5e7b7f1ac0af772e8c565f616a68b28e29e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding mainboard design guide was used as a reference here.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The SMU message response register was moved compared to Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie384de52b1efb1d52f9018315a4b72916a4c9cee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The Sabrina SoC doesn't have the PM_ESPI_CS_USE_DATA2 bit defined in the
PM_SPI_PAD_PU_PD register. It also doesn't have a physical LPC interface
any more, so there are no LPC pins that can be reconfigured as eSPI
interface.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I02bc8d007901c71942475fe707637c5da7227230
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The CPPC feature isn't available on the Sabrina SoC, so drop the
corresponding code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71a1b0717571729ebca3600ac433e621cafc4e61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There are no SATA controllers on the Sabrina SoC. The UPD field will be
removed later as a part of the initial UPD header update.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iedefd9f150e5bcb78173288e5fc9f1bbd6b498cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Some of the names have slightly changed in the PPR, but I kept the
current names for consistency across all AMD SoCs in coreboot. Revision
1.50 of the PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6bda656015858a57e221b8d7819f944c21564a39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The data fabric ID table in PPR #57243 Rev 1.50 has a different IOMS0
fabric ID than Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32890b5c03219f6ebf8180929d71ef726d382483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Since we don't need to support PCI ID remapping for finding the correct
VBIOS binary for the integrated GPU, graphics.c can be dropped for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd5b678f472b3b5888353efd057203eb641be874
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Sabrina is family 17h model A0h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I01e02e3491fb90941c767058986da876bdf7ca1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Compared to Cezanne there are 3 more UART controllers. Revision 1.50 of
the PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I628b1a7a0930f3409acdcabda2b864d42bf6bd23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
The GPIO and GPIO MUX mapping as well as some GPIO to GEVENT mappings
have changed compared to Cezanne. Sabrina also doesn't have a remote
GPIO bank. Revision 1.50 of PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iabb85a3d24c881055e94400d08d01505df44a07a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Compared to Cezanne there are 3 more UARTs controllers. The PCI
interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't
contain a PIRQ mapping for UART4. The reference code has a mapping for
this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5.
Since the I2C5 controller isn't owned by the x86 side and I didn't see
any mapping of the I2C5 controller into the x86 MMIO space, this seems
very plausible. Also add the corresponding fields to the ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This code is common to at least all Zen-based APUs (Picasso, Cezanne,
Sabrina) and is also useful outside of the SoC-specific dynamic ACPI
table generation code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie96d4429fb6ed9223efed9b3c754e04052d7ca7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-by: Eric Peers <epeers@google.com>
The VERSTAGE region is only needed when running verstage in the x86.
This change reduces the early ram size by 512 KiB when using PSP
verstage.
BUG=none
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I45ce421397807dbb1eb48aedd05209b91e89aa4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The FSP gets these values from the UPD and sets the internal values.
The document about eDP tuning is attached in issue tracker of this
ticket, at the issue tracker b/203061533#comment6.
BUG=b:203061533
Cq-Depend: chrome-internal:4303901
Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Compared to Cezanne there are 3 more UARTs controllers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id98767197a21cb1a61f54fc9b256b10a9506c791
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Compared to Cezanne there are 3 more UARTs with DMA controllers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a3d255bb4976a55623f3a161e791e80f1d01c69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Let's increase this to avoid losing any logs.
BUG=b:213828947
TEST=Boot guybrush and no longer see
*** Pre-CBMEM romstage console overflowed, log truncated!
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3258145e352af3a75893c7cc96f36eb238c99abb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Replace the Renoir/Cezanne PCI IDs with the Sabrina ones that were added
in commit 27b02c2eee (include/device/
pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoC).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I427df6f8e8c08fb47ae8513b6cf1085d4294e28f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Document #55758 Rev. 1.13 says that family 17h models 30h-3Fh and later
use the spi_readmode_f17_mod_30_3f struct element for SPI_MODE_FIELD and
spi_fastspeed_f17_mod_30_3f for SPI_SPEED_FIELD, so also use this for
The AMD Sabrina SoC which is family 17h models A0h-AFh.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I336f9ea4a0defdf34e1af4b6d568cfe46488f75e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The Cezanne SoC code was initially started as a copy of example/min86
which only provides enough code to make the SoC code build. Then the
different parts of the real SoC support was brought in patch by patch
which also helped cleaning up and untangling the code. Since the Cezanne
SoC code is now in a rather good shape and the Sabrina SoC is similar to
the Cezanne SoC from the coreboot side, the new SoC support is started
with a copy of the Cezanne code and all the needed changes will be
applied on top of that. In order for the build not to fail due to
duplicate files, this patch does not only copy the directory, but also
replaces most instances of the Cezanne name with Sabrina. Since the
needed blobs aren't available in the 3rdparty/amd_blobs repository yet,
the Cezanne blobs are used for now so that the build will succeed. As
soon as the proper blobs will be available in that repository, the code
will be switched over to use them.
As suggested by Nico, I added a "TODO: Check if this is still correct"
comment to the beginning of every copied file and all SOC_AMD_COMMON_*
Kconfig option selects which will be removed after re-verifying that
each file and each selected common code block is still correct for the
new SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change splits the size of the console transfer region and size of
the bootblock/romstage Pre-RAM console region. This allows having a
larger Pre-RAM console while not impacting the size of the PSP verstage
console.
Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in
`setup_cbmem_console`, I chose to use the offsets provided in the
transfer buffer. It would be nice to eventually do this for all the
fields in the transfer buffer.
BUG=b:213828947
TEST=Boot guybrush and verify verstage logs are no longer truncated
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This implementation is the same for all SoC that select
SOC_AMD_COMMON_BLOCK_NONCAR, so factor it out to the common AMD non-CAR
CPU support code folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53528f0bb75e9d945740ad5065c75e7de7b5878f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61257
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
