Without RELOCATABLE_RAMSTAGE have WB cache large enough
to cover the greatest ramstage needs, as there is no benefit
of trying to accurately match the actual need. Choose
this to be bottom 16MiB.
With RELOCATABLE_RAMSTAGE write-back cache of low ram is
only useful for bottom 1MiB of RAM as a small part of this gets used
during SMP initialisation before proper MTRR setup.
Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
At the higher speeds stressapptest shows memory errors. We don't want
to track down random problems due to simple memory corruption, so slow
memory back down to 300 MHz until someone figures out how to make it
faster without sacrificing reliability.
BRANCH=None
BUG=chrome-os-partner:54144
TEST=stressapptest -M 1024 -s 240
Change-Id: I2417f93f65b1491a028a63ce563ed7dd7831becc
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I02182b25e677e27e8541445938f9da9ae9553fa6
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/350480
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15120
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
To support gpio power off SOC, we need to pass the power off
gpio parameter to BL31. Gru reuse tsadc overtemp pin as power
off gpio, so need to iomux to gpio function when use gpio power
off function, either in bl31 or depthcharge.
BRANCH=None
BUG=chrome-os-partner:53448
TEST=Build gru
Change-Id: Ibfe64042f39f6df1b87536b50fe432859bf74426
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: Ie7a1bbea4a12753f0abac7a9142f2e032686ce31
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349703
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15119
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
To support gpio reset SOC, we need to pass the reset gpio
parameter to BL31. Note: request BL31 have supported this
function.
BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru
Change-Id: I182cff11ce6f5dc3354db0dc053c128b813acf9f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I8283596565d552b1f3db31c28621a1601c226999
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349702
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15118
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
sometimes we need gpio number, so add this macro so we
can get the gpio number if we need.
BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru
Change-Id: I0c8c6cc0643a66e9ae1f21b02c7364c641b9805d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I98e8cf15543179904295a86e9f720c2d7c8b443a
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/349701
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15117
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Disabling ISH causes resets in FSP which leads to hang. This should be
fixed in a later stepping. Until then keep ISH enabled.
BUG=chrome-os-partner:54033
Change-Id: Id9cb276eed8d027ab6d2e81a5ec962bc730c1ff5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15142
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Instead of hard-coding the BIOS region start and end addresses, read
BIOS_BFPREG to determine the base and limit for the mapped BIOS
region.
BUG=chrome-os-partner:54563
Change-Id: Iddd3d4cc945f09e8f147e293bb9144471a6a220d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15269
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This makes it clearer that the read/write operations are being performed
on the host controllers registers.
Change-Id: Id63d778a4a03c461d97e535c34b85ada3ae469de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15281
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This allows initialization of runtime region devices and xlate region
devices where all parameters cannot be statically determined.
BUG=chrome-os-partner:54563
Change-Id: Ia6e1b695fed3bbfa08598d1593e650fc1465d41f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15267
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This makes the name consistent with other region device init macros.
Change-Id: I248894ba6c85326b615dcb71e8f498bc8be50911
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15277
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
spi_read_status reads the status register using hardware sequencing and
returns 0 on success and -1 on error. Use spi_read_status to return
appropriate value for get_sw_write_protect.
BUG=chrome-os-partner:54283
Change-Id: I7650b5c0ab05a8429c2b291f00d4672446d86e03
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15266
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
spi_init should be run early enough in ramstage so that any init
calls (e.g. mainboard_ec_init) that write on flash have right
permissions set.
Change-Id: I9cd3dc723387757951acd40449d4a41986836d2a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15235
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Bootblock:
- Temporary BAR needs to be assigned for SPI device until PCI
enumeration is done by ramstage which allocates a new BAR.
- Call spi_init to allow bootblock/verstage to write/erase on flash.
Ramstage:
- spi_init needs to run in ramstage to allow write protect to be
disabled for eventlog and NVRAM updates. This needs to be done pretty
early so that any init calls(e.g. mainboard_ec_init) writing to flash
work properly.
Verified with this change that there are no more flash write/erase
errors for ELOG/NVRAM.
BUG=chrome-os-partner:54283
Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15209
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.
For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific. The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.
Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.
And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.
Since these custom speed configs will come from devicetree a macro is
added to simplify the description:
register "i2c[4].speed_config" = "{
LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"
Which will result in the following speed config in \_SB.PCI0.I2C4:
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })
Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set CONFIG_GRUB2_EXTRA_MODULES from the Kconfig when building GRUB2.
This causes the specified modules to actually enter the built payload.
Change-Id: I345026af705ba8af77c6c12aba8e1bd4135e519c
Signed-off-by: Benjamin Barenblat <bbaren@google.com>
Reviewed-on: https://review.coreboot.org/15203
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
When doing make in util/cbfstool it contaminates the tree because it generates
the fmd_parser.
Change-Id: Ida855d1e57560c76d3fcfcc8e2f7f75bcdfdd5d4
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/15221
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Currently there are two sources for the final size of the
flash image. One is defined as a Kconfig variable
(ROM_SIZE) and the other can be provided in a user defined
flashmap.fmd. This patch will enable the usage of CONFIG_ROM_SIZE
in flashmap.fmd to define the flash size. In this way, the
Kconfig variable is the only source of information for the
flash image size. This way is optional.
Change-Id: Id5298e06d360aaa6d94f2b5a2ffa65e45919853e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15219
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
fmaptool generates a header file used to hardcode certain values from
the FMAP in coreboot's binaries, to avoid having to find and parse the
FMAP manually for every access. For the offset of the FMAP itself this
has already been using the absolute offset from the base of the whole
ROM, but for individual CBFS sections it only used the offset from the
immediate parent FMAP region. Since the code using it intentionally has
no knowledge of the whole section tree, this causes problems as soon as
the CBFS is a child section of something not at absolute offset 0 (as is
the case for most x86 Chromebooks).
Change-Id: If0c516083949fe5ac8cdae85e00a4461dcbdf853
Reported-by: Rolf Evers-Fischer <embedded24@evers-fischer.de>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15273
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch enlists ELAN trackpad on I2C4 for reef board.
BUG=None
TEST=Build and boot to OS.
Ensure ELAN trackpad is working with ELAN trackpad driver enabled
in kernel.
Change-Id: I788600f16dea9fac0e089cb82ccfc38a960157f9
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/15213
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
New structures and functions have been added to make it easier and
clearer to talk to GPIOs, configure the clock module, and toggle the
LEDs. Use that code in bootblock.c instead of doing those things
manually with hardcoded addresses.
Change-Id: If41db0220de4bc95a6c99945ec402e3026cb4eeb
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/3944
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
RAM doesn't need any initialization on qemu, so we can simply use it
right away. No need to try using the cache as ram in the first place.
We also can place the stack in normal ram right from start and we
don't have to switch it to another place later on. Place the stack
in real mode memory which isn't used for something else.
Change-Id: Ib7a3f58a846d139f7babea5f43722a30fe0fe962
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: https://review.coreboot.org/15214
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is where the RAM is (now), on RISC-V.
We need to put coreboot.rom in RAM because Spike (at the moment) only
supports loading code into the RAM, not into the boot ROM.
Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Variable name shadows parameter name used on other functions,
and it can be local anyway after function removal.
Change-Id: I3164b15b33d877fef139f48ab2091e60e3124c3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15240
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Not masking any bits in Operating System Capabilities, which means we
support all the capabilities that OS passed in Arg3
Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15021
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of programming unsupported CAS use the highest supported
value. Start at DDR3 maximum of CAS 18T.
Increase error message verbosity level.
Useful for overclocking.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
Allows to run a DDR3-1600 DIMM at 933Mhz.
Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15217
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Calculate the value from current DDR frequency.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15184
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Add Ramaxel DRAM manufacturer id.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
The manufacturer name shows up in dmidecode.
Change-Id: I14cdc82c09f0f990e2ba18083748d11d79e53874
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15183
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Set max_mem_clock_mhz in devicetree to 933Mhz.
Allows to run the memory at up to DDR3-1866.
The same frequency was allowed within the first vendor bios,
but Lenovo than decided to limit it to DDR3-1333.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
The RAM is now running at DDR3-1600 instead of DDR3-1333.
This gives about 4% performance increase in glmark2 using the
Intel GPU.
Change-Id: If15be497402d84a2778f0434b6381a64eda832d6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15158
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
CPU_MICROCODE_MULTIPLE_FILES relies on SUPPORT_CPU_MICROCODE_CBFS,
which is not set if CPU_MICROCODE_CBFS_NONE is set.
This makes selecting CPU_MICROCODE_MULTIPLE_FILES conditional.
Change-Id: I0c28f99a1b868bbf90a6f048cce3bea4ff849f76
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15259
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
It would not be possible to set MTRR for range 1MiB to 4MiB.
Our RAMTOP is power of 2 and enabling cache for bottom
1MiB should cause no problems.
Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15238
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Required EHCI state is maintained as a CAR_GLOBAL to have it
properly migrated.
Change-Id: I8df413bec6faae4952670710c8ac804e0331c966
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15236
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Kyösti Mälkki