Commit Graph

30400 Commits

Author SHA1 Message Date
Patrick Georgi de2b6b8349 Documentation: minor grammar fixes
Change-Id: Iff6df888a293b525d436a5be215e8972ae2dd46a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-16 21:17:14 +00:00
Elyes HAOUAS dd12d53494 3rdparty/chromeec: Update to latest master
It's been some time and there are 1420 new commits. Including one that
allows reproducible builds \o/ and one that breaks building with empty
$(CC) :-/

Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30679
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16 13:42:10 +00:00
Felix Singer 07734c91d5 mb/up/squared: Do RAM config based on SKU ID
TESTED=UP Squared

Change-Id: Ic121652213d5b1f65cff2f3096e919a3cf88db72
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34838
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16 07:30:41 +00:00
Sridhar Siricilla d415c206b5 src/soc/intel/{common,cnl,skl,icl}: Move global reset req function to common
send_heci_reset_req_message() is defined in multiple places,
hence move it to common code.

TEST=Verified on CMLRVP/Hatch/Soraka/Bobba/Dragon Egg boards.

Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35228
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16 07:29:36 +00:00
Elyes HAOUAS 198f427907 src/mainboard: Remove unused include <device/pci_ops.h>
Change-Id: Icdbccb3af294dd97ba1835f034669198094a3661
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33528
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-16 07:29:18 +00:00
kenny liang 416be81068 mediatek/mt8183: Add soc ARM Trusted Firmware support
Set BL31 platform to mt8183 to link with ARM Trusted Firmware.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui with more patches in ATF.

Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-16 07:26:37 +00:00
Seunghwan Kim c773b6c896 mb/google/kohaku: Update USB port settings
This change overrides USB port settings for kohaku.

Some port settings are same with baseboard, but I'd like to describe all
settings here to be aware of current setting and usage of USB ports on
kohaku.

BUG=none
BRANCH=none
TEST=built and measured SI of USB ports internally

Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-16 05:29:35 +00:00
Arthur Heymans 2e1427b6a7 mb/packardbell/ms2290: Use common SB code to set up GPIO's
Change-Id: I6658c53213127db5a46f2ea330d85a3a537c3276
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-15 20:57:09 +00:00
Michael Niewöhner a1ef94e822 soc/intel/skylake: add some FSP SATA params
This adds SATA parameters for SpinUp, HotPlug and TestMode to the
Skylake FSP 2.0 interface.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I7ba67879b78c2cb0fd0b0ce832140b213edd5884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35186
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 20:56:24 +00:00
Arthur Heymans 5ea2e405da mb/*/{x201,ms2290}/mainboard.c: Remove superfluous ramstage code
Change-Id: I0270c50dea2a2ce6c8e6114ed708f06be9d33c0e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-15 20:55:28 +00:00
Rizwan Qureshi 279d8b5f3d cpu/intel/microcode: Make microcode lib available in bootblock
Make microcode lib available in bootblock. Now that microcode.c is compiled
in bootlock no need to include it explicitly, hence remove its references.

Change-Id: I419da6af70222902e3ca39fc2133d5dc8558e053
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35278
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 20:45:21 +00:00
Alexander Couzens 49ca968b0b payloads/LinuxBoot: move kernel make flags into own variable
Change-Id: I9240043d2c15b68aabe154b289a961d8d48d3e5f
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-15 20:44:16 +00:00
Elyes HAOUAS 10348399a6 {i945,i82801gx}: Remove unneeded include <cpu/x86/cache.h>
Change-Id: I4f38be28d81c0c01c0389210552232e63ea55545
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34934
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 20:42:34 +00:00
Elyes HAOUAS 087504f142 src/security: Remove unused #include <fmap.h>
Change-Id: I9db59d5db2ed3e792251a94b67fb277d9160e4e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33734
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 20:42:15 +00:00
Elyes HAOUAS 1cd8703b3f southbridge: Remove unused include <device/pci_ops.h>
Change-Id: I8578cf365addc47550e27c9ebed08de340d70ede
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33531
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 20:41:46 +00:00
Elyes HAOUAS e1f8db9adb src/soc: Remove unused include <device/pci_ops.h>
Change-Id: I80c92f744fb9a6c3788b8b9ba779deef76e58943
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33530
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 20:40:52 +00:00
Elyes HAOUAS deda9c0f8a northbridge: Remove unused include <device/pci_ops.h>
Change-Id: Ib60305948ac1d3464586fe69501bd28eecb761ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33529
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 20:39:59 +00:00
Elyes HAOUAS 02381a2ca0 {cpu,device,drivers}: Remove unused include <device/pci_ops.h>
Change-Id: I68da75e3afa2f66aff9961728d4a76bc3e175fce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33527
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 20:38:45 +00:00
Elyes HAOUAS 4655d041cd src/mainboard: Remove not used #include <elog.h>
Change-Id: I901cb35488e08f58cdf97f3a8d0f5a8d03560f86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33729
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 20:35:34 +00:00
Elyes HAOUAS 1e3d16e8d1 nb/i945: Remove unused include <cpu/cpu.h>
Change-Id: I5dff9b7c157b2aba596e95b5fb18a84f7c4e9365
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-15 20:35:14 +00:00
Sellerie 409a5dc8af util/inteltool: Add Intel HD 4400 (Haswell IGD)
Add the 8086:041e integrated graphics controller.
Adding the definition makes the Intel HD 4400 graphics
recognized by inteltool.

It is found on the ark page of e.g. the Intel i3-4130 CPU.

Change-Id: I6d6b2eaa7cc5aa3912592ed3fcb73751b224eede
Signed-off-by: Christoph Pomaska <sellerie@aufmachen.jetzt>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34588
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 17:18:22 +00:00
Johanna Schander c544a85d2a lib/coreboot_table: Show splashscreen in lb_table_init
Every vga init implementation needs to cache the framebuffer state
to be able to fill the lb_framebuffer struct later on in the
fill_lb_framebuffer call. Showing the bootsplash afterwards
guarantees to have the same interface into all the vga drivers.

This is by far from ideal, as it only allows for a single driver at
compile-time and should be adapted in the future.

It was tested on the wip razer blade stealth using vgabios @ 1280x1024
and also in Qemu @ 1280x1024.
By default the qemu framebuffer will be initialized in 800x600@32.
This can be overwriten by configuration by setting
CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_{X,Y}RES .

Change-Id: I4bec06d22423627e8f429c4b47e0dc9920f1464e
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-15 11:10:58 +00:00
Marshall Dawson bfb0c2d543 soc/amd/common: Remove Picasso display HDA from list
The PCO_HDA0 device contains the "ATI" vendor ID 0x1002 and was
incorrectly added to this file.  It isn't anticipated that the
device will need special handling, so remove it from the list
of supported IDs.

Change-Id: I306a806dc510e3a4ee3d9c0663306dc93b1d936d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-15 01:18:32 +00:00
Kyösti Mälkki e3acc8fcf3 src/: Replace some __PRE_RAM__ use
Change-Id: Iaa56e7b98aad33eeb876edd7465c56c80fd1ac18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-14 11:16:17 +00:00
Kyösti Mälkki 4a637802fa ec/acpi: Replace __PRE_RAM__ use
Change-Id: Iae31569f16168ba00ce272e4777f3a69bcd6ee94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-14 10:57:28 +00:00
Kyösti Mälkki 505e3f7e85 arch/x86: Replace some __PRE_RAM__ use
Change-Id: I4d8db430f8cd0bf0f161fc5cef052f153e59e2bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35390
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14 10:56:46 +00:00
Kyösti Mälkki cf49dec4de cpu/x86: Drop lapic_remote_read()
Unused and declaration conflicts with the one
amdfam10-15 uses in romstage.

Change-Id: Icd454431285b7c423a4f78d2a0085497d052adc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35394
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14 10:55:55 +00:00
Kyösti Mälkki 2491d790d2 arch/x86: Remove acpi_fail_wakeup() and cbmem_fail_resume()
Unused since commit d46b8d5.

Change-Id: If0f1e0381dd7698f842dc1288ff222a4d5d4783c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35389
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14 10:55:34 +00:00
Maxim Polyakov 66d875a143 mb/asrock/h110m: configure SuperIO global registers
Information based on superiotool dump.

Change-Id: I24ae9b1a7eab3095518341354544efe613912a6a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-14 05:48:22 +00:00
Maxim Polyakov 15b0ab51b9 mb/asrock/h110m: configure GPIOs in SuperIO chip
Enables and configures GPIOs in the NCT6791D chip. The values for
registers taken from the superiotool dump.

Change-Id: I5968a6c20cc013697d64bfbe4fc2e7b2390b72b0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-14 05:47:59 +00:00
Maxim Polyakov afd7ce680b mb/asrock/h110m: enable ACPI LDN in SuperIO
Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-14 05:47:18 +00:00
Maxim Polyakov 7d549f8908 mb/asrock/h110m: set I/O Range for SuperIO HWM
Change-Id: I30de4f40f8ca87c54faee84053c4bb0f874b2884
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35369
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-14 05:46:54 +00:00
Julius Werner b3f24b4884 arm64: Uprev Arm TF and adjust to BL31 parameter changes
This patch uprevs the Arm Trusted Firmware submodule to the new upstream
master (commit 42cdeb930).

Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff
parameters across platforms which involved changing a few names around.
This patch syncs coreboot back up with that. They also made header
changes that now allow us to directly include all the headers we need
(in a safer and cleaner way than before), so we can get rid of some
structure definitions that were duplicated. Since the version of entry
point info parameters we have been using has been deprecated in Trusted
Firmware, this patch switches to the new version 2 parameter format.

NOTE: This may or may not stop Cavium from booting with the current
pinned Trusted Firmware blob. Cavium maintainers are still evaluating
whether to fix that later or drop the platform entirely.

Tested on GOOGLE_KEVIN (rk3399).

Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-14 05:01:16 +00:00
Kyösti Mälkki 8b93689a35 timestamps: Remove TIMESTAMP_CACHE_IN_BSS
This was implemented for LATE_CBMEM_INIT support which
has already been deprecated.

Change-Id: I39225ba675bc3389e051e15b400a905431969715
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35375
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:48:26 +00:00
Kyösti Mälkki b6b13c9f29 timestamps: Further simplify timestamp_reinit()
Allocation of new table always happens in romstage.

Change-Id: I089a84b372893fb3018a796fb1e16cd58753bdf4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35374
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:47:58 +00:00
Kyösti Mälkki b2536f418f drivers/pc80: Remove some __PRE_RAM__ and __SMM__
Change-Id: Ic90df69c27d524086405238b9683a69771c1b9d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35388
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:29:46 +00:00
Kyösti Mälkki b590a04f78 security/vboot: Replace use of __PRE_RAM__
Change-Id: Ibaeda2762c733fdbe48979b635cc0cfd7ee4295d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35387
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:29:18 +00:00
Kyösti Mälkki 55d0ab5dc4 intel/broadwell: Replace some __PRE_RAM__ use
Guards are required due to different PCI accessor
signatures.

Change-Id: I60e87f16a48565917f6ee9d05cc59d2b9373270c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35381
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:28:53 +00:00
Kyösti Mälkki 80f963ccd5 intel/haswell: Remove some __PRE_RAM__ use
Change-Id: I167e9a171af4fe7997ebb76cdfa22a4578817a55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35380
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:28:36 +00:00
Kyösti Mälkki e9dcc7a3c5 soc/intel: Remove some __PRE_RAM__ use
Change-Id: I35b44967de4e8d9907dc887fe35407bcaf334adc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35379
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 19:28:19 +00:00
Peichao Wang fd15c99f4e mb/google/hatch: Merge emmc_sku_gpio_table and gpio_table to one table
BUG=b:140008849, b:140573677
TEST=verify eMMC SKU and SSD SKU will bring up normally.

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I0c0adf569cc92e8b44ab72379420f2b190fa31f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-09-13 18:05:54 +00:00
Himanshu Sahdev 20667c59d8 emulation/qemu-i440fx/fw_cfg_if.h: replace macro with enum
replace multiple existing FW_CFG_* defines with enum fw_cfg_enum.

Change-Id: I9699df4aeb2d8b18f933bb9aaed16008d10158ad
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-13 17:52:05 +00:00
Marshall Dawson 71dbcf127a drivers/intel/fsp2_0: Allocate cfg_region_size for UPD
In FSP-S, the driver constructs its pointer to UPD using the offset
in the header.  Similarly, use the header's cfg_region_size for
allocating memory and copying the default configuration.

Add sanity checks for unexpedted configuration and UPD header
conditions.

TEST=Verify OK on Mandolin, verify a mock error condition
BUG=b:140648081

Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13 09:59:56 +00:00
Himanshu Sahdev aka CunningLearner 2b84008ed9 arch/x86/bootblock_crt0.S: Leverage eax in protected mode entry
Leverage already used eax register in bootblock_protected_mode_entry.
Avoid another register ebx just for preserving eax value as it is not
needed and is not used at all after moving the value into mm0.
Allow EBX to be preserved for other usage.

Change-Id: Ia668b78f2f97cf026692f1fe63ff8a382a162474
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35292
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 09:59:17 +00:00
Kyösti Mälkki 7f50afb0c7 drivers/elog: Add elog_boot_notify()
Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13 09:58:33 +00:00
Kyösti Mälkki 2cce24dd4b intel/nehalem: Refactor ACPI S3 detection
Change-Id: Ib405f3c3a6143e972963307eef7371dd43b9b5fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-13 09:58:18 +00:00
Kyösti Mälkki 216db613a7 intel/fsp2_0: Move TS_BEFORE_INITRAM
Exclude FSP-M loading from the timestamps used for
RAM detection and training process.

Change-Id: I859b292f2347c6f0e3e41555ad4fb8d95a139007
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-13 09:57:25 +00:00
Selma BENSAID cfcf3c584f mb/google/drallion: Use arcada_ish.bin for arcada_cml
drallion_ish.bin is updated for drallion GPIO changes
and not compatible with arcada_cml.

TEST=Build and boot arcada_cml

Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-13 09:57:12 +00:00
Bora Guvendik 349b6a1152 soc/intel/cannonlake: Allow coreboot to reserve stack for fsp
FSP BIOS 212 / 07.00.6C.40 for CNL/WHL supports FSP to use coreboot stack.
This change selects common stack config, that enables coreboot to support
share stack with FSP.

TEST=Boot to OS on WHL platform

Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-09-13 09:56:54 +00:00
Philip Chen 48427512d6 mb/google/hatch/var: Increase Goodix touchscreen reset delay to 500ms
Even though GT7375P programming guide rev0.4 only requires a reset delay
of 120ms, in practice, we have to increase the reset delay to 500ms, or
Goodix FW update would fail.

This is a workaround. In the long run, we hope Goodix can fix the power
sequence in touch firmware.

BUG=b:138795891, b:138796844
TEST=boot helios board and verify Goodix FW update succeeded

Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-13 03:12:31 +00:00