Commit Graph

9833 Commits

Author SHA1 Message Date
Edward O'Callaghan c814be4158 amd/agesa/s3_resume: Make compiler agnostic.
Clang does not like inline functions defined in C files with prototypes
in headers. Rather Clang expects inline function bodies to be in headers
if they are to be used out of scope. Since inline is purely advisory to
the compiler, drop its usage here.

Change-Id: I08a7a3d2cdf841ffbab10c017c75917768aac209
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5429
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-03 10:00:52 +02:00
Aaron Durbin ab180d85f7 util/cbmem: handle larger than 1MiB mappings for console
In some cases the cbmem console can be larger than the default
mapping size of 1MiB. Therefore, add the ability to do a mapping
that is larger than the default mapping using map_memory_size().
The console printing code will unconditionally map the console based
on the size it finds in the cbmem entry.

Change-Id: I016420576b9523ce81195160ae86ad16952b761c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5440
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 17:01:01 +02:00
Edward O'Callaghan a270586d4b superio/fintek/f71859: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: I3577ca3f761fb699dc51141a02e1f853bf1f1a21
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5417
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:08:32 +02:00
Edward O'Callaghan b5a49ad9d7 superio/fintek/f71889: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: Id8a1a2e8c87add636af1506598c2669d72dc3238
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5437
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:08:19 +02:00
Edward O'Callaghan 880e5248dc superio/fintek/f71872: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: Ia021229154dc90b830a314f3adc2a0dd444bd68d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5436
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:08:09 +02:00
Edward O'Callaghan ade70a0482 superio/fintek/f71863fg: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: I863c16634873224c17e43100271e9b91419724d0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5435
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:07:57 +02:00
Edward O'Callaghan fbdc3ef7d9 superio/fintek/f71805f: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5434
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:07:27 +02:00
Aaron Durbin 905bfb05dc x86: use car_(get|set)_var accessors for apic timer
The timer_fsb variable was not correctly being accessed in the
presence of cache-as-ram. The cache-as-ram backing store could
be torn down but then udelay() could be called causing hangs from
accessing variables that have unknown values.

Instead change the timer_fsb variable to g_timer_fsb and obtain
the value through a local access method that does the correct things
to obtain the correct value.

Change-Id: Ia3e30808498cbe4a7f6f116c17a8cf1240a807a3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5411
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-01 14:31:36 +02:00
Kyösti Mälkki deb2cb27e9 Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATE
Use of CAR_GLOBAL is not safe after CAR is torn down, unless the
board properly implements EARLY_CBMEM_INIT.

Flag vulnerable boards that only do cbmem_recovery() in romstage on S3
resume and implementation with Intel FSP that invalidates cache before
we have a chance to copy the contents.

Change-Id: Iecd10dee9b73ab3f1f66826950fa0945675ff39f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5419
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-01 11:36:00 +02:00
Patrick Georgi 0ec3f493a3 git-ignore site-local
It's _local_

Change-Id: I5624e240ffe486763b25b14b218e69362c488f50
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5432
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-01 08:55:02 +02:00
Edward O'Callaghan d3043313a9 superio/fintek/f81865f: Avoid .c includes
We should not be #include .c files, instead link early_serial into
romstage and provide a prototype.

Change-Id: Ia9277169ce1592e1fc72f8849f0982741daec567
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5416
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-31 01:05:40 +02:00
Alexandru Gagniuc 01c44000be cubieboard: Enable the SD controller and mux SD pins
This step needs to be done before calling any MMC functionality.

Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4745
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-03-29 22:28:44 +01:00
Alexandru Gagniuc fccfee3bce mainboard/hp: Add initial support for Pavilion m6-1035dx
This was a pathetically easy port, where all the components are
already supported. This is basically a verbatim copy of amd/parmer.
The EC is an ENE KB932, which is a part that does surprisingly little
for an EC. This also means we need almost no code to get it working.
I've "select"ed the EC in Kconfig, which is the only difference from
parmer, although the keyboard worked fine without it.

I haven't coupled in the ACPI code from the EC yet, so battery level
is not readable from the OS. Hotkeys work except for brightness
control, and the CapsLock LED blinks at regular intervals instead of
following the CapsLock key.

Change-Id: Idfec6f848b99a52e73eac22d516f3550477ad822
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5409
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-28 20:59:57 +01:00
Paul Menzel 35a4901d3a mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`
It's not needed and causes build failures without CONFIG_CHROMEOS.

Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd
Reported-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5398
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-28 19:28:31 +01:00
Aaron Durbin 4f3bb801ed cbfstool: provide structure to linux payload builder
This change started with tracking down a bug where the trampoline
size was not being taken into account for sizing the output buffer
leading to a heap corruption.  I was having a hard time keeping
track of what num_segments actually tracked as well as what parts
were being placed in the output buffer. Here's my attempt at
hopefully providing more clarity.

This change doesn't crash when adding a bzImage:
$ dd if=/dev/zero of=bb.bin bs=64 count=1
$ ./cbfstool tmp.rom create -s 4M -B bb.bin -m x86 -a 64
$ ./cbfstool tmp.rom add-payload -f ~/Downloads/bzImage -C "1" -n
"fallback"/payload

Change-Id: Ib1de1ddfec3c7102facffc5815c52b340fcdc628
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5408
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-28 14:40:53 +01:00
Wilbert Duijvenvoorde 2164831671 util/superiotool: Add initial support for Fintek F71869ED.
Datasheet: http://www.fintek.com.tw/files/productfiles/F71869_V1.1.pdf
Practically the same as F71869AD, just another ID (0x1408).
Tested on actual hardware, Jetway NC9C-550-LF.

Update:
Fixed F71869ED based on the proper datasheet:
http://www.alldatasheet.com/datasheet-pdf/pdf/459075/FINTEK/F71869ED.html

Change-Id: I5da858565ca16ba4d73b47b42fadd31dabbc290b
Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com>
Reviewed-on: http://review.coreboot.org/5380
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-03-27 10:15:28 +01:00
Edward O'Callaghan 024822f26d mainboard/jetway/nf81-t56n-lf: Enable ACPI S3 support in Kconfig
Switch on ACPI suspend/resume support which now works after many cycles.

Change-Id: I94a9bc9f23c2b4482d940018d542ab89e6c76f09
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5406
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-03-26 13:15:13 +01:00
Wilbert Duijvenvoorde ffdf2e1acf util/superiotool: Register fix for Fintek F71869AD
Fixed F71869AD based on the proper datasheet:
http://www.alldatasheet.com/datasheet-pdf/pdf/459074/FINTEK/F71869AD.html

Change-Id: If22341551c6a1a9bbae088801a6194f7b5b6bf4d
Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com>
Reviewed-on: http://review.coreboot.org/5405
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-24 23:44:52 +01:00
Edward O'Callaghan 1547ef2362 mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cb
Change-Id: Ia58994d14ebf488a9200b02ec7af9c71ef4de9e6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5401
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-24 07:10:55 +01:00
Aaron Durbin 3eb8eb7eba rmodules: use rmodtool to create rmodules
Start using the rmodtool for generating rmodules.
rmodule_link() has been changed to create 2 rules:
one for the passed in <name>, the other for creating
<name>.rmod which is an ELF file in the format of
an rmodule.

Since the header is not compiled and linked together
with an rmodule there needs to be a way of marking
which symbol is the entry point. __rmodule_entry is
the symbol used for knowing the entry point. There
was a little churn in SMM modules to ensure an
rmodule entry point symbol takes a single argument.

Change-Id: Ie452ed866f6596bf13f137f5b832faa39f48d26e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5379
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-03-20 23:55:55 +01:00
Aaron Durbin 4fde5a66b4 util: add rmodtool for parsing ELF files to rmodules
The current implementation of creating rmodules relies
on invoking the linker in a certain manner with the
relocations overlaid on the BSS section. It's not really
surprising that the linker doesn't always behave the way
one wants depending on the linker used and the architecture.
Instead, introduce rmodtool which takes an ELF file as an
input, parses it, and creates a new ELF file in the format
the rmodule loader expects.

Change-Id: I31ac2d327d450ef841c3a7d9740b787278382bef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5378
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-03-20 21:34:39 +01:00
Aaron Durbin 36be8135d7 cbfstool: add ELF writing support
In order to generate rmodules in the format of ELF files
there needs to be support for writing out ELF files. The
ELF writer is fairly simple. It accpets sections that can
be associated with an optional buffer (file data). For each
section flagged with SHF_ALLOC a PT_LOAD segment is generated.
There isn't smart merging of the sections into a single PT_LOAD
segment.

Change-Id: I4d1a11f2e65be2369fb3f8bff350cbb28e14c89d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5377
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-18 18:59:25 +01:00
Edward O'Callaghan 8089f17806 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: If8c53b5370be9101b9e5f2dfa88a6229f500a0f6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5392
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-17 19:14:30 +01:00
Edward O'Callaghan 38608937b6 romcc.c: Fixes warning about unused function from unused macros.
GCC suppresses warnings about unused static functions if they are
inline, however Clang only does this for header files. None of these
MASK_ declarations are used, so just remove them.

Change-Id: Ia230beba3f6367237838d9b3d90536459e1d52cb
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5273
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-17 19:09:49 +01:00
Idwer Vollering 5809a7395d Make POST device configurable.
Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4561
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-16 21:42:49 +01:00
Aaron Durbin c078094f39 cbfstool: add symbol table parsing to the ELF parser
Optionally parse the symbol table contained within an ELF
file. It currently assumes there is only one symbol table present,
and it errors out if more than one is found.

Change-Id: I4ac4ad03184a319562576d8ab24fa620e701672a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5376
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14 21:51:38 +01:00
Aaron Durbin c3e6e14a12 cbfstool: add string table parsing to ELF parser
Optionally parse the string tables within an ELF file.

Change-Id: I89f9da50b4fcf1fed7ac44f00c60b495c35555ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5375
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14 21:51:27 +01:00
Aaron Durbin ccb5ad8d3c cbfstool: add relocation parsing to ELF parser
Optionally parse the relocation entries found within an ELF
file.

Change-Id: I343647f104901eb8a6a997ddf44aa5d36c31b44b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5374
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14 21:51:14 +01:00
Aaron Durbin d0f6165923 cbfstool: introduce struct parsed_elf and parse_elf()
In order to make the ELF parsing more flexible introduce
a parse_elf() function which takes a struct parsed_elf
parameter. In addition take a flags parameter which instructs
the ELF parser as to what data within the ELF file should be
parsed.

Change-Id: I3e30e84bf8043c3df96a6ab56cd077eef2632173
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5373
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14 21:50:42 +01:00
Aaron Durbin 19a11d6fe9 cbfstool: remove incorrect section size check
I was overzealous in checking the section size with respect
to the file size. That check makes no sense as the section only
deals with link sizes -- not on-disk sizes. Remove the check as
it doesn't make any sense.

Change-Id: I348e7847ae3a50badc22693439614f813462445a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5384
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 23:02:46 +01:00
Edward O'Callaghan ed2bcaa731 mainboard/jetway/nf81-t56n-lf: Fix HWM base addr.
The target board has a different base addr. for its hardware
monitor (fans, temp, etc) from the Fintek Super I/O datasheet.

Change-Id: Ifc025cb92d0fc4e8f813091d00a6c87deae05863
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5383
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13 20:25:44 +01:00
Edward O'Callaghan 236cf47513 mainboard/jetway/nf81-t56n-lf: Remove hard-coded IMC fan craft.
Fan controls in 0x400-0x4ff are not programmed here. Thus fan
control from amd/persimmon in the devicetree.cb does not apply
to this board.

Change-Id: I9156143476df0a7b44c7af90fa2107e8a8ba851e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5381
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13 20:25:22 +01:00
Aaron Durbin a31ff73e8d cbfstool: elfparsing: check segment and section regions
While parsing the section and program headers ensure the
locations of their contents are within the elf file proper.

Change-Id: I856f7de45f82ac15977abc06e51bedb51c58dde1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5372
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:31:49 +01:00
Aaron Durbin b1b5118c71 cbfstool: elfheaders: use proper parameters to calloc()
Though the result doesn't matter much, the callers of calloc()
should order the parameters correctly. i.e. the first paramter
is the number of elements in an array and the second is the
size of each element.

Change-Id: Ic7c2910d623d96f380feb4e5f6fa432376f49e9b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5371
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:28:57 +01:00
Aaron Durbin 54ef306377 cbfstool: add eflparsing.h
elfparsing.h serves as the header to working with the elf
parser. Additionally, only include what is needed by the other
files. Many had no reason to be including elf.h aside from fixing
compilation problems when including cbfs.h.

Change-Id: I9eb5f09f3122aa18beeca52d2e4dc2102d70fb9d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5370
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:28:44 +01:00
Aaron Durbin aa8784c2d1 cbfstool: move iself() to eflheaders.c
The only user of iself() was in elfheaders.c. Move it there,
and make it local to the compilation unit.

Change-Id: I0d919ce372f6e2fce75885fb4fcba20d985979b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5369
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:28:07 +01:00
Aaron Durbin a983cea5b9 cbfstool: elfheaders: use common checks and buffer helpers
The elfheaders code was manipulating struct buffers. Use
the introduced buffer helper functions. Additionally fix
up offset and size checks for the program headers and section
headers by using common code paths.

Change-Id: I279c77f77aaa1860a0be43fb111df890dd1d84d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5368
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13 05:27:54 +01:00
Alexandru Gagniuc 0c54bfa0ee Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs"
This reverts commit b845636ce6.
This commit changed the board status script to describe all boards in
terms of x86 terminology, such as CPU->southbridge->northbridge.

This terminology does not apply to a number of SoCs, in which the
buses are not connected via successive bridges, and as such it is
misleading and misguided to describe ideas of southbridge and
northbridge for these devices.

Change-Id: I98ba24ee00b816bf20d507c6d313ec2946acaedf
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5177
Tested-by: build bot (Jenkins)
2014-03-12 16:37:41 +01:00
Chris Douglass b34739b4b0 drivers/spi: Add support for adesto SPI flash parts
Adds support for the following Adesto Technologies
SPI Flash parts.

AT25DF081
AT25DF321
AT25DF641

It has been tested on an Orion VPX7654 board populated
with an AT25DF321A part. The "08" and "64" densities have not
been tested.

These parts are the successors of the Atmel AT26DF line that
was spun out or purchased by Adesto.

In this patch, adesto.c is identical to winbond.c with part
entries for the Adesto parts. The datasheet for the AT25DF parts
includes a "100MHz" programming command in addition to the "85MHz"
command that is currently used but this patch does not add support
for that enhanced programming mode.

Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5225
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-12 01:03:31 +01:00
Aaron Durbin 06ece7de93 chromeos: provide option to dynamically allocate ram oops buffer
Fixing the location of the ram oops buffer can lead to certain
kernel and boot loaders being confused when there is a ram
reservation low in the address space. Alternatively provide
a mechanism to allocate the ram oops buffer in cbmem. As cbmem
is usually high in the address space it avoids low reservation
confusion.

The patch uncondtionally provides a GOOG9999 ACPI device with
a single memory resource describing the memory region used for
the ramoops region.

BUG=None
BRANCH=baytrail,haswell
TEST=Built and booted with and w/o dynamic ram oops. With
     the corresponding kernel change things behave correctly.

Change-Id: Ide2bb4434768c9f9b90e125adae4324cb1d2d073
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5257
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 21:37:36 +01:00
Duncan Laurie e7e78d61a9 baytrail: Reserve memory between ASEG and 1MB and for ramoops
Low system tables are in this region, and it is probably safer
to keep ASEG reserved.

Also keep the region used by ramoops from being used by the OS
and from being cleared by developer mode boots.

Lots more work needed to make the ACPI tables fully functional.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=boot on rambi and see that the kernel finds RSDP and uses ACPI

Change-Id: I4f7064d3cff14a3ecf15b194a1f20c1fa9d5e134
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4932
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-11 19:56:17 +01:00
Duncan Laurie 714b1e8b6c rambi: Enable USB boot with EHCI controller
This adds the EHCI driver back to libpayload and configures
the devicetree to route ports to EHCI.

This is hopefully just temporary until the issues with XHCI
can be worked out.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi

Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175513
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4931
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:55:58 +01:00
Duncan Laurie 3c9f17462a baytrail: Add EHCI initialization
This adds required steps to initialize the EHCI controller
on the baytrail platform.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi

Change-Id: I3a5487791e2305616036d4550e260a178c0e1c4d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175512
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4930
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:55:30 +01:00
Duncan Laurie f81a91a768 baytrail: Add XHCI initialization
This adds required steps to initialize the XHCI controller
on the baytrail platform.

Actually using XHCI is causing lots of bad behavior including
apparent memory corruption.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Ic43e04f4b47e107ec3bb0c387a9fc72c3cae0271
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175511
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4929
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:55:12 +01:00
Aaron Durbin 97651c55a3 baytrail: add audio clock workaround for LPE
Apparently the LPE device needs a 25MHz clock. Provide
the work around to enable this clock.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Confirmed setting being applied.

Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175493
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4928
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:54:58 +01:00
Aaron Durbin 65ad521f8a baytrail: add ccu iosf access functions
The clock control unit needs to be accessed to configure
some of the devices properly. Therefore. provide a way
to access the CCU.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built.

Change-Id: I30ed06e6aef81ee99c6d7ab3cbe8f83818b8dee5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175492
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4927
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:54:04 +01:00
Aaron Durbin 46ab8cdc68 baytrail: HDA function disable workaround
Parts of the audio path are common between the HDA and LPE.
However, those parts are power-controlled by the D-state of
the HDA device. Therefore, one cannot put the HDA into D3Hot
because those audio paths will be shutdown.

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Disabling HDA still
     causes a shutdown when performing warm reset, however I
     was able to verify the magic sequence was being performed.

Change-Id: I3b01356d85a4b7b902bd896b8eb9e7bc509fcc42
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175491
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4926
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:53:51 +01:00
Aaron Durbin 1eae3eed29 baytrail: allow function disable on TXE
Previously it was not known how to put the TXE pci device
into D3Hot. It's been disseminated that this is not a requirement
for disabling the TXE pci device in the function disable register.
Therefore, allow this by returning 0 from place_device_in_d3hot().

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Temporarily set TXE to be disabled. Noted FUNC_DIS was being
     set accordingly.

Change-Id: Ibf537bf8ba718859591dc89bdf41e57c1ea9d836
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175490
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4925
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:53:17 +01:00
Duncan Laurie 223d4a4ff6 baytrail: Switch graphics init to use reg_script
This is an example consumer of the register script handler.

BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=build and boot on rambi and see recovery screen

Change-Id: I4954a5defd0a345b179819b9f6bb15ea340a6715
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175214
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4924
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:52:06 +01:00
Aaron Durbin 6e8c2790bb cbfstool: add struct buffer helper routines
There are some open-coded manipulation of the struct buffer
innards in the elf parsing code. Add helper functions to avoid
reaching into the struct itself.

Change-Id: I0d5300afa1a3549f87f588f976184e880d071682
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5367
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11 19:46:45 +01:00