Commit Graph

44287 Commits

Author SHA1 Message Date
Subrata Banik 78e66ad63b soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS
`heci_finalize` ensures to put all heci devices to D3 by setting the
D0i3 bit prior to booting to the OS.

BUG=b:200644229
TEST=Verified D0i3 bit is set for all HECI devices prior to booting
to OS.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-06 19:04:56 +00:00
Subrata Banik 3710e9972b soc/intel/common: Helper function to check CSE device `devfn` status
This patch creates a helper function in cse common code block to check
the status of any CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and
CSE_4.

Currently cse common code is only able to read the device state of
`PCH_DEVFN_CSE` CSE device alone.

Additionally, print `slot` and 'func' number of CSE devices in case
the device is either disable or hidden.

BUG=b:200644229
TEST=Able to build and boot ADLRVP-P with this patch where the serial
message listed the CSE devices that are disabled in the device tree
as below:

HECI: CSE device 16.01 is disabled
HECI: CSE device 16.04 is disabled
HECI: CSE device 16.05 is disabled

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-06 19:03:55 +00:00
Subrata Banik c6e2552ce6 soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devices
This patch ensures to pass cse device function number as argument for
`set_cse_device_state()` to allow coreboot to perform enable/disable of
D0i3 bit for all CSE devices to put the CSE device to Idle state or
Active state.

BUG=b:200644229
TEST= Able to build and boot ADLRVP where `set_cse_device_state()` is
able to put the CSE device toidle state or active state based on `devfn`
as argument.

Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-06 19:03:31 +00:00
Raul E Rangel db16ac9578 lib/thread: Remove thread stack alignment requirement
CPU_INFO_V2 now encapsulates the cpu_info requirements. They no longer
need to leak through to thread.c. This allows us to remove the alignment
requirement.

BUG=b:179699789
TEST=Reboot stress test guybrush 50 times.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0af91feddcbd93b7f7d0f17009034bd1868d5aef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05 22:40:25 +00:00
Raul E Rangel 968f140ecb Revert "soc/amd/cezanne: Disable Co-op multitasking"
This reverts commit 5f80e7c764.

The smm_do_relocation failure has been fixed. I also added CPU_INFO_V2
into this patch to satisfy the dependency.

BUG=b:194391185, b:179699789
TEST=reboot stress test guybrush for 50 iterations.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05 22:39:38 +00:00
Raul E Rangel c842c59b3e lib/thread: Switch to using CPU_INFO_V2
CPU_INFO_V2 changes the behavior of cpu_info(). There is now only 1
cpu_info struct per cpu. This means that we no longer need to allocate
it at the top of each threads stack.

We can now in theory remove the CONFIG_STACK_SIZE alignment on the
thread stack sizes. We can also in theory use threads in SMM if you are
feeling venturesome.

BUG=b:194391185, b:179699789
TEST=Perform reboot stress test on guybrush with COOP_MULTITASKING
enabled.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05 22:39:16 +00:00
Raul E Rangel b2346a56f1 arch/x86,cpu/x86: Introduce new method for accessing cpu_info
There is currently a fundamental flaw in the current cpu_info()
implementation. It assumes that current stack is CONFIG_STACK_SIZE
aligned. This assumption breaks down when performing SMM relocation.

The first step in performing SMM relocation is changing the SMBASE. This
is accomplished by installing the smmstub at 0x00038000, which is the
default SMM entry point. The stub is configured to set up a new stack
with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point
of smm_do_relocation located in RAMSTAGE RAM.

This means that when smm_do_relocation is executed, it is running in SMM
with a different sized stack. When cpu_info() gets called it will be
using CONFIG_STACK_SIZE to calculate the location of the cpu_info
struct. This results in reading random memory. Since cpu_info() has to
run in multiple environments, we can't use a compile time constant to
locate the cpu_info struct.

This CL introduces a new way of locating cpu_info. It uses a per-cpu
segment descriptor that points to a per-cpu segment that is allocated on
the stack. By using a segment descriptor to point to the per-cpu data,
we no longer need to calculate the location of the cpu_info struct. This
has the following advantages:
* Stacks no longer need to be CONFIG_STACK_SIZE aligned.
* Accessing an unconfigured segment will result in an exception. This
  ensures no one can call cpu_info() from an unsupported environment.
* Segment selectors are cleared when entering SMM and restored when
  leaving SMM.
* There is a 1:1 mapping between cpu and cpu_info. When using
  COOP_MULTITASKING, a new cpu_info is currently allocated at the top of
  each thread's stack. This no longer needs to happen.

This CL guards most of the code with CONFIG(CPU_INFO_V2). I did this so
reviewers can feel more comfortable knowing most of the CL is a no-op. I
would eventually like to remove most of the guards though.

This CL does not touch the LEGACY_SMP_INIT code path. I don't have any
way of testing it.

The %gs segment was chosen over the %fs segment because it's what the
linux kernel uses for per-cpu data in x86_64 mode.

BUG=b:194391185, b:179699789
TEST=Boot guybrush with CPU_INFO_V2 and verify BSP and APs have correct
%gs segment. Verify cpu_info looks sane. Verify booting to the OS
works correctly with COOP_MULTITASKING enabled.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05 22:38:45 +00:00
Michael Niewöhner 9990866fcf drivers/intel/fsp2_0: don't force-use `python2`
Some distributions (e.g. NixOS, Debian) are actively working on getting
rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and
Python 3 as of upstream commit 0bc2b07, use whatever version is present
by utilizing `python`.

Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-10-05 20:33:18 +00:00
Martin Roth 26f97f9532 src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05 18:07:08 +00:00
Martin Roth 50863daef8 src/mainboard to src/security: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-05 18:06:52 +00:00
Martin Roth 0949e73906 src/acpi to src/lib: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05 18:06:39 +00:00
Martin Roth 6c3ece9c9e Documentation: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05 18:06:24 +00:00
Nick Vaccaro d4c55353e0 driver/intel/pmc_mux/conn: Add type-c port info to cbmem
This change adds type-c port information for USB type-c ports to cbmem.

BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot
volteer2 to kernel, log in and check cbmem for type-c info exported to
the payload:
  localhost ~ # cbmem -c | grep type-c
  added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
  added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0

Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-05 03:44:37 +00:00
Sheng-Liang Pan 2970f45fe6 mb/google/trogdor: Add new vaviant quackingstick
New boards introduced to trogdor family.

BUG=b:201263032
BRANCH=none
TEST=make

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I8299ddda14eb82103f17f8464a14992aa757afa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-04 22:40:03 +00:00
Meera Ravindranath 1399442289 soc/intel/adl: Drop SGPM, RGPM and EGPM methods
These methods can now be dropped as Dynamic GPIO PM is enabled.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0c7b67b5414d8c80775ab7678ce7b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 19:51:07 +00:00
Meera Ravindranath a7c333362c mb/*/brya/variants/brask: Enable dynamic GPIO PM
GPIO PM was disabled for brask to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. This change drops the GPIO PM override and
re-enables dynamic GPIO PM.

TEST=Boot brask to OS, ensure no TPM errors.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-10-04 19:50:43 +00:00
Meera Ravindranath 94a03fff07 mb/intel/adlrvp{p,m}: Enable dynamic GPIO PM
GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. This change drops the GPIO PM override and
re-enables dynamic GPIO PM.

TEST=Boot adlrvp to OS, ensure no TPM timeout errors.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-04 19:49:38 +00:00
David Wu 126162c38f mb/google/brya: Enable DDR4 SODIMM for brask
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in
brask device tree and add SPD addressese for the two DIMMs.

Separate the Kconfig items of brya and brask. Move
HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya
and add config SPD_CACHE_IN_FMAP to brask.

Add a new section RW_SPD_CACHE to fmd for caching SPD data.

The renamed romstage.c is used by both brya and brask and a new
function variant_get_spd_info is provided to support the different
SPD source types.

BUG=b:194055762
BRANCH=None
TEST=build pass

Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 18:41:03 +00:00
Ryan Lin 4a48dbe60b src/soc/intel/alderlake: Add PsysPmax setting
This patch feeds PsysPmax setting to FSP through UPD and adds a
PsysPmax member in chip information so that we can set PsysPmax
through devicetree. The PsysPmax needs to be set correctly mapping
to maximum system power. Otherwise, system performance would be limited
due to the default PsysPmax setting in FSP is only 21W.

BUG=b:193864533, b:195615830
TEST=Set PsysPmax to an example value eg 145 in devicetree &&
put debug code in FSP to print the PsysPmax value before sending
to Pcode, ensure the setting is correctly programmed.

Change-Id: Ia07aa815f90739240f110cab984068237c02d896
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 17:45:38 +00:00
Nick Vaccaro 15066ba8d4 driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.h
Move the locally declared typec_orientation enum from chip.h to
coreboot_tables.h.

Change enum typec_orientation name to type_c_orientation for consistency
with contents of coreboot_tables.h.

Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE.

BUG=b:149830546
TEST="emerge-volteer coreboot" and make sure it compiles successfully.

Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-04 17:15:47 +00:00
Nick Vaccaro a62b41819c coreboot tables: Add type-c port info to coreboot table
This change adds type-c port information for USB Type-C ports to the
coreboot table.  This allows depthcharge to know the usb2 and usb3
port number assignments for each available port, as well as the SBU
and data line orientation for the board.

BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds
successfully.  Cherry-pick CL to enable this feature for volteer,
flash and boot volteer2 to kernel, log in and check cbmem for type-c
info exported to the payload:
  localhost ~ # cbmem -c | grep type-c
  added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
  added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0

Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 17:12:48 +00:00
Felix Held 56da0b79ad lib/hardwaremain: change type of "complete" element in boot_state struct
A signed bitfield with a length of 1 bit can only have the values 0 and
-1. Assigning a 1 ends up behaving as expected, but it's not the
semantically correct thing to do there. Changing the type of the element
to an unsigned bitfield with a length of 1 would fix that, but since
this is used as a boolean value, just change it to bool type.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I230804335e7a15a8a9489859b20846988ba6c5cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-04 15:58:32 +00:00
Felix Held f10776781d lib/hardwaremain: add missing types.h include
The u8 type is used in the file, but neither stdint.h not types.h was
included in the file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd67aff9eba01f9618004c869f1473217b3aeae4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-04 15:58:10 +00:00
Lai, Jim ae9a84478f mb/google/brya/variants/kano: Correct MIPI camera info
Correct OVTI2740 information for Kano:
MIPI camera CIO port, HID and Link Freq

BUG=b:200974074
TEST=Build and boot on Kano
     camera driver is not probed before,
     and it can now be probed properly
     after this change.

Signed-off-by: Lai, Jim <jim.lai@intel.com>
Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 07:59:31 +00:00
Rex-BC Chen 5020fe3449 util/cbfstool: Add support for ARM64 UefiPayload
UEFI payload is supported on some ARM64 platforms, for example MT8195.
As a result, add MACHINE_TYPE_ARM64 to support ARM SystemReady.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4c0c6e263bd2f518a62ff9db44d72dd31086756a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-10-04 02:31:01 +00:00
Michael Niewöhner 880acbe2f4 soc/intel/common: round PM Timer emulation frequency multiplier
Round the PM Timer emulation frequency multiplier to the closest value
to increase precision.

Test: compared hexdumps of CML binaries for the expected result:
      before: 0x262E8B51, after: 0x262E8B52

Change-Id: Iafd645c248fc17943ea4be558ed7d01a301ba809
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57943
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-02 21:00:42 +00:00
Rex-BC Chen f4d6e9085d soc/mediatek: add debug dump for ltiming and clock_div
ltiming and clock_div are not support for MT8173, so we separate them
to weak function: mtk_i2c_dump_more_info()

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I3228c6953be5fac18a76029702b878a34c7563f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58074
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-02 11:50:22 +00:00
Daolong Zhu f4b71734b2 soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed
1. The original algorithm for I2C speed cannot always make the
   timing meet I2C specification so a new algorithm is introduced
   to calculate the timing parameters more correctly.
2. Some I2C buses should be initialized in a different speed while
   the original implementation was fixed at fast mode (400Khz).
   So the mtk_i2c_bus_init is now also taking an extra speed
   parameter.

There is an equivalent change in kernel side:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1

BUG=b:189899864
TEST=Test on Tomato, boot pass and timing pass
     at 100/300/400/500/800/1000Khz.

Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com>
Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-02 11:48:34 +00:00
Subrata Banik 38abbdab71 soc/intel/common/../cse: Avoid caching of CSE BAR
This patch ensures all attempts to read CSE BAR is performing PCI config
space read and returning the BAR value rather than using cached value.

This refactoring is useful to read BAR of all CSE devices rather than
just HECI 1 alone.

Additionally, change the return type of get_cse_bar() from `uintptr_t`
to `void *` to avoid typecasting while calling read32/write32 functions.

BUG=b:200644229
TEST=Able to build and boot ADLRVP where CSE is able to perform PCI
enumeration and send the EOP message at post.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-02 08:44:42 +00:00
Subrata Banik f576581954 soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macro
CSE_DELAY_BOOT_TO_RO -> CSE_DELAY_BOOT_TO_RO_MS

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I4471e4553a081eaf5c8118e9600497a2b2437ac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-02 08:42:46 +00:00
Seunghwan Kim c543a81736 mb/google/dedede/var/bugzzy: Update device tree
Update bugzzy device tree override based on the EVT schematics.

BUG=b:195215785
BRANCH=dedede
TEST=emerge-dedede coreboot

Change-Id: Iba8e3fd24461b4228c6e6fa933c0093e3e45ee97
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-01 22:48:26 +00:00
Sean Rhodes f71d8c94ea soc/tigerlake: Make IO decode / enable register configurable
This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-10-01 18:53:28 +00:00
David Wu 7a63f48a54 mb/google/brask/var/brask: Configure GPIOs according to schematics
Update initial gpio configuration for brask

BUG=b:197385770
TEST=emerge-brask coreboot

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I71026565b876739d2a08ef79940f47c476ca70a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58041
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01 18:49:45 +00:00
Sumeet Pawnikar 21c431b81d soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU
There are two different types of 282 SKU available with TDP
of 15W and 12W for Alder Lake-M SoC. This patch adds support
for these TDP values for 282 SKU as per document 643782.

BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board

Change-Id: I553b2362b7bf811e6bf02fd9d68f78c2caeb7398
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
2021-10-01 18:44:33 +00:00
Sumeet Pawnikar e415df9b7f mb/intel/adlrvp: set PL4 value dynamically for thermal
Set PL4 value dynamically for adlrvp board based on CPU SKUs
which is detectable at runtime. These values are based on
platform design specification.

BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board
On 682:
 Overriding power limits PL1 (4000, 28000) PL2 (64000, 64000) PL4 (140000)

Change-Id: I9c0c418e2548cc7f9aa647a5ad98123b33e9f9b8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01 18:43:52 +00:00
Sumeet Pawnikar 125206322d mb/google/brya: move MILLIWATTS_TO_WATTS macro in header file
Move MILLIWATTS_TO_WATTS macro in power_limit header file
so all other files can use the same macro.

BUG=None
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01 18:43:16 +00:00
Sumeet Pawnikar e06e43a83f mb/intel/adlrvp: set power limits dynamically for thermal
Set power limit values dynamically based on CPU TDP and PCI ID of SKU.
These values are as per platform design specification.

BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board

Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01 18:42:46 +00:00
Sumeet Pawnikar e2e0a6b597 acpi/acpigen_dptf: Add TPCH participant for dptf
Add TPCH as participant for dptf control functionality.

BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: I17c0c6cfb7804dd2caa188acc93f1a63b47cab36
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01 18:34:55 +00:00
Sumeet Pawnikar 4bb63e81f2 soc/intel/common: Add PMC IPC commands for FIVR control
Add PMC IPC commands information for FIVR control functionality

BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: I9d08bb71f7ea5da7614c68fc0ce4edf9aef59baa
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01 16:01:49 +00:00
Felix Singer ae90f2ebc5 util/liveiso: Install nvme-cli tool
nvme-cli is used to manage NVMe devices and it supports many vendors.
Also, it seems it's commonly used to do firmware updates.

Change-Id: I26a78867b01d3af0441827c5b25343a46d7ddea1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-01 15:08:07 +00:00
Eric Lai 38c83c90b3 mb/google/brask: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.
Follow up commit 658d7c5

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I508f7e21888cc1938aa9a6f0066c17029773974b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01 14:58:07 +00:00
Eric Lai 0d6ad2638a mb/google/brya/var/felwinter: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.
Follow up commit 658d7c5

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I494e0edc135d730cf7bb437f0196cdf233d970d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01 14:57:29 +00:00
David Wu 6c2d99f618 mb/google/brask/var/baseboard/brask: Update GPIO GPP_B5 and GPP_B6
Update GPIO GPP_B5 and GPP_B6 based on schematics.

BUG=b:197385770
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If83e02eec7c48b9ab41d346aa8baef7c0c881df1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-10-01 14:08:46 +00:00
Werner Zeh b1e4a9a6c3 mb/siemens/mc_ehl: Move UART_FOR_CONSOLE switch to variant level
There are currently two variants for mc_ehl where different UARTs are
used for the console. Move the Kconfig switch UART_FOR_CONSOLE to the
Kconfig of the variant and select the matching value there.

Change-Id: I7152013a0e32ff151b92932a47953705e591dc0d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58052
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-01 14:08:29 +00:00
Werner Zeh 264ace99e8 mb/siemens/mc_ehl: Add a new variant mc_ehl2
Add a new variant of the mc_ehl board called mc_ehl2. This patch just
copies the files and renames things where needed.
Following patches will adapt the needed features for this new variant.

Change-Id: I3ec3c091017fd66fe6a09216203cdc7c9e833846
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-10-01 14:07:41 +00:00
Werner Zeh 0bebcdb165 mb/siemens/mc_ehl1: Enable LPSS UART
Enable LPSS UART for coreboot console on mc_ehl1.

Change-Id: Id995953741d48fbbe2482ff7c0ef81cac5a31207
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-10-01 14:07:00 +00:00
David Wu 16e815fcad mb/google/brya/var/kano: Add Synaptics touchpad
Add Synaptics touchpad for kano.

BUG=None
TEST=emerge-brya coreboot and check touchpad function work.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Iec43aaa9525309d2a0e3c9822038869786f5fe66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-01 01:38:03 +00:00
Julius Werner e55d2e13e0 arch/arm64: Remove unnecessary interfaces
<clocks.h> and smp_processor_id() aren't used anywhere anymore. Get rid
of them.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1a8c892b066e6ac0e7cec5316633d44165344e78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-01 00:02:06 +00:00
Julius Werner b5e7bd2a58 drivers/gic: Remove unnecessary code
On AArch64 platforms, GIC initialization is generally the job of Trusted
Firmware and shouldn't be necessary in coreboot. Only the ancient T210
platform (which was started before we had decided on using Trusted
Firmware) calls this code, and even there they have a comment wondering
"do we still need this?". I'm just gonna assume (without testing because
that board is ancient and I'm lazy) that they don't, and that the TF GIC
initialization[1] is sufficient here. Remove this obsolete driver.

[1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff448/plat/nvidia/tegra/soc/t210/plat_setup.c#259

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-01 00:01:56 +00:00
Aamir Bohra ee760b4be8 mb/amd/bilby: Use I2S TDM interface
Bilby uses I2S TDM interface for audio, instead of HDA interface.

Change-Id: I7c8ec02d0e63730cb54a27d3bea1d102e037823d
Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
2021-09-30 13:54:46 +00:00