Commit Graph

35728 Commits

Author SHA1 Message Date
Furquan Shaikh fd4fbe8148 mb/google/zork: Configure all pads in ramstage for dalboz reference
This change configures all missing pads in ramstage for dalboz
reference. This ensures that the state of all pads is set correctly
for the payload/OS. Also, all the pads for the platform are configured
in baseboard gpio table in ramstage to ensure that variants can
override any pads if required.

BUG=b:154351731

Change-Id: Ia30da908d3827177a7b3594ffba38bff81018ab9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23 14:11:16 +00:00
Furquan Shaikh 65e1117741 mb/google/zork: Configure all pads in ramstage for trembyle reference
This change configures all missing pads in ramstage for trembyle
reference. This ensures that the state of all pads is set correctly
for the payload/OS. Also, all the pads for the platform are configured
in baseboard gpio table in ramstage to ensure that variants can
override any pads if required.

BUG=b:154351731

Change-Id: Idd827b6a4f995546493596f22249f8699bdf526b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23 14:11:03 +00:00
Furquan Shaikh ac16650e0c mb/google/zork: Remove unnecessary PULL_UP from early_gpio_table
This change drops PULL_UP configured on pads in early_gpio table since
these pads have external pulls.

BUG=b:154351731

Change-Id: Id270e7b4f83dfa942655f513776a3b1c15c9678d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23 14:10:50 +00:00
Furquan Shaikh 6f48626a82 soc/amd/common/gpio: Fix definition of GPIO_INT_ENABLE_STATUS_DELIVERY
This change fixes the definition of `GPIO_INT_ENABLE_STATUS_DELIVERY`
to use `GPIO_INT_ENABLE_DELIVERY` instead of
`GPIO_INT_ENABLE_STATUS_DELIVERY`.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I64d912200779875cf121cec4476fd39de74c0223
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23 14:10:34 +00:00
Felix Held 86db2c74ff amd/picasso: rename PCIe descriptor to DXIO descriptor
Most of the DXIO descriptors are used to configure PCIe engines and
lanes, but on Picasso system some of the DXIO lanes can also be
configured as SATA or XGBE ports.

Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23 13:47:39 +00:00
Felix Held a19d98647b vc/amd/fsp/picasso: add logical to lane number in port descriptor struct
The lane numbers in the PCIe/DXIO descriptor are the logical and not the
physical ones, so add logical to the corresponding field names of the
fsp_pcie_descriptor struct.

Change-Id: I7037fed225119218e87593932815aff815e83ff8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23 13:46:40 +00:00
Kevin Chiu a2b04f45c0 mb/google/kukui: Add new configs 'esche' and 'burnet'
new boards introduced to Kukui family.
esche: clamshell
burnet: 360 convertible

BUG=b:161768221
BRANCH=master
TEST=emerge-jacuzzi coreboot

Change-Id: I2245c34533549bb94c58938fee5778b8a03e2767
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-23 12:57:25 +00:00
Christian Walter b73dd9c97e mb/prodrive/hermes: Update VBT file
Update .vbt file to support two DP outputs.

Change-Id: Ifd4163aafe4ef3070d04a72a4699303af72c5102
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23 12:12:00 +00:00
Jeremy Soller 625af2b194 MAINTAINERS: Add Jeremy Soller for ec/system76 and mb/system76
I currently maintain System76 coreboot support.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I4240618c9d9846c3b9e30db4d5ac725e1ca2a09c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43674
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23 09:30:48 +00:00
Jeremy Soller 0de0fe1104 ec/system76_ec: add support for System76 EC
This adds ACPI code for System76 EC and converts system76/lemp9
to use EC_SYSTEM76_EC.

Tested on system76/lemp9.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I1f693268d94b693b6764e4a3baf4c3180689f3be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Michael Niewöhner
2020-07-23 09:30:22 +00:00
TimChu b8d6af9569 mb/ocp/deltalake: Add ipmi POST start command in romstage
Add function to send POST start command to BMC. This function is
used in romstage and the POST end command will be sent in u-root.

TEST=Read POST command log in OpenBMC,
if command received successfully, message may show as below,

root@bmc-oob:~# cat /var/log/messages |grep -i "POST"
 2020 Jul 15 16:36:11 bmc-oob. user.info fby3-v2020.23.1:
ipmid: POST Start Event for Payload#2
root@bmc-oob:~#

Signed-off-by: TimChu <Tim.Chu@quantatw.com>
Change-Id: Ide0e2a52876db555ed8b5e919215e85731fd80ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23 09:12:59 +00:00
Morgan Jang 9862138b67 mb/ocp/deltalake: Implement SMBIOS type 9 -- system slots by SKU
Create SMBIOS type 9 by getting PCIe config from BMC.

TEST=Check SMBIOS type 9 is created correctly on different SKUs

Change-Id: Ifd2031b91c960ff2add8807247271eb7c38a0bf2
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23 09:10:11 +00:00
Jonathan Zhang b45ed65ef0 soc/intel/xeon_sp/cpx: display SystemMemoryMapHob fields
SystemMemoryMapHob is necessary for SMBIOS type 17 among other things.
It is a fairly large structure, so the pointer to the data instead of
the structure itself, is included in the HOB. Use pointer to
SystemMemoryMapHob structure to interpret SystemMemoryHob HOB body.

Adjust the structure definition to match with CPX-SP ww28 release.

Display more fields to ensure the structure definition is correct.

TEST=Boot DeltaLake server, and check field values of SystemMemoryMapHob
to make sure they are correct:
0x7590a090, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
        f8870015-6994-4b98-95a2bd56da91c07f: FSP_SYSTEM_MEMORYMAP_HOB_GUID
================== MEMORY MAP HOB DATA ==================
hob: 0x777f7000, structure size: 0x6c88
        lowMemBase: 0x0, lowMemSize: 0x20, highMemBase: 0x40, highMemSize: 0x5d0
        memSize: 0x600, memFreq: 0xb76
        NumChPerMC: 3
        SystemMemoryMapElement Entries: 2, entry size: 16
                memory_map 0 BaseAddress: 0x0, ElementSize: 0x20, Type: 0x1
                memory_map 1 BaseAddress: 0x40, ElementSize: 0x5d0, Type: 0x1
        BiosFisVersion: 0x0
        MmiohBase: 0x80000
0x777f7000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
...
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I271bcbd6030276b8fcd99d5b4f2c93f034dd9b52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43336
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23 08:46:14 +00:00
Yu-Ping Wu b086728094 libpayload: cbgfx: Add draw_line()
Add a function draw_line() to draw either a horizontal or vertical line
segment.

Theoretically a horizontal line can also be drawn by calling
draw_rounded_box() with dim_rel.x being the line length and dim_rel.y
being the line width. However, due to the truncation in integer division
when converting relative coordinates to absolute ones, this will
potentially produce inconsistent line widths, depending on the value of
pos_rel.y.

It is guaranteed that draw_line() will produce consistent line widths,
regardless of the position of the line. Also, when the thickness
argument is zero, this function is able to draw a line with 1-pixel
width, which is not achievable by draw_rounded_box().

BRANCH=puff
BUG=b:146399181, b:161424726
TEST=emerge-puff libpayload

Change-Id: I2d50414c4bfed343516197da9bb50791c89ba4c2
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2020-07-23 05:09:31 +00:00
Krishna Prasad Bhat 918073d9bf mb/intel/jasperlake_rvp: Enable CSE Firmware Lite SKU for JSLRVP
This patch enables CSE Lite SKU for jasperlake rvp.

BUG=b:160201335
BRANCH=None
TEST=Build and boot jasperlake rvp with CSE Lite SKU.
Cq-Depend: chrome-internal:3142530

Change-Id: I60039ffb1f24cf98f55e83d8c8649745598aa43a
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40571
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23 04:54:52 +00:00
Krishna Prasad Bhat 21b303dc54 mb/intel/jasperlake_rvp: Skip CPU Replacement Check for jasperlake rvp
This patch enables the SkipCpuReplacementCheck config for jasperlake rvp
to avoid the forced MRC training with the soldered down SOC.

BUG=b:160201335
BRANCH=None
TEST=Build and verify on jasperlake rvp with CSE Lite SKU.
Cq-Depend: chrome-internal:3142530

Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23 04:54:38 +00:00
V Sowmya c529e6ca7c mb/google/dedede: Enable the CSE Lite SKU for dedede
This patch enables the CSE Lite SKU for the dedede baseboard.

BUG=b:160201335
TEST=Build and boot waddledoo with CSE Lite SKU.
Cq-Depend: chrome-internal:3142530

Change-Id: I24d7d715d55524807af0127aa4a346a008164b8c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-23 04:54:25 +00:00
V Sowmya 3915627615 mb/google/dedede: Skip the CPU replacement check for dedede
This patches enables the SkipCpuReplacementCheck config for
the dedede baseboard to avoid the forced MRC training for all
its variants with the soldered down SOC.

BUG=b:160201335
TEST=Build and verify CSE Lite SKU on Waddledoo.
Cq-Depend: chrome-internal:3142530

Change-Id: I611e66f74a3b9b090ab5e0d836231643d3f919dc
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-23 04:54:14 +00:00
V Sowmya e8156ad981 soc/intel/jasperlake: Add the SkipCpuReplacementCheck configuration
Add SkipCpuReplacementCheck config to control the FSPM UPD used
for skipping the CPU replacementment check to avoid the forced
MRC training for the platforms with soldered down SOC.

BUG=b:160201335
TEST=Build and verify CSE Lite SKU on Waddleddo.
Cq-Depend: chrome-internal:3142530

Change-Id: I63fcdab3686322406cf7c24fc26cbb535cc58c8d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-23 04:54:01 +00:00
Angel Pons df96d4db84 sb/intel/i82801jx/hdaudio.c: Rename to `azalia.c`
Other Intel southbridges use this name for the HD audio codec.

Change-Id: Ic96797e6c2028f082130211bb5f4270391f866c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22 22:21:13 +00:00
Angel Pons 0cd80270d1 sb/intel/i82801ix/hdaudio.c: Rename to `azalia.c`
Other Intel southbridges use this name for the HD audio codec.

Change-Id: I50dbf0a079944b7fa6cfd6622c0626bc9139af85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22 22:20:50 +00:00
Angel Pons 25a0b0ac5e sb/intel/i82801ix/sata.c: Use `probe_resource`
It is impossible for `find_resource` to return NULL, it dies instead.

Change-Id: If8e26f768383e741100e3690322db3dabeec1922
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22 22:20:05 +00:00
Tim Wawrzynczak 7777e1c30b ec/google/chromeec: Fix Coverity Scan error (BAD_SHIFT)
A recent Coverity scan found an issue with the way the
EC_HOST_EVENT_MASK macro was being used. It was being passed values
between 0 and 63, but since it is doing basically (1ULL << (value - 1)),
this caused a shift of -1 when `i` is 0 and also doesn't reach the 63rd
bit of the mask. This is fixed by incrementing the start and end
conditions of the loop by 1, so the event mask ranges from bits 0 to 63,
instead of -1 to 62.

Found-by: Coverity CID 1430218
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6a7cfa64545f3d313de24407f0a91b48368f2a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-22 21:06:56 +00:00
Tim Wawrzynczak 60c619f6a3 soc/intel/jasperlake: Move tco_configure to bootblock
Similar to CB:43313 (SHA bb50c67227), it seems possible for the same
problem to come up on jasperlake. Again, it should be harmless to
configure the TCO device earlier in the boot flow.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If95e46124660b4ed457434f727c9f9f7b02b0327
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43539
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 21:06:34 +00:00
Tim Wawrzynczak 03ed5bff5c soc/intel/cannonlake: Move tco_configure to bootblock
Similar to CB:43313 (SHA bb50c67227), it seems possible for the same
problem to come up on cannonlake. Again, it should be harmless to
configure the TCO device earlier in the boot flow.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib8883d27b2a0994a67ec5e044a692a2e853fd680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43538
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 21:06:29 +00:00
Kane Chen bfd6521ce7 mb/google/zork: Modify Woomax variant
Update Woomax configuration including GPIO, memory SPD table, I2C devices
and USB type C.

BUG=b:158343602
BRANCH=None
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I55ba995d9438551d45cb9e17f92b5089ccf4a5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-22 15:20:28 +00:00
Angel Pons 3580d816e6 nb/intel/i945: Put names to northbridge PCI devices
Tested with BUILD_TIMELESS=1, Getac P470 does not change.

Change-Id: I0d51f48f0c1e37c41322a0eda49806925d9d194d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42285
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 14:51:39 +00:00
Felix Held ce55b36c99 mainboard/amd/mandolin: describe where the two HDA codecs reside
Change-Id: I99b062e4ce1cf862ea03b0edb6ea843df5f8f2b2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-22 14:43:13 +00:00
Tim Chu 0ecb7857ce mb/ocp/deltalake: Unset POWER_STATE_DEFAULT_ON_AFTER_FAILURE
Change PCH power policy. Set default of
POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n in order to change power
state to S5 when power is reapplied after power failure.

TEST=Base on CB:42289, CB:43338 and build for Deltalake.
The following Kconfig options must be selected:
	select SOC_INTEL_COMMON_BLOCK_PMC
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select CPU_INTEL_COMMON_SMM

Boot the system and check the last bit of GEN_PMCON_B is set to 1
through ITP with command: pch.pm_dump

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I4d4f14bdfc18740976171fd5d369b2d79a916dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42976
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 12:20:49 +00:00
Johnny Lin 2b3a500fed mb/ocp/deltalake: Set FSP log level and add default values if VPD variables are not found
1. Read VPD variable 'fsp_log_level' to decide FSP log level.
2. Define the default values when the VPD variables cannot be found,
   put all the values to vpd.h for better documentation and maintenance.

Tested=On OCP DeltaLake, the fsp_log_level can be changed from the VPD variable.

Change-Id: I44cd59ed0c942c31aaf95ed0c8ac78eb7d661123
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-22 12:19:53 +00:00
Felix Held 973b2aaa24 vc/amd/fsp/picasso: mark remaining UPD header structs as __packed
Change-Id: I5a97de69bfda201e039587c67037bfb93ca16c15
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43658
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 11:53:12 +00:00
Angel Pons 8d5cedf046 sb/intel/i82801jx: Drop `docking_supported`
The three mainboards using this southbridge are desktop boards, which
are not dockable. The Dell Precision M6400 laptop is dockable, but even
though it has an Eaglelake MCH, it uses an i82801ix southbridge instead.
So, one could still port that laptop to coreboot after this change! :P

Also, drop the now-unnecessary `chip` and `dev` variables.

Change-Id: Ic9ab497c91d66032929190cde22d59a208887f50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22 08:27:33 +00:00
Angel Pons 27387c3cf5 sb/intel/i82801jx: Drop `c3_latency`
The three mainboards using this southbridge do not define it. Note that
the default value of zero might be wrong, so add a FIXME comment.

Change-Id: Id16bb12a4628daf311bddf7e4701fc480d6b18e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22 08:27:23 +00:00
David Hendricks 4cdc698707 Doc/tutorial/part1.md: Show how to list toolchain targets
Change-Id: I276ea0a6b52b55b8772c76f48f7a0fb149af6e78
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43518
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 04:56:25 +00:00
Hung-Te Lin bc792af28e mb/google/kukui: revise config structure for Jacuzzi followers
There are more Jacuzzi followers coming and we want to have a simplified
way of adding new boards. Now, detachable and tablets should select
BOARD_GOOGLE_KUKUI_COMMON and clamshells should select
BOARD_GOOGLE_JACUZZI_COMMON.

BUG=None
TEST=make menuconfig; make -j # for kukui, krane, jacuzzi, juniper
BRANCH=kukui

Change-Id: Ifc1eb6a3792f46c5db6b5346902f1114955b28ae
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-22 00:27:43 +00:00
Ian Feng b0b7c351d7 mb/google/dedede: Create madoo variant
Create the madoo variant of the waddledoo reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

BUG=b:161191394
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_MADOO

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I6d3f611606f86036d67be9c8b0fda833ab61ecc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-21 23:57:43 +00:00
Subrata Banik b622d4b27b soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2
This patch performs below operations
1. Add support for FSP 2.2
2. Set EnableMultiPhaseSiliconInit to ensure bootloader can call
FspMultiPhaseSiInit() API.
3. Provide placeholder to perform require chipset programming (example TCSS)
before calling FspMultiPhaseSiInit() API.

Change-Id: I15252d2db3f8e75d430b84e86cc5141225a3f981
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-21 22:57:49 +00:00
Furquan Shaikh f6b2e6f836 mb/googlz/zork: Drop unnecessary PULL_UPs in variant overrides
This change drops the pulls configured on override GPIOs as they
already have external pull-ups. Also, pads which are unused are
configured as PAD_NC.

BUG=b:154351731

Change-Id: I8da5d51af25bbe2694c21ecb0868c9cc387243cb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-21 22:42:57 +00:00
Angel Pons b4b4e32e4c sb/intel/lynxpoint/me_9.x.c: Add spaces around `=`
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I1baa731335a9c543c7d31b9aadc8758806750c64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42629
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 22:12:59 +00:00
Michael Niewöhner 48833363da mb/system76/lemp9: drop FSP_M_XIP
Drop FSP_M_XIP since it's selected by the soc already.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I999d369be395de08d4ab7f115fedf4b7fa10eb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-07-21 22:11:56 +00:00
Michael Niewöhner f662020a4d mb/system76/lemp9: drop ONBOARD_VGA_IS_PRIMARY
Drop config ONBOARD_VGA_IS_PRIMARY as it's only needed for mainboards
with multiple graphics devices.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6525c65af3dcfc96ea3d68a1388432179e9ac43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43636
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 22:11:41 +00:00
Angel Pons 5ad4dabfa1 configs/config.stm: Correct config file name
Otherwise, Jenkins doesn't pick up the file, and STM doesn't get
build-tested.

Change-Id: I7cf23c8352f82b2672c7ff25efba0057b8e059cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-07-21 22:08:04 +00:00
Peter Lemenkov d4fb407158 mb/lenovo/t430/gma-mainboard.ads: Replace with GPLv2+ equivalent
Replace it with t430s/gma-mainboard.ads which is licensed under more
flexible terms (GPL-2.0-only vs. GPL-2.0-or-later). Apart from licensing
terms these files are identical.

This makes diff between boards smaller.

Change-Id: I633702d363134654e71e35404237d75b499f089a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-21 21:53:03 +00:00
Peter Lemenkov a1dcb994d7 mb/lenovo/t420/gma-mainboard.ads: Replace with GPLv2+ equivalent
Replace it with t420s/gma-mainboard.ads which is licensed under more
flexible terms (GPL-2.0-only vs. GPL-2.0-or-later). Apart from licensing
terms these files are identical.

This makes diff between boards smaller.

Change-Id: I5393a603b5a4cd353149c1fa9e3e29020946b962
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-21 21:52:53 +00:00
Angel Pons 002e5e057c security/intel/stm: Add missing <stdbool.h>
Jenkins does not build `config.stm` because the file name lacks the
mainboard name. So, the code was not being build-tested, and it does not
build because several files lacked the definition for `bool`.

Add the missing #include directives. Renaming the config file so that
Jenkins build-tests it is done in a follow-up.

Change-Id: Idf012b7ace0648027ef6e901d821ca6682cee198
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43622
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 20:04:12 +00:00
Elyes HAOUAS 04071f43bc src: Use ACPI macros
Change-Id: I2cf11b784299708f02fd749dcb887b6d25f86f5b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21 18:26:47 +00:00
Mate Kukri f2c13bd905 soc/intel/baytrail: Add new CPUID 0x30679
This ID is reported by newer mfg date SOCs. Needed for newer GBYT4 boards.

Change-Id: I6af746d66a15f67553de1dc1c925e5cb0b181898
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21 18:26:15 +00:00
Mate Kukri 9c4f97ac28 mb/biostar: Add TH61-ITX port
- CPU: only tested with a Xeon E3-1220 (Sandy Bridge)
- RAM: native raminit tested (4G+4G, 8G+8G)
- USB: both chipset and ASMedia USB3 work, tested in SeaBIOS and Linux (5.4)
- LAN: tested in Linux
- SATA: all 4 ports work, tested in SeaBIOS and Linux
- iGPU: I can't test it as I only have a Xeon for this socket
- PEG: tested with an nVidia GT210, initialized by SeaBIOS
- PS2 keyboard and mouse combo port: no devices to test with
- Front panel header: tested, works
- Audio: tested, works
- Diagnostic LEDs: TBD

Change-Id: I9fd3c0b148b694fcb8e728cc17f0bd45eb5af9f2
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43165
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:25:51 +00:00
Angel Pons 1659724375 e7505/i82801dx: Use common code for early SMBus
While it looks different, the early SMBus code for this southbridge is
still the same. In addition, this code was not checking the vendor ID
before. It is assumed that adding this check does not pose a problem.

Change-Id: I95ae4db399ce5592cefca82fa75f349220023b8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42006
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:24:07 +00:00
Angel Pons 7a2cb35262 i945/pineview/x4x/i82801gx: Use common code for early SMBus
The early SMBus code for this southbridge checked if the PCI device ID
is valid. However, we can't easily do that in common code, and we should
not attempt to do so either: if a SMBus device behaves differently, then
it should not be using the common code anyway.

Since this southbridge is used with two different northbridges, we need
to update both of them. Plus, x4x raminit no longer needs to know which
southbridge it is paired with, since both i82801gx and i82801jx use the
common early SMBus code, so we drop some preprocessor around includes.

Change-Id: Ic60a3f89bda6000fbe646461f05240c1b09db6e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42005
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:23:54 +00:00