According to the documentation [1], IA32_PLATFORM_ID MSR register
address should be 17H.
[1] Table 2-2. Intel (R) 64 and IA-32 Architectures Software Developer’s
Manual. Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Change-Id: I9a16b162db51d21c7849b3c08c987ab341845b1e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The NO_POST option covers more than classical port 80 output, hence
selecting it seems wrong in any case. The default is still rather
user patronizing, but let's keep it.
As a side effect, this fixes the ability to override the default
for NO_POST which Kconfig rejected while these boards selected it.
(Seems like a bug in Kconfig, though.)
Change-Id: I896b08812b1aa6ce249d7acc8073ebcc0f72eace
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Some boards with the G41 chipset lacked programming CIR, so this
change add that to those boards too.
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The vendorcode/eltan mboot and verified boot options only build if a
few other Kconfig options are defined.
Change-Id: Ie333d2fbf294e23ec01df06ee551e2d09541c744
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35954
Reviewed-by: Wim Vervoorn
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is only one subdir in vendorcode/siemens and it does not feature
a Kconfig file.
Change-Id: I136743344465cea9c769234aa84d9ebe874ef0d2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The next board rev will have a new option for an Elan touchscreen. Add
support for this in the devicetree, as well as use the 'probed' property
on both touchscreen options.
BUG=b:141957731
BRANCH=none
TEST=compiles (next board rev not available yet)
Change-Id: I135e693304cbb8dffc0caf4c07846033d6802208
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Update GPIO_138 and GPIO_139 setting to fix EMR function.
BUG=b:141729962,b:141281846
BRANCH=octopus
TEST=verify EMR function in Grob360S.
Change-Id: I28cef592374fb4aeee2f3d3010cc0e237d62a2fd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Rework SGX enable status in a clean way without using a global variable.
Change-Id: Ida6458eb46708df8fd238122aed41b57ca48c15b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is done by default in the main Makefile.inc.
TEST: With BUILD_TIMELESS=1 the resulting binary is identical before
and after the change.
Change-Id: Ie85e023df1f1c2b0f115e4f92719a511f60019c3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Since struct dramc_param has been defined, we can pass the struct
directly from mt_mem_init().
BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: If7333fb579eff76dd9d1c2bf6fdfe7eccb22050f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35846
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load the calibration params from flash first and check the correctness
of the params. If the params have correct format, perform DRAM fast
calibration with these params to reduce bootup time. Otherwise, load the
DRAM blob and perform DRAM full calibration.
Bootup time of DRAM partial calibration:
- 1,349,385 usecs with low frequency
- 924,698 usecs with middle frequency
- 1,270,089 usecs with high frequency
3,544,172 usecs in total.
Bootup time of DRAM fast calibration:
- 216,663 usecs with low frequency
- 328,220 usecs with middle frequency
- 322,612 usecs with high frequency
867,495 usecs in total.
BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Load calibration params from flash. If the format of the params is
correct, use these calibration params for fast calibration to reduce the
bootup time.
Bootup time of DRAM partial calibration:
- 1,349,385 usecs with low frequency
- 924,698 usecs with middle frequency
- 1,270,089 usecs with high frequency
3,544,172 usecs in total.
Bootup time of DRAM fast calibration:
- 216,663 usecs with low frequency
- 328,220 usecs with middle frequency
- 322,612 usecs with high frequency
867,495 usecs in total.
BUG=b:139099592
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I9ef4265dd369a1c276bb02294696556df927e7bc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35164
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dramc_param module simplifies the communication between coreboot and
MTK DRAM full calibration blob, and is shared by both implementations to
ensure the same format of parameters.
BUG=b:139099592
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Since we always write to &ch[chn].ao.dummy_rd after calling
dramc_engine2_end(), this write could be merged into dramc_engine2_end()
to simplify code.
BUG=none
BRANCH=none
TEST=emerge-kukui coreboot
Change-Id: Ibb4bd5ed016118811ad2097098417c19f00f4263
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35749
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is now done during the romstage.
Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape
in the same way bash/zsh do. As a result, the decoded files ended up
with ASCII numbers instead of the decoded binary data.
Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68
Signed-off-by: Greg V <greg@unrelenting.technology>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Minimize use of hard-coded value for acpi_table_header->length to soft
code. Replace length of acpi_header_t with sizeof(acpi_fadt_t).
Change-Id: Ibcae72e8f02497719fcd3f180838557e8e9abd38
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Nuvoton and Winbond use the same off-by-5 indirect address space to
access their hardware monitor/environment controller in the SIO chip, so
move this to a common location and replace the inb/outb calls with the
corresponding inline functions from device/pnp.h
Change-Id: I20606313d0cc9cf74be7dca30bc4550059125fe1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The superio driver that was linked in is nct6779d but static
devicetree expected symbol superio_nuvoton_nct5572d_ops.
Change-Id: I648b7680bb39b9ff5b38cc3bd5147bd336e0b282
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Devices behind LPC can expose more buses (e.g. I2C on a super-i/o).
So we should scan buses on LPC devices, too.
Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
scan_usb_bus() and root_dev_scan_bus() had the very same implementation.
So rename the latter to scan_static_bus() and use that for both cases.
Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31901
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting the cbfs prefix is prone to error. Therefore add a Kconfig
choice for 2 common values, fallback and normal, while still keeping
the ability to specify an arbitrary value.
Change-Id: I04222120bd1241c3b0996afa27dcc35ac42fbbc8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The value stored to 'spd_bytes_total' is never read. Now it is fixed.
This is spotted using clang-tool v9.
Also add a check if spd_bytes_used and/or spd_bytes_total are reserved
and make sure that spd_bytes_used is not greater than spd_bytes_total.
Change-Id: I426a7e64cc4c0bcced91d03387e02c8d965a21dc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This reverts commit 275f2e22a1.
Since in this commit the inclusion of site-local/Makefile.inc was moved
outside of the guard 'ifeq ($(NOCOMPILE),1)', this Makefile.inc will be
included always here (what seems to be the intention of this commit).
As we have a second place where site-local/Makefile.inc is included
(top-level Makefile.inc via subdirs-y class) this unconditional include
leads to a double included site-local/Makefile.inc. Therefore one will
get errors if a separate rule is used in site-local/Makefile.inc.
Change-Id: I0a693c1d793b978c8023e4f107dce139d537d8db
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
For fields with single bit, it's easier to declare as
DEFINE_BIT(name, bit)
Change-Id: If20e6b1809073b2c0dc84190edc25b207bf332b7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Applying reset_gpio config of stylus for kohaku. GPP_A19 has been assigned in
the latest schematics.
We would keep GPP_A10 as output high for old revision devices temporarily.
BUG=b:141914474
BRANCH=none
TEST=verified stylus works internally
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I61f0f9a4378f47bf455f0726d44beeaf2f67197b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Add PRESERVE to UNIFIED_MRC_CACHE so that we don't retain the memory
training data upon a FW update unless we need to. We have had users
complaining that a 15 second memory training upon update makes them
believe that their device is not booting, thus many of them hard
resetting before bootup.
BUG=b:142084637
BRANCH=None
TEST=flash RW_SECTION_A, RW_SECTION_B, and WP_RO sections and make
sure memory training doesn't occur on following bootup.
Change-Id: Ia5eb228b1f665a8371982544723dab3dfc40d401
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35803
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Maxim Polyakov