Commit Graph

25154 Commits

Author SHA1 Message Date
Jonathan Neuschäfer 0bb93707c8 Documentation/timestamp.md: Fix markdown formatting
Fix the headline levels (only the document's title should be a top-level
document), and use "# " instead of "====" to mark headlines, because
it's more obvious what the different levels of that are. Also fix some
other things.

Arguably, the explicit table of contents could be removed.

Change-Id: Ie29b6393e9d7871ea3c900e016b5c3ed415538ac
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17 17:18:23 +00:00
Jonathan Neuschäfer 7719d50352 Documentation/Intel: Adjust heading levels
Adjust the headings so that there is only one h1 tag per file.

Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-17 17:18:07 +00:00
Shelley Chen a2e17586dc mb/google/poppy/variants/nami: Update GPIOs
Updating some GPIOs based on changes in the latest schematics.  Also
renaming signals to match that of latest schematics.

BUG=b:73749640
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
     Make sure different SKUs still boot.

Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17 17:15:45 +00:00
Justin TerAvest a8a717de30 mb/google/octopus: Enable Yorp EC software sync
With one additional EC change, Yorp is able to flash the EC as part of
software sync and successfully boot. This change is only made for Yorp
as we want this disabled for Bip bringup.

BRANCH=none
BUG=b:77874283
TEST=Successful flash and boot on Yorp with this change
TEST=Checked GBB flags on Yorp and Bip images with gbb_utility
CQ-DEPEND=CL:1014397

Change-Id: I4969b254c6a58fba9dd8d2f31feb25b55c7a0c65
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25692
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17 16:05:40 +00:00
T Michael Turney 809fa7b5c2 cbfs: Add cbfs_boot_load_file()
Generalize cbfs_boot_load_struct() by passing in CBFS type

Change-Id: I6e5f845cb4ce5b00f01a39619919f85e39028f19
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-17 10:46:13 +00:00
Venkateswarlu Vinjamuri 79f1c3e2a5 soc/intel/apollolake: Implement _PS0/_PS3 methods for PCIe root ports
Creates a common asl include file for PCIe power state methods. This
allows ports to be enabled independently.

BUG=None
BRANCH=None
TEST=None

Change-Id: I7b1cf4e14ebdfe9ecc7131dfe47c70ed7e2c3dc5
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/25532
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17 10:44:47 +00:00
Venkateswarlu Vinjamuri f03c63ef95 soc/intel/apollolake: Configure PCIe root port #3 for GLK WiFi
GLK Octopus uses PCIe root port #3 (PCIe ID 13.0) for discrete PCIe
wifi card.

BUG=None
BRANCH=None
TEST=Use Stone Peak discrete wifi card and test s0ix.

Change-Id: I8a064c5d97e4765bd97ec560c89b207b574b1fa1
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/25638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17 10:42:46 +00:00
Venkateswarlu Vinjamuri efeb6903fe soc/intel/apollolake: Configure PCIe root port #1 for APL WiFi
APL uses PCIe root port 1 (PCIe ID 14.0) for discrete PCIe wifi card.

BUG=None
BRANCH=None
TEST=Use Stone Peak discrete wifi card and test s0ix.

Change-Id: Ia81722f4533916fe93009a73d86765e5de9dab08
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/25637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17 10:42:32 +00:00
Arthur Heymans a4e8f67b94 nb/intel/x4x/rcven.c: Change the verbosity of some messages
Displaying the whole receive enable procedure is very verbose should
only be done if CONFIG_DEBUG_RAM_SETUP is selected.

Change-Id: Ib568621e6d044624c1c0aeb6fb08945f561395c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-17 10:41:57 +00:00
Arthur Heymans 276049f9ee nb/intel/x4x: Add a convenient macro to loop over bytelanes
During raminit a lot of procedures need to be done for each bytelane.

Change-Id: Ib9a30ffabaf5c845e962e3e79cf4a20faa1d9857
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-17 10:41:14 +00:00
Arthur Heymans 1994e448be nb/intel/x4x: Clarify the raminit memory mapping
This replaces magic values by macros and adds some comments to improve
readability.

Adds a convenient function to fetch the test address of a rank.

Also fixes the temporary memory map by changing a write to MCHBAR
0x100 to 0x110, since this is what vendor does. (No difference
observed thus far)

TESTED on DG43GT

Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-04-17 10:40:36 +00:00
Arthur Heymans 0bf87de667 nb/intel/x4x: Refactor setting default dll settings
This patch pushes these large default delay tables to a different file
to reduce cluttering up the actual raminit source. While doing so it
also uses more but smaller arrays and also adds the respective default
delays for DDR3 which are not yet used in this patch.

This patch add a function to set the read DQS delays instead of just
programming magic values. (This will prove useful for DQS read
training)

To prepare for adding trainings on the delay values it stores these
default delays in the sysinfo struct to program those. Later when
trainings are implemented those trained values will be used instead of
these safe default values, via using the cached sysinfo in 'mrc'
cache.

TESTED on DG43GT (still works fine)

Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-17 10:40:11 +00:00
Arthur Heymans adc571a54c nb/intel/x4x: Use SPI flash to cache raminit results
Stores information obtained from decoding dimms and receive enable
results for future use.

Depreciates using rtc nvram to store receive enable settings.

A notable change is that receive enable results are always reused, not
just on a resume from S3.

This requires cbmem to be initialized a bit earlier, right after the
raminit finished to be able to add the sysinfo struct to cbmem which
gets cached to the SPI flash in ramstage.

TESTED on Intel DG43GT with W25Q128.V. With 4 ddr2 dimms time in
raminit goes from 133,857ms (using i2c block read to fetch SPD) to
21,071ms for cached results.

Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-17 10:39:45 +00:00
Paul Menzel 0cdaad36eb Use git HTTP URLs without `/p` in it
Change-Id: I9972b138c6dd2a289880c4ec8b3fe64fc3baa66b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25545
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17 10:38:06 +00:00
Frank Wu 2a67c37020 mb/google/poppy/variants/nami: Enable DPTF and configure DPTF parameters
The commit enables DPTF function. The DPTF parameters are provided by
thermal team.

BUG=b:72974136
BRANCH=poppy
TEST=emerge-nami coreboot then check the parameters in DPTF ui tool

Change-Id: I9b7ae34ee64f19ef783a8c1571831b2293105a18
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17 06:05:50 +00:00
Frank Wu 0ac94ee3b0 soc/intel/skylake: check DPTF_TSR0_ACTIVE_AC* in _ACx methods
Because thermal table is not included the values of DPTF_TSR0_ACTIVE_AC5
and DPTF_TSR0_ACTIVE_AC6 from internal nami/vayne thermal team.
Add conditional compilation in _ACx methods if DPTF_ENABLE_FAN_CONTROL
is defined in the dptf.asl.

BUG=b:72974136
BRANCH=poppy
TEST=emerge-nami coreboot and booted on nami board.

Change-Id: I3e36ce94f714ff13f8ccee65992d7a9c7e0bb5b2
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25614
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17 06:04:56 +00:00
Patrick Rudolph ad4ddfcfdb util/intelmetool: Add additional helpful error messages
Add more verbose error message for common problems on modern
operating systems, like Secure Boot and CONFIG_STRICT_DEVMEM.

Change-Id: Ie3361910d48271bcc2cd3b4b74937fbc5df0a176
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16 22:27:26 +00:00
Patrick Rudolph 405d2eabe0 util/intelmetool: Fix bootguard dump
* Fix broken bootguard report on Intel ME 9.5+
* Fix broken debug statement
* Add additional rehide_me()
* Move last rehide_me()

Tested on Lenovo T470p. It shows correct BootGuard state:
Verified & Measured Boot.

Tested on Lenovo T430. It shows correct BootGuard state: Disabled.

Change-Id: Ib6c49ee39dd9962a4981e7de19b1c98c753f2944
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16 22:27:14 +00:00
Patrick Rudolph 0391d0b023 util/intelmetool: Add support for platforms without RCBA
Only try to unhide MEI if the PCI device wasn't found and
probe for RCBA before trying to use it.

Allows to run the utility on Skylake and newer hardware that
do not have RCBA any more.

TODO: Use sideband interface to unhide MEI.

Change-Id: I7926aa80b132d5be9fece0724516701d74dd4d3d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16 22:27:02 +00:00
Patrick Rudolph aac3b31dbb util/intelmetool: Fix crash on strict devmem kernels
Don't crash if mapping MEI PCI memory fails.
This can happen if CONFIG_STRICT_DEVMEM is enabled.

Change-Id: I33c75a7cccb4cefaa26f70aed4bdc4bd620cdad0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16 22:26:46 +00:00
Paul Menzel 44ad86a723 util/scripts: Add script to alphabetize MAINTAINERS file
Copy script from Linux added in commit 7683e9e5 (Properly alphabetize
MAINTAINERS file) by Linus Torvalds.

> This adds a perl script to actually parse the MAINTAINERS file, clean
> up some whitespace in it, warn about errors in it, and then properly
> sort the end result.
>
> My perl-fu is atrocious, so the script has basically been created by
> randomly putting various characters in a pile, mixing them around, and
> then looking it the end result does anything interesting when used as
> a perl script.

Change-Id: I2eb4e3f9863d0fe242fb690f1121842c80d72d6a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/20742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16 22:25:31 +00:00
Piotr Kubaj f3bd97cb89 util/lint: Fix execution on OpenBSD
util/lint/lint creates a file using mktemp.
mktemp on OpenBSD requires at least 6 X's, while only 5 are in the template.

Change-Id: I0b80214dd83d21e12e16a5002c68127a7ca2e41b
Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl>
Reviewed-on: https://review.coreboot.org/19745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16 22:19:07 +00:00
Piotr Kubaj 1b36c9de66 nvramtool: Fix build with OpenBSD
OpenBSD needs the same includes as NetBSD. It also doesn't have x86_64_iopl
function, but amd64_iopl.

Change-Id: I28273d4d87a3a77cf35412a0695325c0535e42e5
Signed-off-by: Piotr Kubaj <pkubaj@anongoth.pl>
Reviewed-on: https://review.coreboot.org/19741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-04-16 22:18:26 +00:00
Bill XIE a4bf0b7cd1 drivers/pc80/tpm: Add some optional delay to tis_readresponse()
Certain TPMs (observed on Infineon SLB9635 installed on revolve 810 g1)
seem to need some delay between tis_wait_valid() and
tis_has_valid_data(), or tis_has_valid_data() may invalidly return 0,
ending the loop immaturely with some bytes left unread, and fail to
pass the check below, causing the current command not finalized by
tis_command_ready(), and blocking any later tis_wait_ready().

This time the added delay is controlled by a Kconfig option
TPM_RDRESP_NEED_DELAY.

Change-Id: Ic2a2f252e72a0bbce51e2863f8e46647b1570ba5
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/25322
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16 15:47:53 +00:00
Paul Menzel c8412ed1f9 nb/intel/i945/gma: Log native graphics init in level INFO
This information is not spew but useful to users.

Change-Id: I195c6913b7f0b96680b433ff3251aebb7e0f70f3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-16 08:48:36 +00:00
Paul Menzel 82683c0d6d nb/intel/i945/gma: Fix aligment of equal sign
Change-Id: I4251071fc8d41a923b4e12de214670764097d47c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-16 08:48:27 +00:00
Hannah Williams 0a2b9d4ab3 mb/google/octopus: Add Write Protect GPIO to cros_gpios
This will enable crossystem to access WP GPIO

BUG=b:78009842
TEST= wpsw_cur in crossystem reads the correct gpio

Change-Id: Iedd0057d6bdfd5a666ff282bc784f7b98e8c96e8
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16 08:47:14 +00:00
Dan Elkouby dabebc3716 nb/intel/sandybridge: support more XMP timings
Tested with a pair of GSkill F3-1866C9-8GSR.

This makes sure in particular that we honor the CMD rate requested by
the XMP profile. This memory kit needs a CMD rate of 2 to be stable at
DDR3-1600 and up, even though it passes training at 1.

Also respect requested CWL to match vendor firmware and for a potential
increase in performance. The tested kit requests a tighter value than
the per-frequency table provides and has shown to be stable using that
setting.

Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25664
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16 08:46:30 +00:00
Dan Elkouby 0c024208cd device/dram/ddr3: improve XMP support
- Fix offsets for supported CAS latencies
- Add support for reading CWL and CMD rate from the profile

Change-Id: Ie4f545ed1df92c146be02f56fea0ca9037478649
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16 08:46:23 +00:00
Jonathan Neuschäfer 9f79d60910 Documentation/acpi/gpio.md: Fix formatting of table
The table in Documentation/acpi/gpio.md is currently detected as
free-form text (at least by GitHub and recommonmark), instead of a
table. Wrap it in a code formatting block to preserve the manual
formatting.

Change-Id: If460d7f1ba1a6198d949886f0f55fd6254bc2f7a
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16 08:45:40 +00:00
Jonathan Neuschäfer b709b50a36 Documentation/acpi/gpio.md: Fix markdown heading levels
Only the document title should be a top-level heading ('#'). Everything
else should be a second- over lower-level heading ('##').

Also remove the '#' sign at the end of heading lines. "# Foo #" is
mentioned as a valid syntax variant at [1], but it's quite uncommon.

[1]: https://daringfireball.net/projects/markdown/syntax#header

Change-Id: Ida16c3ecaa22e8439007673cb943d04952e19471
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16 08:45:16 +00:00
Richard Spiegel 3d34ae3fc4 soc/amd/stoneyridge/northbridge.c: Fix bit definitions
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits. Fix these definitions, including the header file where they are
defined.

BUG=b:77940747
TEST=Build and boot grunt.

Change-Id: Icb5334110248d7806421200a161fa3befefcea8a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25665
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16 08:44:50 +00:00
Richard Spiegel bbcfa8afd5 soc/amd/stoneyridge/lpc.c: Fix bit definitions
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits, also some bits were wrongly named (possibly copied from previous chip).
Fix these definitions, including the header file where they are defined.

BUG=b:77940747
TEST=Build and boot grunt.

Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16 08:44:44 +00:00
Chris Zhou e148ddc3dd mb/google/poppy/variants/nami: Add SPD file for Pantheon
Add SPD file for sdp hynix_dimm_H5AN8G6NCJR-VKC (ram id: 15).

BUG=b:77893710
TEST=Verified that the device with this memory part boots to OS fine.

Change-Id: I434d42ff12e6dae39e5676f36ba6cf00b3a48b06
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16 08:42:15 +00:00
Chris Zhou 1564bf09ee mb/google/poppy/variants/nami: Add SPD file for Pantheon
Add SPD file for sdp micron_dimm_MT40A512M16LY-075E (ram id: 14).

BUG=b:77930401
TEST=Verified that the device with this memory part boots to OS fine.

Change-Id: Ia44e70948e57c2f19664d874ae005ac39d748f92
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16 08:40:36 +00:00
Aaron Durbin 4677f6bbfa lib/bootmem: tightly couple bootmem_init to bootmem_write_memory_table
In https://review.coreboot.org/25383 people were confused about the
ordering of bootmem calls w.r.t. when entries are exposed to the OS. To
alleviate this add a notion of bootmem being initialized. In addition to
that, only mark bootmem initialized when bootmem_write_memory_table() is
called. Any other calls to bootmem before that will report an error on
the console.

Change-Id: I5bc31f555038ccabb82d902c54f95858679b1695
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-16 08:39:21 +00:00
Nico Huber 99b65668f9 soc/intel/skylake: Hook up libgfxinit
Also base the FSP/GOP related bail-out on the correct Kconfig option
to allow adding a VBT along with libgfxinit.

Most things should work, what doesn't is backlight control because
coreboot misses the settings (moved to FSP and need backporting).
Also, Kaby Lake is still unsupported.

TEST=Booted yet to be upstreamed Skylake-S port (Kontron/bSL6) both with
     text and linear framebuffer mode and viewed a FILO menu.

Change-Id: I79fbfed7732cf02d054530ea7ec0d34de32836ba
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-04-16 08:37:09 +00:00
Marshall Dawson edf2f59b1d google/kahlee: Resume on AC insertion
The EC should wake the system from S3 when the AC connector is plugged.

BUG=b:77602394
TEST=verify resume on insert with Grunt

Change-Id: I4bcaef2fe75283aaa6260b5b9efd408ff4b05f4c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16 08:35:33 +00:00
Garrett Kirkendall 1b92474412 vendorcode/amd/pi/00670F00: Remove unused headers
Remove unused header files in
src/vendorcode/amd/pi/00670F00/agesa_headers.h.  This  is a first
clean up.  Hopefully more headers will be removed in other commits.
Header files cannot be removed at this time.  They are used by files in
vendorcode/amd/pi/00670F00/.

BUG=b:77944801
BRANCH=none
TEST=build Gardenia and Grunt

Change-Id: I99b77f6ba41ded30122a01bbe709681312561436
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25644
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16 08:35:05 +00:00
Garrett Kirkendall 30df2a41ce vendorcode/amd/pi/00670F00: Remove unused headers
Remove unused AGESA header files from
vendorcode/amd/pi/00670F00/binaryPI/AGESA.c

BUG=b:77905293
BRANCH=none
TEST=build Gardenia.

Change-Id: Ic38424d489dcc37a4074159e33fca0d49c71f701
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16 08:34:50 +00:00
Akshu Agrawal 0e9aa2623a mb/google/kahlee: Select BT I2S PAD on ACP_BT_UART mux
bt-pad-enable property is used by kernel driver to set
BT I2S PAD on ACP_BT_UART_PAD_SEL mux, for those platforms which
use these pins for BT I2S. By default the pins are set for UART.

BUG=b:72360151
TEST=Tested playback and capture on audio device connected to BT I2S

Change-Id: Id76bfa1fa1dde904f02a03b0c15986ecb1bbcc97
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25653
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16 08:34:12 +00:00
Dan Elkouby 3781e1fda9 autoport: add missing PCI IDs
As seen on ASUS P8Z77-V Pro

Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16 08:33:43 +00:00
David Hendricks f8d13d5658 intel/fsp_broadwell_de: Set FSP serial speed to match coreboot's
This makes FSP use the same baud rate as coreboot so that the user can
more easily change it without having to modify the FSP binary.

Change-Id: I0084aa9a0394ad7eabdd88809b66fc21a25ba316
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-16 05:57:06 +00:00
Hannah Williams 57d8ccb5f0 soc/intel/apollolake: Fix CPU address bits
APL and GLK have 39 address bits

Change-Id: I9b761492332c545c13a0594d8f5937ca84bc0699
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16 05:04:35 +00:00
Katherine Hsieh 0c557cd983 Revert "mb/google/reef/sand: Override USB2 phy settings"
This reverts commit aef0d6b0a7.

This commit can only pass far-end USB eye diagram but will fail on 
near-end. Confirmed with Intel we should revert it.

Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/25651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-16 02:39:34 +00:00
Aaron Durbin fa529bb940 soc/intel/apollolake: update cache options for glk
On glk there's a 4MiB L2 cache all the time. Take advantage of that
by initializing a 1MiB cache-as-ram area.

BUG=b:72728953

Change-Id: Ia4e777a13607d8b70c05534b0a172f0ec6b04c51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25645
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16 02:25:28 +00:00
Werner Zeh cee8532ce3 intel/fsp_broadwell_de: Remove buggy code for SMBus clock gating
The pch_smbus_init() function contains code to enable clock gating for
the SMBus controller. Unfortunately this code is buggy and leads to a
hanging system with the latest microcode version.
The hang occurs as follows:
The clock gate register is mapped into RCBA space. After reading the
RCBA address from the LPC device config space no mask is applied to the
value (only bits 31..14 are valid while bit 0 is the enable bit). For
this reason the final address is off by one. The old microcodes at least
allowed this unaligned access to the RCBA space. With the latest
microcode this access leads to CPU hang.

Once this is fixed the next issue occurs: After setting the clock
gating bit for SMBus (bit 5) the SMBus controller disappears from the
PCI bus completely and hence no usage of it is possible anymore.

To fix this issue the clock gating code is completely removed as it was
intentionally meant to enable clock gating on the SMB_CLK line and not
the clock gating on the PCIe interface of the SMBus controller.

This issue is known already and was discussed on the mailinglist:

[coreboot] BDX-DE PCI init fail
https://mail.coreboot.org/pipermail/coreboot/2018-January/085908.html

TEST=Boot mc_bdx1 with microcode version M1050663_07000012.

Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25652
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16 02:25:06 +00:00
Patrick Rudolph 0b643d2499 nb/intel/sandybridge/peg: Add PEG driver stub
Required for other ACPI generators, like the one used for _ROM.

* Add ACPI code for PEG10/PEG11/PEG12/PEG60 and include it on all platforms.
* Add PCIe driver for PEG. The driver returns ACPI names for ssdt generators.

Needs test on real hardware.

Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22337
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13 16:55:14 +00:00
Martin Roth 70df5d6e43 src/mainboard/kahlee: Turn on keyboard backlight on grunt
Turn on keyboard backlight in romstage to indicate that the system is
booting.

BUG=b:77921345
TEST=Boot grunt, keyboard backlight comes on.

Change-Id: Ib215b19ebdee2f8c4f431af775905eca42436d1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25636
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13 16:50:52 +00:00
Martin Roth 2c3e3ef654 soc/amd/stoneyridge: add a romstage hook for mainboards
There wasn't previously a way for Stoney platforms to run mainboard
specific code in romstage.  This adds an early call for configuration
and passes along whether the system is currently resuming from S3.

BUG=b:77921345
TEST=Build, verify that weak function implementation gets called.

Change-Id: Id94855e1084814ec37956e603cd093d70f01a559
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-13 16:50:41 +00:00