Use shared gpio code from common folder, except for
INTEL_LYNXPOINT_LP, which has it's own gpio code.
Needs test on real hardware !
Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13615
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This makes the test IDs the default, taken from depthcharge
master (board/*/fmap.dts, hwid property).
Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13634
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
These are generated from depthcharge's board/*/fmap.dts using the
dts-to-fmd.sh script.
One special case is google/veyron's chromeos.fmd, which is used for a
larger set of boards - no problem since the converted fmd was the same
for all of them.
Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT
region ends up at the beginning of flash). This becomes necessary
because we're working without a real cbfs master header (exists for
transition only), which carved out the space for the offset.
Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12715
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The last_boot NVRAM option was deprecated and removed in
commit 3bfd7cc6. Remove the last_boot option from all
affected mainboards to eliminate user confusion.
Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12316
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Those are actually board specific. Keep the old value as defaults,
though. The defaults are included by all affected boards.
Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Move the CHROMEOS dependent symbols VIRTUAL_DEV_SWITCH and
VBOOT_DYNAMIC_WORK_BUFFER under the CHROMEOS config options for the
mainboards that use them.
Change-Id: Iad126cf045cb3a312319037aff3c4b1f15f6529d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Add CHROMEOS dependencies to selects for the following Kconfig
symbols:
CHROMEOS_RAMOOPS_DYNAMIC
CHROMEOS_RAMOOPS_NON_ACPI
CHROMEOS_VBNV_CMOS
CHROMEOS_VBNV_EC
CHROMEOS_VBNV_FLASH
EC_SOFTWARE_SYNC
LID_SWITCH
RETURN_FROM_VERSTAGE
SEPARATE_VERSTAGE
VBOOT_DISABLE_DEV_ON_RECOVERY
VBOOT_EC_SLOW_UPDATE
VBOOT_OPROM_MATTERS
VBOOT_STARTS_IN_BOOTBLOCK
WIPEOUT_SUPPORTED
This gets rid of these sorts of Kconfig errors:
warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has
unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS)
Note: These two boards would never actually have CHROMEOS enabled:
intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out
google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS
Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11272
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CAR_MIGRATION was removed in commit:
cbf5bdfe - CBMEM: Always select CAR_MIGRATION
ALT_CBFS_LOAD_PAYLOAD was removed in commit:
cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD
MARK_GRAPHICS_MEM_WRCOMB was removed in commit:
30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB.
EXTERNAL_MRC_BLOB was removed in commit:
0aede118 - Drop unused EXTERNAL_MRC_BLOB
CACHE_ROM is only in Google's codebase.
LID_SWITCH is only in Google's codebase.
DEFAULT_POST_DEVICE_LPC is only in Sage's codebase.
ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used.
HUDSON_NOT_LEGACY_FREE never existed as far as I can tell.
MAINBOARD_DO_EDID never existed as far as I can tell.
Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10616
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Commit 899d13d (cbfs: new API and better program loading) broke
panther's lan init when no vpd.bin present from which to read
the MAC address. Fix this by checking the validity of the search
address pointer, rather than the search length.
Change-Id: I8c7ca410d8ce5c5d92242a21c4c2ff4c001a68bd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10509
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
A new CBFS API is introduced to allow making CBFS access
easier for providing multiple CBFS sources. That is achieved
by decoupling the cbfs source from a CBFS file. A CBFS
source is described by a descriptor. It contains the necessary
properties for walking a CBFS to locate a file. The CBFS
file is then decoupled from the CBFS descriptor in that it's
no longer needed to access the contents of the file.
All of this is accomplished using the regions infrastructure
by repsenting CBFS sources and files as region_devices. Because
region_devices can be chained together forming subregions this
allows one to decouple a CBFS source from a file. This also allows
one to provide CBFS files that came from other sources for
payload and/or stage loading.
The program loading takes advantage of those very properties
by allowing multiple sources for locating a program. Because of
this we can reduce the overhead of loading programs because
it's all done in the common code paths. Only locating the
program is per source.
Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9134
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Old igd.asl had inconsistent addresses (between _DOD and actual device)
and ghost devices. Any of those is enough to make brightness on windows
fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous
copying of the same thing 6 times per chipset. Leave only hooking up and
chipset-specific part in chipset directory. Move NVS handling and ACPI-spec
parts to a common file.
Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7472
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
This code is not specific to ChromeOS and is useful outside of it.
Like with small modifications it can be used to disable TPM altogether.
Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10269
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of being pointer based use the region infrastrucutre.
Additionally, this removes the need for arch-specific compilation
paths. The users of the new API can use the region APIs to memory
map or read the region provided by the new fmap API.
Change-Id: Ie36e9ff9cb554234ec394b921f029eeed6845aee
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9170
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
SLIT and SRAT are created this way only on amdk8 and amdfam10.
This saves the need of having a lot of dummies.
Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7052
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The variable was set on all haswell boards, so we can do it like on
broadwell where the MSR based timer is assumed to be around, too.
Change-Id: Id48ad7454d4cf83c3b1616b64687cdcfee4baa10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10256
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Sample code belongs to documentation, not copied 100x over prodcution code.
Change-Id: I6bb318d76057d02bd6ac5641d12d56ab6d60b745
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10229
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We already have APM_CNT_FINALIZE defined to the same value. Just use it
thoughout.
Change-Id: Ife94ec7a34da27d3a720bda7337c02e41f18ac72
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10226
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Remove dependency of Haswell on cpu/intel/socket_rpga989 code,
which is a carry-over from Sandy Bridge/Ivy Bridge and older
coreboot conventions where features were structured around socket types.
Add CPU-specific options to Kconfig and required subdirs to
Makefile.inc which are curently included with socket_rpga989.
TEST=successfully built and booted on google/panther
Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10037
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These options will need to just be selected in within
the .config files. There's not need in duplicating all
these options.
Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9959
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For boards with MAINBOARD_HAS_CHROMEOS, we should also
state what kind of storage is available for vboot's
non-volatile data.
The flags are taken from the chromium repository and
have no effect with CHROMEOS disabled.
Change-Id: I1747ad26c8c7f6d4076740ec2800dbd52c5d6b3d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change switches all mainboard vendors and mainboards
to be autoincluded by Kconfig, rather than having to be mentioned
explicitly.
This means, vendor and mainboard directories are becoming more
"drop in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree mainboards / components
to be built with a given coreboot version (given that the API did
not change)
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a
Reviewed-on: http://review.coreboot.org/9295
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
PHYSICAL_REC_SWITCH is set n by default and y for panther and stumpy.
BUG=none
BRANCH=ToT
TEST=Built nyan_blaze using vboot1/2. Built falco, lumpy, nyan,
blaze, parrot, rambi, samus, storm, pinky with default configuration.
panther and stumpy are not tested because they currently don't build on ToT.
Original-Change-Id: Ic45f78708aaa7e485d2ab459fd1948524edb412f
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227940
Original-Reviewed-on: https://chromium-review.googlesource.com/229602
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit edb2ba347b48887ffe450586af0351e384faad59)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I277f665cd4f3e1c21745cdc5c7a2cfe148661abe
Reviewed-on: http://review.coreboot.org/9444
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
This config is used only to generate PIRQ table. If no such table is
supplied there is no need for config.
Change-Id: I537d440f53019a6bf7f190446074e75e7420545a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7566
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
In case we get an invalid thermal reading, let's run the fan
at full speed rather than at low speed. This might impact the
user experiance slightly in cases where the bad reading does
not happen while the system is hot, but it will increase stability
in the cases where the system is actually overheating.
Also, set the critical temperature below tjmax, because otherwise
thermal shutdown by the OS will never be triggered.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Iab262f1f17a5dff875c596d9e8d50e4e50ee90f9
Reviewed-on: https://chromium-review.googlesource.com/188556
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 721fc2361ea9c6fea75409be57726294ce840f03)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6962
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The google mainboards were updated to unconditionally include
chromeos.c except for panther.
Change-Id: I35bbd56326ee0f94ee542bae28f9c23980e9a9ed
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6874
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Remove #include early_serial.c and rename to early_init.c as no actual
UART configuration is done here. Note that this SIO component still
hard codes its base address to 0x2e.
Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6271
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This change makes it possible for vboot to avoid an
exploit that could cause involuntary switch to dev mode.
It gives depthcharge/vboot some information on the
type of input device that generated a key.
BUG=chrome-os-partner:21729
TEST=manually tested for panther
BRANCH=none
CQ-DEPEND=CL:182420,CL:182241,CL:182946
Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/182357
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Tested-by: Luigi Semenzato <semenzato@chromium.org>
Commit-Queue: Luigi Semenzato <semenzato@chromium.org>
Reviewed-on: http://review.coreboot.org/6003
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Set critical temp to match newer devices
Change-Id: I11f32297a9b8c9a3554821b5d1cd723d8d9e2b69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/6023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
BUG=chrome-os-partner:21535
BUG=chrome-os-partner:25990
BRANCH=panther
TEST=manual: Boot on Panther and look in /sys/firmware/log for
the string "PCIe Root Port 4 ASPM is enabled"
Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187153
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6007
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
FLVL is used to keep track of which thermal zones are active, but it is
not initialized upon boot / resume. An initial value of zero corresponds
to all zones being active, which causes the fan to spin at max speed
until the OS changes zones. Fix this annoyance by initializing FLVL to
the lowest temperature zone.
Also, fix a related bug where FLVL may jump to an undesired value. For
example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's
already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4
active!). Fix this by not taking zone ON / OFF actions if our zone is
already ON / OFF.
BUG=chrome-os-partner:25766, chrome-os-partner:24775
TEST=Suspend / resume on Panther 20 times, verify that thermal zone after
resume matches expectation based upon temperature. Also, stress system
and verify thermal zones become active according to temperature
increase.
Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186455
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186669
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6006
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Without this patch coreboot will always use the read-only version
of ramstage, even if there is a read-write version available.
BRANCH=panther
BUG=chrome-os-partner:25870
TEST=Install different RO and RW version, check in cbmem log that
coreboot's romstage and ramstage have different timestamps
in their banners.
Change-Id: I723a3d4479d59534660728d891a9f40a077b4ef0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186664
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/6005
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Based on latest thermal report
BUG=chrome-os-partner:24532
TEST=boot tested on panther
BRANCH=panther
Change-Id: I4b8639f926fc3cf57eb5329818b9b912bfbe222d
Signed-off-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186113
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6004
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
When the thermal sensor on Panther is unavailable (early on resume)
it will return 0x80 which causes our AML thermal code to overflow,
which causes the system to shut down. Instead, return a reasonable
value in those cases so that the system will continue running until
the sensor gets back on its feet.
BUG=chrome-os-partner:24918
BRANCH=panther
TEST=suspend_resume_test survived more than 100 iterations on Panther
Change-Id: Ib2d714c39d353ce2415361bc6590784a3f6837d2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182369
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6002
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
