Moves the K8 CPU_ADDR_BITS definition from socket to model.
Previously socket_F was not setting CPU_ADDR_BITS correctly.
Tested on Sun Ultra 40 M2 with two 2nd-gen Opterons w/ 2x4x2GiB DIMMs.
Most if not all K8-based chips support 40-bit physical addresses, with
possible exception of IA32-only K8-based Athlon XP-M chips.
Probably irrelevant, unless your machine has enough memory (at least 60 to
64GiB before MMIO hoisting) to exceed the CPU_ADDR_BITS default of 36 from
src/cpu/x86/Kconfig.
Change-Id: I01a2a59fa902280171840c36ca2e631476d3d603
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10963
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The new toolchain depends on it.
Change-Id: I9070925eeb3f63a6c31e7474ffb9cba15884703d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/10976
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I3cf6a579f4e62a59828e81aa63c3a1a020a15ea6
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10906
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For people new to Linux, add the xxd hint to compare output with output
from Linux.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: Ia46aeed056b12abbadf8205b044944385d9410e1
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Found while doing code review.
Simplify the code by using a loop for positive and negative phase
adjustments.
Change-Id: I0980443d0d2815bccef969709fddecc07d61a788
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10890
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Issue observed:
Two memory DIMMs are placed in the same channel, but only one shows up.
The SPD is read and printed, but the first DIMM isn't recognized any more.
Due to an existing but unconfigured memory DIMM the timB test failed.
Test system:
* Intel Pentium CPU G2130
* Gigabyte GA-B75M-D3H
* DIMMs:
* crucial 2GB 256Mx64 CT2566aBA160BJ
* corsair 8GB CMZ16GX3M2A1866C9
Problem description:
The channel's rankmap was overwritten by the second slot's rankmap.
Problem solution:
Logical OR the channel's rankmap with every slot's rankmap.
Final testing result:
The DIMM is recognized and can be properly configured and used.
The timB test doesn't fail any more.
Change-Id: I17a205ff4d344c13d9ddfe71aaae2f3cef047665
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10960
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
It doesn't know "source", but wants the older "." instead
Change-Id: Iafa61b1d2ffc9c737ab67a417c62417593b69374
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/10974
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION
structure to include these new PCD options and initialized the setting
when given in devicetree.cb.
Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/10838
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
In case of continuous mode, use STA_ACTIVITY bit to determine if DMA
operation is complete. However, in case of ONCE mode, use STA_BSY bit
to determine if DMA operation on the channel is complete.
This change was propogated from T210, commit ID fe48f094
BUG=None
BRANCH=None
TEST=Ryu/Rush build OK.
Change-Id: I13073cc12ed0a6390d55b00c725d1cc7d0797e23
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aab62d5148b57fd1e05c1e838eafe8fdee431ef8
Original-Change-Id: I7388e9fd73d591de50962aaefc5ab902f560fc6f
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286468
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/11017
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The LZ4 decompressor currently doesn't check for output overruns before
writing data in the case where a block had been incompressible (and
included verbatim in the compression stream). This is extremely unlikely
with the default 4MB blocks, but still a nice thing to fix. We'll still
output as much data as we can before returning an error to support
partial decompression use cases.
This matches the behavior already in place for normal, LZ4-compressed
blocks where the decompression function is already (supposed to be)
doing complete bounds checking (although it is not guaranteed to output
all valid bytes before aborting on an output overrun, and you should try
to provide a few dozen bytes of extra buffer space beyond the parts
you're interested in on partial decompression).
BRANCH=None
BUG=chrome-os-partner:32184
TEST=None
Change-Id: I5e40c8cec8947ec0ec8f6d8c8fa2574cfb4dc958
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 636985334c9b3b93a12d4066d2829f1f999c9315
Original-Change-Id: Iecf44650aade60b9fa1b13e57da752fb482a3f3f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286240
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Address region from 0x0 to 0x00ffffff is used for IROM_LOVEC and
can not be accessed by Bootloader.
Issue found in CL: 283104 is captured by this patch.
BUG=None
BRANCH=None
TEST=Compiles successfully and reboot test does not crash in firmware
Here are memory mapping table before and after this CL for evt2 board:
Before:
Mapping address range [0000000000000000:0000000040000000) as cacheable | read-write | secure | device
Mapping address range [0000000040000000:0000000040040000) as cacheable | read-write | non-secure | normal
Mapping address range [0000000040040000:0000000080000000) as cacheable | read-write | secure | device
Mapping address range [0000000080000000:00000000feb00000) as cacheable | read-write | non-secure | normal
Mapping address range [00000000fec00000:0000000100000000) as cacheable | read-write | secure | normal
Mapping address range [0000000100000000:0000000140000000) as cacheable | read-write | non-secure | normal
After:
Mapping address range [0000000001000000:0000000040000000) as cacheable | read-write | secure | device
Mapping address range [0000000040000000:0000000040040000) as cacheable | read-write | non-secure | normal
Mapping address range [0000000040040000:0000000080000000) as cacheable | read-write | secure | device
Mapping address range [0000000080000000:00000000feb00000) as cacheable | read-write | non-secure | normal
Mapping address range [00000000fec00000:0000000100000000) as cacheable | read-write | secure | normal
Mapping address range [0000000100000000:0000000140000000) as cacheable | read-write | non-secure | normal
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I07d38a8994c37bf945a68fb95a156c13f435ded2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3eee44944c2c83cc3530bfac0d71b86d3265f5b2
Original-Change-Id: I2b827064807ed715625af627db1826c3a01121ec
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285260
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11015
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Even if DEBUG=0, BL31 puts NOTICE(..) messages on serial console. Set
LOG_LEVEL=0 if coreboot does not use serial.
BUG=None
BRANCH=None
TEST=Compiles successfully and no console output from bl31 for
production images.
Change-Id: Ie77bcac3e2a0d314545b6811327c413536c77fb9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8e3bcbf6249c80850a87dd66f34d3ff36158641
Original-Change-Id: I1415a3816cd2fa9dd05bcbd36ac0abc3f2759960
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286150
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/11014
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
BUG=chrome-os-partner:42881
BRANCH=None
TEST=Using ctrl-d in recovery mode to switch to dev mode works.
Change-Id: Iefbd11d435c4beb570875d4835a085b194d1d1e8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: be172409792a224855b1d31621f23d1969d319b9
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Change-Id: Icf57dfc4cc258aa2cba341f40d285f8c843aace5
Original-Reviewed-on: https://chromium-review.googlesource.com/286612
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/11013
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If the Host Command payload is less than 4 bytes
and is word aligned then the payload was not transferred at all.
EC reads the old packet and CRC mismatch occurs.
In this issue, the HC command packet
consisting of EC_CMD_REBOOT_EC as command and EC_REBOOT_COLD
as payload encountered the same problem as above.
Hence select byte access mode for shorter payloads.
BRANCH=None
BUG=chrome-os-partner:42396
TEST=System should boot after
chromeos-firmwareupdate
Change-Id: I22bdb739108d31b592c20247be69c198d617d359
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8a43d2636b1bbfbac0384e1ea5e8853a7bd87a7f
Original-Change-Id: I5572093436f4f4a0fc337efa943753ab4642d8e4
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286537
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/11012
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Log the global reset causes in the power state structure.
While working in there pack the struct and use width-specific
types as this struct crosses the romstate <-> ramstage boundary.
Lastly, remove hsio version as it wasn't being written or read.
After global reset induced:
PM1_STS: 0000
PM1_EN: 0000
PM1_CNT: 00000000
TCO_STS: 0000 0000
GPE0_STS: 00000000 00000000 00000000 00000000
GPE0_EN: 00000000 00000000 00000000 00000000
GEN_PMCON: d8010200 00003808
GBLRST_CAUSE: 00000000 00040004
Previous Sleep State: S0
BUG=None
BRANCH=None
TEST=Induced global reset on glados using ETR3 register and write
to cf9.
Change-Id: I97b93de336e74c0e02199241376e74340612f0a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bbc8f1d62131c0381e9d401f3281ee7a17fc2a47
Original-Change-Id: I1a8e5d07c6c0e09c163effe27491d8f198823617
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286640
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11011
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The GPIO mapping was incorrect for wpsw_cur.
The GPIOs for East community were in two ranges:
0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and
12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26]
The discontinuity was not accounted for, hence the error.
The original offset was 0x16 whereas it should be 0x13
BUG=chrome-os-partner:42798
BRANCH=None
TEST=Run crossystem and test wpsw_cur entry. If screw is present,
it should be 1 and if not present, it should be 0
Change-Id: I2faea1fe1415c9d4cb23444d03c7c9d47c87e8e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30ac96f606a5618e9ef12bac3f50fac433141acd
Original-Change-Id: I166a7c3e15a990b507ae3c13e15ab56bee7fb917
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286534
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/11010
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Document the lid open state and separate the routines with a single
blank line.
BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu
Change-Id: I244f20c03bc7530ad8d140fba41dd97c12c079e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 57313253fdef3f2d3f0e16b8ab8aa91202d45b16
Original-Change-Id: I7b3bd9cf16e915d214eb2de0017a8d91a934b112
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286267
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11009
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove the address from the copyright notices.
BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu
Change-Id: Ibe8196841d9e76c9ee3a3dbae802ecc63dc7904c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cc12d2658324a375d02748098f0a2f4b5d1b5615
Original-Change-Id: I81a71e4ad9b8a66ad0e9a93cbeb512d90eb35906
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286266
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11008
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Tested-by: build bot (Jenkins)
If a resume from S3 is occuring one needs to take into account
deep S3 in order to check the proper power failure bits.
When deep S3 is enabled the suspend well will be turned off.
Therefore don't look for that bit when determining a power
failure.
BUG=chrome-os-partner:42847
BRANCH=None
TEST=Suspend and resumed with deep s3 enabled and disabled.
Change-Id: I2b3372a40b3d8295ee881a283b31ca7704e6764a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3ba22be37d8700f4e8a4a0f5c05fb9290cfc9b2
Original-Change-Id: I890f71a7cbea65f1db942fe2229a220cf0e721b0
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286271
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
GEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and
save the full 32 bits for completeness.
BUG=chrome-os-partner:42847
BRANCH=None
TEST=Built and booted. Noted output on terminal.
Change-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0
Original-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286270
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11006
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Charger performance states table defines charger current limit for each
p state. Modify charger current control values for SANYO battery used
in Cyan.
BUG=None
BRANCH=None
TEST=System is charging battery, in shell window, issue command
"echo 0 > /sys/class/thermal/cooling_device4/cur_state",
"echo 1 > /sys/class/thermal/cooling_device4/cur_state",
"echo 2 > /sys/class/thermal/cooling_device4/cur_state",
"echo 3 > /sys/class/thermal/cooling_device4/cur_state", or
"echo 4 > /sys/class/thermal/cooling_device4/cur_state", will see EC
console show different charging current value.
Change-Id: Ie9bc78822a73de6bed338bfbcc5e9045653689dc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3a6162151d1f9c756a13d2afc17f6b9c18608efc
Original-Change-Id: I71e8247d057e4728eedcd5e8a275b64428290d09
Original-Signed-off-by: li feng <li1.feng@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285605
Original-Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Original-Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: http://review.coreboot.org/11004
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch updates the Serial IO modes for UART2 to PCI mode
in devicetree for glados board.
Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit
legacy UART will stop working after devicetree change.
BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for glados and tested LPSS logs on glados.
CQ-DEPEND=CL:284881 CL:284882 CL:284883
Change-Id: I433979c852c80848c006ef089b43d75a17e761c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189
Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284826
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11002
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch updates the Serial IO modes for UART 1 and 2
in devicetree for kunimitsu boards.
UART1 are disabled and
UART2 is in PCI mode.
BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for kunimitsu and tested LPSS logs on Kunimitsu.
Change-Id: I5a46ab9e0b792478ee2e0845aeab1443423a2fac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38c7b963a9d679ee5106c5343e1173d0b5056627
Original-Change-Id: I39cbb6bb0991e5f9b3365adaf6b24818d112cd1a
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284825
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11001
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch updates the Serial IO modes for UART 1 and 2
in devicetree for sklrvp boards.
UART1 is disabled and
UART2 is in PCI mode.
BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for sklrvp and tested LPSS logs on RVP3.
Change-Id: I59a657d6a3744040ec6be290ba966672e0e5f17e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5a20a70801d66abd87d4214e1ef187b86eed99da
Original-Change-Id: I381374272e1824ca8887ea5c5662215dde2c0a56
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284824
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
printk called before console init causes sluggish execution because
of Rx timeout.
BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for sklrvp and tested LPSS logs on RVP3 and Kunimitsu.
Change-Id: I61d5c0f5a4e93695bcba90b7ac7d4f68e2d625be
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 77c58702c8279c6d9c6ae1c946bf1b76df20714d
Original-Change-Id: Ib85029456059248cc2c88aaccba4fa12cc5a76be
Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284823
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10996
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
FSP will initialize GPIOs during TempRamInit.
So configure LPSS UART2 GPIOs in native mode
after TempRamInit.
BRANCH=none
BUG=chrome-os-partner:41374
EST=Build and boot on RVP3. Check LPSS logs on UART2
Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c
Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9
Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/281604
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10995
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
On Skylake, only UART2 is supported as debug port and the macros
INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial
code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and
Glados boards.
BRANCH=none
BUG=chrome-os-partner:40857
TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2
Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642
Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10994
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
FSP 1.1 platforms should be conforming to the spec. In order
to ensure following specification remove the crutch that allows
FSP to no conform.
BUG=chrome-os-partner:41961
BRANCH=None
TEST=Built.
Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a
Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285187
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Disabling the wwan gpio line
since wwan is not used.
BRANCH=none
BUG=none
TEST=wwan should not connect to network on cyan/strago.
Change-Id: I9d2e5d5b185a4622218e894d3b092afe15e09289
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9a20c602b3bb768baa38b17e21cb4e5b0d9249ef
Original-Change-Id: Ib8d5fd15a172ef898ce675a85c2ea3e5f5c79144
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285304
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Removing GOP initialization in normal mode since we don't need to
show splash screen in normal mode. GOP will get initialized in dev
and recovery mode.
BRANCH=none
BUG=None
TEST=Splash screen will come only in dev or recovery mode.
Change-Id: Ia5e12cf45d723f2f14c447e29b78119552d5e1ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 79d1c877343704ea51143b922d9ac9209be4d4b5
Original-Change-Id: Id5ca99757427206413483d07b4f422b4c0abfa5d
Original-Signed-off-by: Abhay <abhay.kumar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285300
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10990
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All boards should have their L1 sub states working now so
re-enable the defaults.
BUG=chrome-os-partner:41861
BRANCH=None
TEST=Built and booted glados into OS. PCIe devices show up still.
Change-Id: Ic040fa108a662e15bb97cf8b0961f0f56683e146
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 380491f8267e60c3c6bc62486aaf21e201fcfd36
Original-Change-Id: Idc6923b1fdd1c20d463eb7782be112f90b9adbfd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285170
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10989
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For some unkonwn reason the pcie root port settings weren't
being honored in the device tree. Fix that omission.
BUG=chrome-os-partner:41861
BRANCH=None
TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree
settings were being honored.
Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257
Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285027
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10987
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Unhide the SPI controller PCI device if it is enabled in
devicetree.cb so flashrom can do its job.
BUG=chrome-os-partner:37711
BRANCH=none
TEST=run flashrom -r on glados
Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245
Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284948
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10986
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:40526
BRANCH=None
TEST=Verify that system boots when used with coreboot and EC
versions that also have Software Sync enabled.
Change-Id: I6ed562fa51d83ddf16fc74d35db7c0004f57c79e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 090a66c50fac21808c4721a32b1728cc904f1b00
Original-Change-Id: Ia4d87d9a177c579567c03ae113889a277ffecee0
Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/283573
Original-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Original-Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/10985
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is breaking the build right now. Reapply once the correct headers are in place.
This reverts commit 406effd590.
Change-Id: I34b8717820ed58b462d4e7793711ee98fb8b882f
Reviewed-on: http://review.coreboot.org/11020
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix typo. Use the correct math helper int-lt.
Change-Id: Ia5e722020c75595dfcfb853ea8238fb8391f9a04
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10980
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
All \_PR entries needs to be changed from CPU# to CP##
so that it can support more cores.
BRANCH=none
BUG=chrome-os-partner:38734
TEST=build and boot cyan/strago boards.
Change-Id: I80a79ec8edbce46826140470645b7532ae361f91
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca269a7ffcd2ef16fcef93851e68c2d91104e3e1
Original-Change-Id: I48e73742dc3b11ee6e96f70bcd2d10d01609ad7c
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285700
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10991
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds support for binarypi based boards that have
to make adjustments to the memory configuration settings.
A PlatformMemoryConfiguration[] table that describes
the memory configuration must be defined in the
mainboard folder.
Change-Id: I5e4b476a4adf3dd1f3b7843274a81ecb243d10ab
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/10672
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The code for removing a file had its own merge routine. Use the generic one
instead.
Change-Id: I90ed007ab86f78a2728f529fa0143c5c1dfbbdc3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/10967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
So far it's still unused, but its purpose will change:
It will become an offset to another structure that contains additional file
attributes.
This change is compatible because the binary format doesn't change and so far
the field was always set to 0, which can serve nicely as 'unused' field.
Change-Id: I2dafb06866713d43a236556f9492641526270837
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This makes the Makefile more robust when changing the file name
or changing the .config outside of make *config
Change-Id: Ifc013cc3ef899a7846742a961261ac50bc67e27b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10970
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch adds support for the SuperSpeed half of USB 3.0 hubs, which
previously prevented SuperSpeed devices behind those hubs from working.
BRANCH=None
BUG=chrome-os-partner:39877
TEST=Played around with multiple hubs and devices on Oak and Falco, can
no longer find a combination that doesn't work.
Change-Id: I20815be95769e33d399b7ad91c3020687234e059
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3db96ece20d2304e7f6f6aa333cf114037c48a3e
Original-Change-Id: I2dd6c9c3607a24a7d78c308911e3d254d5f8d91d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284577
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: chunfeng yun <chunfeng.yun@mediatek.com>
Reviewed-on: http://review.coreboot.org/10958
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We have been trying to avoid reassigning previously used USB addresses
to different devices since CL:197420, because some devices seem to take
issue with that. Unfortunately, that patch doesn't affect XHCI: those
controllers insist on chosing addresses on their own. The only way to
prevent them from reusing a previously assigned address is to not
disable that slot at all.
This patch implements address reuse avoidance on XHCI by not disabling
slots when a device is detatched (which may occur both on physical
detachment or if we simply couldn't find a driver for that device).
Instead, we just release as many resources as we can for detached
devices (by dropping all endpoint contexts) and defer the final cleanup
until the point where the controller actually runs out of resources (a
point that we probably don't often reach in most firmware scenarios).
BRANCH=none
BUG=chrome-os-partner:42181
TEST=Booted an Oak plugged into a Servo without having a driver for the
SMSC network chip, observed that it could still enumerate the next
device afterwards. Kept unplugging/replugging stuff until the cleanup
triggered and made sure the controller still worked after that. Also
played around a bit on a Falco without issues.
Change-Id: Idfbab39abbc5bc5eff822bedf9c8d5bd4cad8cd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88c6bcbc41156729c3c38937c8a4adebc66f1ccb
Original-Change-Id: I0653a4f6a02c02498210a70ffdda9d986592813b
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284175
Original-Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10957
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Jonathan A. Kollasch