Commit Graph

32951 Commits

Author SHA1 Message Date
Julius Werner b38586f77f vboot: Remove hard dependency on MISSING_BOARD_RESET
Having a working board reset is certainly better when you're running
vboot (because otherwise you'll hang when transitioning into recovery
mode), but I don't think it should be strictly required, since it's
still somewhat usable without. This is particularly important for
certain test platforms that don't have a good way to reset but might
still be useful for vboot testing/prototyping.

Change-Id: Ia765f54b6e2e176e2d54478fb1e0839d8cab9849
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38417
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25 00:08:17 +00:00
Subrata Banik 86e0ac4755 soc/intel/skylake: Remove unused ICH memory reference
TEST=Build and boot EVE and Soraka to OS.

Change-Id: Ic7840ce264393b4a955f17b16f5e0f556e34a776
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38511
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-24 22:55:44 +00:00
Subrata Banik 21d79ad0d5 soc/intel/skylake: Move pci_irqs.asl from SA to PCH
SoC handles PCI IRQs programming inside PCH related ASL.

TEST=Build and boot EVE and Soraka to OS.

Change-Id: If95101193fa1b528dc64f57c0fc12f13f16d82b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-24 22:55:26 +00:00
John Su 8f18eb510c mb/google/drallion: Remove fixed IccMax values
Remove fixed IccMax values for U22 CPU.
IccMax will be selected by CPU SKU.

BUG=b:148110226
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
     Flashed to device and checked IccMax[1].

Change-Id: Ifcd31ad5b608ce599d4294a6522fdda022f8a177
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-01-24 22:55:07 +00:00
Wim Vervoorn 9eca4b15ff mb/portwell/m107: Remove mainboard sleepstates.asl
BUG=N/A
TEST=build

Change-Id: Ifb45bc1f7f4d3744124d6797fb4c791fd5f227ca
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-24 22:54:13 +00:00
Alex Levin 9bcdeb274a arch/x86/acpi_device: Add macros to define gpio interrupt with wake
Add Provides ACPI_GPIO_IRQ_LEVEL_[LOW|HIGH]_WAKE versions to allow board to define a gpio irq as wake capable.

Change-Id: I42f5084c5f0f5da0a4b39df77707b2f158bcc03d
Signed-off-by: Alex Levin <levinale@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-24 18:36:10 +00:00
Wonkyu Kim d250063c09 mb/intel/tglrvp: Enable SATA
Enable both SATA ports for TGLRVP.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-24 09:53:14 +00:00
Wonkyu Kim 815d96a975 soc/intel/tigerlake: Enable SATA
Configure SATA FSP UPD according to mainboard design.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-24 09:52:54 +00:00
Felix Held 8b3380044d Documentation: link asus p5q on mainboard page
Change-Id: Ia3f58cc15897bff87dd699ab1fb1c42545119f0b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-23 16:38:39 +00:00
Subrata Banik f8d9a13aba soc/intel/common: Update SA bit fields as per EDS
This patch updates system agent related registers bit definitions
as per EDS.

For example:
As per CNL/ICL EDS MCHBAR register base is between bit 16-38
but coreboot programming was not aligned with EDS previously.

CNL EDS doc number: 566216

Also provide provision to program 64bit values as per SA EDS definitions

TEST=Dump MCHBAR in coreboot and ASL shows same 32 bit value.

Change-Id: I37340408fe89c94ce81953c751c8d7e22bc81a42
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-23 05:06:12 +00:00
Wisley Chen 6476e41512 mb/google/hatch/var/dratini: Update DPTF parameters
1. Add a TEMP_SENSOR3
2. Update DFPS (fan performance state) table with values received
   from thermal team
3. Update PL1 override to 15W
4. Update PL2 override to 51W

BRANCH=hatch
BUG=b:147792204
TEST=build and verify by thermal team

Change-Id: I21c17c09a097c963f4dd1b7d5f8212c83a639dc3
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38025
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22 22:00:55 +00:00
Julius Werner a211298d20 Update vboot submodule to upstream master
Updating from commit id 2843aa62:
2019-12-12 Julius Werner   2lib: Move firmware body size reporting to
			   separate function

to commit id f5367d59:
2020-01-20 Joel Kitching   vboot: translate recovery reason info from
			   vboot 2->1

This brings in 27 new commits.

Change-Id: I7d33337881fa2d36d6e562b0a390b56227cfad55
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2020-01-22 22:00:46 +00:00
Nick Vaccaro ef8258a830 soc/intel/tigerlake: enable gpio dual route support
Enable SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT for tigerlake.

BUG=b:142961277, b:145494156
BRANCH=none
TEST=none

Change-Id: I1f785f410982f7d7598942f9b12196851e77c240
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37629
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22 22:00:33 +00:00
Tim Wawrzynczak 27db6c866c mb/google/hatch: Kohaku: Add MKBP to suspend wake events
This CL allows MKBP events from the EC to wake the system from suspend
states.

BUG=b:144122000
BRANCH=firmware-hatch-12672.B
TEST=Verify that MKBP events generated from EC will wake the system
from S0ix.

Change-Id: I8a0d2c7ed89fa1ea937a08c3082cc5d3e782efff
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-22 22:00:23 +00:00
Angel Pons d8eadffc7b superiotool: add IT8772F register dump
Values as per "IT8772E Preliminary Specification V0.4 (For F Version)".
Some values are unclear on this document, but is the only one I have.

Change-Id: I6d74984f453c47d6ec71963a7dcab961a22a5964
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-22 17:22:50 +00:00
Jett Rink 8db8a6154f ec/google/chromeec: add support for fw_config cbi field
The firmware configuration (fw_config) field is store in the CBI EEPROM
and it should be used to make firmware customization instead of
sku/variant id.

BUG=b:145519081
TEST=builds

Change-Id: I790998a29e724ecdff8876cca072267537b7cea6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-01-22 15:43:42 +00:00
Jett Rink ba2edaffdc ec/google/chromeec: update ec_commands.h
Copy ec_commands.h directly from Chromium OS EC repo at sha e57217a250.

This is needed for the FW_CONFIG CBI field definition.

Change-Id: Id010721033ebe32ac9c9482d666cf790442a26ee
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-01-22 15:43:40 +00:00
Srinidhi N Kaushik d801b1feb8 soc/intel/tigerlake: Update fsp_params for TGL
Add initial fsp upd settings for TGL, both romstage and ramstage upd's to
support basic build and boot of TGL RVP.
    - Add Silicon upd settings which includes
      * Serial IO/UART settings
      * Graphics settings
      * USB2/USB3 settings
    - Add Romstage upd settings which includes
      * Pcie Root port settings
      * IGD initialization
      * Hyper Threading settings
      * SMBus controller settings
      * Debug probe settings

BUG=none
BRANCH=none
TEST=Build and boot Tigerlake rvp board

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I16df66451fd3a681df1222d283d97dd6bdaff0e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37960
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22 15:43:12 +00:00
Ravi Sarawadi 9d678f2e56 soc/intel/tigerlake: Update GPIO config
GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups from coreboot so that they are mapped properly.
GPIO communities should be properly configured in GPIO_CFG and
MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured
in GPIO_CFG register while the PMC_GPP_* in pmc.h are used to
configure the MISCCFG registers.

BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board. Verified that after
     setting the gpe from devicetree the GPP_EN register for
     that community gets updated setting that specific bit.
     From the iotools i checked that GPE_EN register for that
     community is updated with that specific bit set to 1.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-22 15:42:44 +00:00
Tan, Lean Sheng 26136092c0 soc/intel/common: Add Elkhartlake Device IDs
Add Elkhartlake CPU, SA and PCH IDs.
EHL PCH is code named as MCC.
Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22 15:42:26 +00:00
Wonkyu Kim 8406179eff soc/intel/tigerlake: Update interrupt info
Update interrupt header and interrupt mapping per Intel Silcon reference code.
Need to match pci_irqs.asl with FSP setting which followed by PCH BIOS spec.

Reference
PCH BIOS spec#613495
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg
/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/PeiItssPolicyLibVer2.c

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iffc4efad4d0aa55fc0de88d7fe32c0356dbc3c60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38258
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22 15:42:12 +00:00
Wim Vervoorn 13471bc864 mb/facebook/fbg1701: Remove ACPI S4 support
Align the fbg1701 sleepstates implementation with monolith.

BUG=N/A
TEST=build

Change-Id: I3a715781bf51da41d6954463ad38ed94b0dfd217
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-22 15:41:18 +00:00
Wim Vervoorn b362938bef mb/facebook/monolith: Disable S3 and S4
The monolith board doesn't support the S3 and S4 states because of the
watchdog and failover mechanisms.

Remove S3 and S4 from the available sleepstates.

BUG=N/A
TEST=build

Change-Id: I01f67d8bb3f9e45caef748caca91eeb6859d7393
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-22 15:41:09 +00:00
Wim Vervoorn bccc7e7072 {soc,southbridge}/*/*/acpi: Add possibility to disable S4
Some boards don't support S3 or S4. The S4 state can't be removed from
the available sleep states.

Add a config item that allows removal of the S4 state from the list of
available sleep states. The S4 state can be removed by selecting the
item on board level.

For the AMD chipsets the SSFG mask is updated to remove the S4 state.

BUG=N/A
TEST=build

Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22 15:41:02 +00:00
Jamie Chen 951a6207f3 mb/google/puff: Add ac/dc loadline configuations
According to VRTT report, add ac/dc loadline configuations in puff device
tree.

BUG=b:147206535
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
     Flashed to puff and checked the log.
     All ac/dc loadline configs were set correctly.

Change-Id: Ia806de23a1fefcaac3ce9a462a8a04eee5eabcae
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-21 13:10:47 +00:00
Wisley Chen a5ce45b954 mb/google/hatch/var/jinlon: Remove DPTF fan control
Jinlon will use EC to control fan, so remove DPTF fan control.

BUG=b:141259174
TEST=emerge-hatch coreboot chromeos-bootimage

Change-Id: I8ada4fe72eee260fecf45d00510da8b91e3f10a4
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-21 13:10:19 +00:00
Peter Lemenkov e9e1c4048e mb/lenovo/t410/Kconfig: Don't select ONBOARD_VGA_IS_PRIMARY explicitly
ONBOARD_VGA_IS_PRIMARY is selected if board selects
DRIVERS_LENOVO_HYBRID_GRAPHICS.

See commit 35abe73e with Change-Id:
I6594fbb957c9a8135fe670d38b5755adf29d2dff ("mb/lenovo/t430: Fix Dual
Graphics").

Change-Id: I39687e5cd34979fd4318978f5aa46ac6cdf721e8
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-21 13:09:54 +00:00
Ivan Vatlin 0ebb7840e7 mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2
Signed-off-by: Ivan Vatlin <jenrus@tuta.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-21 13:06:39 +00:00
Michał Żygowski 16434322ed mb/pcengines/apu2/mainboard.c: Add SMBIOS type 16 and 17 entries
Use information provided by AGESA to fill the SMBIOS memory tables.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I45bb2fc36cf0c01670e9fc8559d3a6183ea271f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-21 13:06:17 +00:00
Mike Banon 33768dd08b biostar/a68n_5200: Switch away from ROMCC_BOOTBLOCK
Following the example of change CB:37737 (ee8f969).
Switching was done by moving a SIO configuration and
the clocks setup from 'romstage.c' to 'bootblock.c'.

Tested-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Change-Id: I2e710ac61843c09a055523c7971e4c05bae56a37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-21 10:57:19 +00:00
Edward O'Callaghan 73692e8b77 mainboard/hatch: Fix puff USB ACPI names and types
Fix devicetree to advertise the correct USB names and types
in the generated ASL.

BUG=b:146437991
BRANCH=none
TEST=booted and inspected the reported generated ASL.

Change-Id: I133b4db444f9a5f0a36d8e976ae490f24cf307d8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-01-21 04:22:35 +00:00
Marshall Dawson d125593b2e soc/amd/picasso: Add SMMSTORE support
Add SMMSTORE support for saving EFI NVRAM variables in
conjuction with Tianocore payload.

Test: none, as this duplicates tested functionality in
amd/stoneyridge.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Id05b33edf949611c3f9eac94e7b63a4266c6c4d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20 22:15:14 +00:00
Marshall Dawson 80556ec247 drivers/smmstore: Clarify Kconfig cbfs wording
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ibb37c2d99c1a95b1d37bec784c98e636da4836d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38470
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20 17:40:26 +00:00
Idwer Vollering a682fc81ae util/amdfwtool: guard typedef aliases
Build tested on Ubuntu 18 LTS, FreeBSD.

Change-Id: Ida2c1f36aba7469d69dbb12ee6afce4a181bd6b7
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20 14:43:31 +00:00
Idwer Vollering 724753d472 util/cbmem: simplify include lines in Makefile
Change-Id: I3d0ab7dacb5facb7dd14dd471cd0fb9f06bf0e37
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20 14:40:27 +00:00
Patrick Georgi 186c2f9abc util/nvramtool: Create nvramtool object directories earlier
The existing rule created a potential race condition between creating
the directory and putting files in there, so use our existing
infrastructure for directory creation instead.

Change-Id: If52a9f558c7d9ce85f71ba53232594699c9d357a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37798
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20 14:31:29 +00:00
Maciej Matuszczyk d76947f13b mb/lenovo/x201: Support undock button on X200 ultrabase
Only the ACPI code needs to be extended, as smihandler.c already
supported it. The _Q50 Method is just _Q18 with changed name.

On Linux, pressing the undock button does nothing, so the only safe
way to undock is to press Fn+F9. With this patch, when the undock
button is pressed, the green LED lights up, and undocking is safe.

Change-Id: Iaaecad031bb1f39dd1a778d0c8eaea6bce9e0f57
Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38446
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20 14:20:18 +00:00
Piotr Kleinschmidt 302951d9c3 mb/pcengines/*: enable simple IO-based GPIO control
Add Nuvoton NCT5104D GPIO IO VLDN and define an IO base address
unused by any peripheral for GPIO use.

Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I034c5d0169b8d97eac97a20c92c22816fd674f79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-20 11:10:20 +00:00
Piotr Kleinschmidt 79d7f6b5fc superio/nuvoton/nct5104d: Add virtual LDN for simple GPIO IO control
Now, Super I/O GPIOs can also be controlled directly through
access to I/O registers. VLDN 108 and specific I/O port from a range
<100h; ff8h> may be enabled in mainboard devicetree.

Change-Id: I4ce99bb44e6f5db684170f4190bdc38a944849f6
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35849
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20 11:09:57 +00:00
Wim Vervoorn aa1eff3031 mb/facebook/monolith: Drop PWRB device
The mainboard ASL code contained a power button definition. This is not
required as the system uses the standard ACPI power button.

Remove the PWRB device from ASL.

BUG=N/A
TEST=tested using fwts on a facebook monolith.

Found-by: fwts 19.12.00
Change-Id: I25a842539ee2e8febc8a1ae88843a71ccb4ee68e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38133
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20 10:56:16 +00:00
Wim Vervoorn e181dd164b {mb/facebook/fbg1701,mb/portwell/m107}: Drop PWRB device
The mainboard ASL code contained a power button definition. This is not
required as the system uses the standard ACPI power button.

Remove the PWRB device from ASL.

BUG=N/A
TEST=build

Found-by: fwts 19.12.00
Change-Id: I4fac1411fd99475551bc970818759649f80b3f0e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38134
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20 10:56:02 +00:00
Felix Held c83b9783d4 Documentation/superio: add generic PNP device documentation
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-20 10:54:56 +00:00
Matt DeVillier 9cc1603173 soc/amd/stoneyridge: Add SMMSTORE support
Add SMMSTORE support for saving EFI NVRAM variables in
conjunction with Tianocore payload.

Test: build/boot several google/kahlee variants, test
manipulation and persistence of Tianocore bootorder variables.

Change-Id: Ida604a44d1fa5288e96dbe05de1f847e597cc95d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-20 10:50:06 +00:00
Wim Vervoorn 05bc9b38a3 util/ifdtool: Correct region resize handling
When regions are resized they are always aligned to the top of the
region. For the BIOS region this is correct. The other regions however
should be aligned to the bottom of the region.

Update the region handling to only align BIOS region to top of region.

BUG=N/A
TEST=verified image resize

Change-Id: Ied0e763b5335f5f124fc00de38e5db1a4d0f6785
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-20 10:49:12 +00:00
Angel Pons 42d300533e mb/hp/snb_ivb_laptops: Switch to overridetree setup
NOTE: The ME interface was disabled on folio_9470m and revolve_810_g1.
It is assumed that they were ported while the ME was in an abnormal
state (usually due to me_cleaner usage), and that it should be enabled.
In any case, the MEI device is hidden if the ME fails to boot already.

Change-Id: Ibf32a034653946f49f72a2c19c41a4033964ef83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20 09:02:19 +00:00
Angel Pons ba9e482a36 mb/hp/revolve_810_g1: Transform into variant
Update Makefile.inc so as to add the SPD data when needed. Tested
building other variants, no spd.bin gets added because they don't select
GENERIC_SPD_BIN.

Tested with BUILD_TIMELESS=1, binary does not change.

Change-Id: I0cda3f839baa227ce6a4b8f0510934125e5afb59
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20 09:02:01 +00:00
Angel Pons 650a56f7bb mb/hp/folio_9470m: Transform into variant
Tested with BUILD_TIMELESS=1, binary does not change.

Change-Id: I65696c5739469b33253c22c1d5a65cc31ef3a421
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20 09:01:50 +00:00
Angel Pons 533e4399f1 mb/hp/8770w: Transform into variant
Since this board does not have integrated graphics, do not install the
INT15 handler if it is not selected in Kconfig.

NOTE: Since cmos options are not very flexible, this board ends up with
a spurious gfx_uma_size option. Other than that, everything is the same.

Tested with BUILD_TIMELESS=1, binary does not change when ignoring the
cmos options.

Change-Id: I2ebcfd5160773bf98a3d23e797a89e290063d112
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20 09:01:35 +00:00
Angel Pons e4faf5a209 mb/hp/8470p: Transform into variant
Tested with BUILD_TIMELESS=1, binary does not change.

Change-Id: I6dbecb0b4d38ed4af8966f5391fce1f2c9c5d182
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20 09:01:22 +00:00
Angel Pons 5aee8262d5 mb/hp/8460p: Transform into variant
Tested with BUILD_TIMELESS=1, binary does not change.

Change-Id: I17b6ac9ac2433b760e125a1ce708d3b422b632b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-20 09:00:55 +00:00